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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_single.v
 
INCLUDE def_axi_master.txt
 
module PREFIX_single(PORTS);
 
   parameter                           MASTER_NUM  = 0;
   parameter                           MASTER_ID   = 0;
   parameter                           MASTER_PEND = 0;
 
`include "prgen_rand.v"
 
   parameter                           MAX_CMDS    = 16; //Depth of command FIFO
   parameter                           DATA_LOG    = LOG2(EXPR(DATA_BITS/8));
   parameter                           PEND_BITS   =
                                       (MAX_CMDS <= 16)  ? 4 :
                                       (MAX_CMDS <= 32)  ? 5 :
                                       (MAX_CMDS <= 64)  ? 6 :
                                       (MAX_CMDS <= 128) ? 7 :
                                       (MAX_CMDS <= 256) ? 8 :
                                       (MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal
 
 
 
   input                               clk;
   input                               reset;
 
   port                                GROUP_STUB_AXI;
 
   output                              idle;
   output                              scrbrd_empty;
 
 
 
   //random parameters   
   integer                             GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
 
   reg                                 AWVALID_pre;
   reg                                 WVALID_pre;
   wire                                BREADY_pre;
   reg                                 ARVALID_pre;
   wire                                RREADY_pre;
 
   reg                                 enable = 0;
   reg                                 rd_enable = 0;
   reg                                 wr_enable = 0;
   reg                                 wait_for_write = 0;
 
   reg                                 scrbrd_enable = 0;
   reg [LEN_BITS-1:0]                   wvalid_cnt;
 
   reg                                 rd_cmd_push = 0;
   wire                                rd_cmd_pop;
   wire [PEND_BITS:0]                  rd_cmd_fullness;
   wire                                rd_cmd_empty;
   wire                                rd_cmd_full;
   reg [ADDR_BITS-1:0]                  rd_cmd_addr_in;
   reg [LEN_BITS-1:0]                   rd_cmd_len_in;
   reg [SIZE_BITS-1:0]                  rd_cmd_size_in;
   wire [ADDR_BITS-1:0]         rd_cmd_addr;
   wire [LEN_BITS-1:0]                  rd_cmd_len;
   wire [SIZE_BITS-1:0]         rd_cmd_size;
 
   reg                                 rd_resp_push = 0;
   wire                                rd_resp_pop;
   wire                                rd_resp_empty;
   wire                                rd_resp_full;
   reg [ADDR_BITS-1:0]                  rd_resp_addr_in;
   reg [SIZE_BITS-1:0]                  rd_resp_size_in;
   wire [ADDR_BITS-1:0]         rd_resp_addr;
   wire [SIZE_BITS-1:0]         rd_resp_size;
 
   reg                                 wr_cmd_push = 0;
   wire                                wr_cmd_pop;
   wire [PEND_BITS:0]                  wr_cmd_fullness;
   wire                                wr_cmd_empty;
   wire                                wr_cmd_full;
   reg [ADDR_BITS-1:0]                  wr_cmd_addr_in;
   reg [LEN_BITS-1:0]                   wr_cmd_len_in;
   reg [SIZE_BITS-1:0]                  wr_cmd_size_in;
   wire [ADDR_BITS-1:0]         wr_cmd_addr;
   wire [LEN_BITS-1:0]                  wr_cmd_len;
   wire [SIZE_BITS-1:0]         wr_cmd_size;
 
   reg                                 wr_data_push = 0;
   wire                                wr_data_pop;
   wire [PEND_BITS:0]                  wr_data_fullness;
   wire                                wr_data_empty;
   wire                                wr_data_full;
   reg [ADDR_BITS-1:0]                  wr_data_addr_in;
   reg [LEN_BITS-1:0]                   wr_data_len_in;
   reg [SIZE_BITS-1:0]                  wr_data_size_in;
   wire [ADDR_BITS-1:0]         wr_data_addr;
   wire [LEN_BITS-1:0]                  wr_data_len;
   wire [SIZE_BITS-1:0]         wr_data_size;
   wire [DATA_BITS/8-1:0]               wr_data_strb;
   wire [7:0]                           wr_data_bytes;
   wire [ADDR_BITS-1:0]         wr_data_addr_prog;
   wire [7:0]                           wr_data_offset;
 
   wire                                wr_resp_push;
   reg                                 wr_resp_pop = 0;
   wire                                wr_resp_empty;
   wire                                wr_resp_full;
   wire [1:0]                          wr_resp_resp_in;
   wire [1:0]                          wr_resp_resp;
 
   reg                                 wr_fifo_push = 0;
   wire                                wr_fifo_pop;
   wire                                wr_fifo_empty;
   wire                                wr_fifo_full;
   reg [DATA_BITS-1:0]                 wr_fifo_data_in;
   wire [DATA_BITS-1:0]                wr_fifo_data;
 
   wire                                rd_fifo_push;
   reg                                 rd_fifo_pop = 0;
   wire                                rd_fifo_empty;
   wire                                rd_fifo_full;
   wire [DATA_BITS-1:0]                rd_fifo_data_in;
   wire [1:0]                          rd_fifo_resp_in;
   wire [DATA_BITS-1:0]                rd_fifo_data;
   wire [1:0]                          rd_fifo_resp;
 
   reg                                 scrbrd_push = 0;
   reg                                 scrbrd_pop = 0;
   wire                                scrbrd_empty;
   wire                                scrbrd_full;
   reg [ADDR_BITS-1:0]                 scrbrd_addr_in;
   reg [DATA_BITS-1:0]                 scrbrd_data_in;
   reg [DATA_BITS-1:0]                 scrbrd_mask_in;
   wire [ADDR_BITS-1:0]                scrbrd_addr;
   wire [DATA_BITS-1:0]                scrbrd_data;
   wire [DATA_BITS-1:0]                scrbrd_mask;
 
   integer                             wr_fullness;
   integer                             rd_fullness;
   integer                             rd_completed;
   integer                             wr_completed;
   integer                             wr_pend_max = MASTER_PEND;
   integer                             rd_pend_max = MASTER_PEND;
   wire                                wr_hold;
   wire                                rd_hold;
 
   integer                             rand_chk_num = 0;
 
 
   assign                              idle = rd_cmd_empty & rd_resp_empty & wr_cmd_empty & wr_data_empty & wr_resp_empty;
 
   always @(rand_chk_num)
     if (rand_chk_num > 0)
       insert_rand_chk_loop(rand_chk_num);
 
   always @(posedge enable)
     begin
        @(posedge clk);
        wr_enable = 1;
        repeat (50) @(posedge clk);
        rd_enable = 1;
     end
 
   //for incremental data
   reg [DATA_BITS-1:0]                 base_data = 0;
   integer                             ww;
   initial
     begin
        ww=0;
        while (ww < DATA_BITS/8)
          begin
             base_data = base_data + ((MASTER_NUM + ww) << (ww*8));
             ww = ww + 1;
          end
     end
 
   assign         rd_cmd_pop   = ARVALID & ARREADY;
   assign         rd_resp_pop  = RVALID & RREADY & RLAST;
   assign         rd_fifo_push = RVALID & RREADY;
   assign         wr_cmd_pop   = AWVALID & AWREADY;
   assign         wr_data_pop  = WVALID & WREADY & WLAST;
   assign         wr_fifo_pop  = WVALID & WREADY;
   assign         wr_resp_push = BVALID & BREADY;
 
   assign         RREADY_pre = 1;
   assign         BREADY_pre = 1;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       AWVALID_pre <= #FFD 1'b0;
     else if ((wr_cmd_fullness == 1) & wr_cmd_pop)
       AWVALID_pre <= #FFD 1'b0;
     else if ((!wr_cmd_empty) & wr_enable)
       AWVALID_pre <= #FFD 1'b1;
 
 
   assign         AWADDR  = wr_cmd_addr;
   assign         AWLEN   = wr_cmd_len;
   assign         AWSIZE  = wr_cmd_size;
   assign         AWID    = MASTER_ID;
   assign         AWBURST = 2'd1; //INCR only
   assign         AWCACHE = 4'd0; //not supported
   assign         AWPROT  = 4'd0; //not supported
   assign         AWLOCK  = 2'd0; //not supported
 
   always @(posedge clk or posedge reset)
     if (reset)
       ARVALID_pre <= #FFD 1'b0;
     else if (((rd_cmd_fullness == 1)) & rd_cmd_pop)
       ARVALID_pre <= #FFD 1'b0;
     else if ((!rd_cmd_empty) & rd_enable)
       ARVALID_pre <= #FFD 1'b1;
 
   assign         ARADDR  = rd_cmd_addr;
   assign         ARLEN   = rd_cmd_len;
   assign         ARSIZE  = rd_cmd_size;
   assign         ARID    = MASTER_ID;
   assign         ARBURST = 2'd1; //INCR only
   assign         ARCACHE = 4'd0; //not supported
   assign         ARPROT  = 4'd0; //not supported
   assign         ARLOCK  = 2'd0; //not supported
 
   assign         rd_fifo_data_in = RDATA;
   assign         rd_fifo_resp_in = BRESP;
 
   assign         wr_data_bytes = 1'b1 << wr_data_size;
 
   assign         wr_data_strb =
                  wr_data_size == 'd0 ? 1'b1       :
                  wr_data_size == 'd1 ? 2'b11      :
                  wr_data_size == 'd2 ? 4'b1111    :
                  wr_data_size == 'd3 ? {8{1'b1}}  :
                  wr_data_size == 'd4 ? {16{1'b1}} : 'd0;
 
   assign         wr_data_addr_prog = wr_data_addr + (wvalid_cnt * wr_data_bytes);
 
   always @(posedge clk or posedge reset)
     if (reset)
       WVALID_pre <= #FFD 1'b0;
     else if ((wr_data_fullness == 1) & wr_data_pop)
       WVALID_pre <= #FFD 1'b0;
     else if ((!wr_data_empty) & wr_enable)
       WVALID_pre <= #FFD 1'b1;
 
 
   assign         wr_data_offset = wr_data_addr_prog[DATA_LOG-1:0];
 
   assign         WID   = MASTER_ID;
   assign         WDATA = wr_fifo_empty ? 0 : wr_fifo_data;
   assign         WSTRB = wr_data_strb << wr_data_offset;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       wvalid_cnt <= #FFD {LEN_BITS{1'b0}};
     else if (wr_data_pop)
       wvalid_cnt <= #FFD {LEN_BITS{1'b0}};
     else if (WVALID & WREADY)
       wvalid_cnt <= #FFD wvalid_cnt + 1'b1;
 
   assign         WLAST = WVALID & (wvalid_cnt == wr_data_len);
 
   assign         wr_resp_resp_in = BRESP;
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          wr_fullness <= #FFD 0;
          rd_fullness <= #FFD 0;
          rd_completed <= #FFD 0;
          wr_completed <= #FFD 0;
       end
     else
       begin
          wr_fullness <= #FFD wr_fullness + wr_cmd_pop - wr_resp_push;
          rd_fullness <= #FFD rd_fullness + rd_cmd_pop - rd_resp_pop;
          rd_completed <= #FFD rd_completed + rd_resp_pop;
          wr_completed <= #FFD wr_completed + wr_resp_push;
       end
 
   assign         wr_hold = wr_fullness >= wr_pend_max;
   assign         rd_hold = (rd_fullness >= rd_pend_max) | (wait_for_write & (wr_completed <= rd_completed + rd_fullness));
 
 
 
   task insert_rd_cmd;
      input [ADDR_BITS-1:0]  addr;
      input [LEN_BITS-1:0]   len;
      input [SIZE_BITS-1:0]  size;
 
      begin
         rd_cmd_addr_in  = addr;
         rd_cmd_len_in   = len;
         rd_cmd_size_in  = size;
         rd_resp_addr_in = addr;
         rd_resp_size_in = size;
 
         if (rd_cmd_full) enable = 1; //start stub not started yet
 
         wait ((!rd_cmd_full) & (!rd_resp_full));
         @(negedge clk); #FFD;
         rd_cmd_push  = 1;
         rd_resp_push = 1;
         @(posedge clk); #FFD;
         rd_cmd_push  = 0;
         rd_resp_push = 0;
      end
   endtask
 
   task insert_wr_cmd;
      input [ADDR_BITS-1:0]  addr;
      input [LEN_BITS-1:0]   len;
      input [SIZE_BITS-1:0]  size;
 
      begin
         wr_cmd_addr_in  = addr;
         wr_cmd_len_in   = len;
         wr_cmd_size_in  = size;
         wr_data_addr_in = addr;
         wr_data_len_in  = len;
         wr_data_size_in = size;
 
         if (wr_cmd_full) enable = 1; //start stub not started yet
 
         wait ((!wr_cmd_full) & (!wr_data_full));
         @(negedge clk); #FFD;
         wr_cmd_push  = 1;
         wr_data_push = 1;
         @(posedge clk); #FFD;
         wr_cmd_push  = 0;
         wr_data_push = 0;
      end
   endtask
 
   task insert_wr_data;
      input [DATA_BITS-1:0]  wdata;
 
      begin
         wr_fifo_data_in  = wdata;
 
         wait (!wr_fifo_full);
         @(negedge clk); #FFD;
         wr_fifo_push = 1;
         @(posedge clk); #FFD;
         wr_fifo_push = 0;
      end
   endtask
 
   task insert_wr_incr_data;
      input [ADDR_BITS-1:0]  addr;
      input [LEN_BITS-1:0]   len;
      input [SIZE_BITS-1:0]  size;
 
      integer valid_cnt;
      integer wdata_cnt;
      reg [7:0] data_cnt;
      integer bytes;
      reg [DATA_BITS-1:0] add_data;
      reg [DATA_BITS-1:0] next_data;
      begin
         //insert data
         valid_cnt = 0;
         while (valid_cnt <= len)
           begin
              bytes = 1'b1 << size;
              wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
              data_cnt  = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
              add_data  = {DATA_BITS/8{data_cnt}};
              next_data = base_data + add_data;
              insert_wr_data(next_data);
              valid_cnt = valid_cnt+1;
           end
         //insert command
         insert_wr_cmd(addr, len, size);
      end
   endtask
 
   task insert_scrbrd;
      input [ADDR_BITS-1:0]  addr;
      input [DATA_BITS-1:0]  data;
      input [DATA_BITS-1:0]  mask;
      begin
         scrbrd_enable = 1;
         scrbrd_addr_in  = addr;
         scrbrd_data_in  = data;
         scrbrd_mask_in  = mask;
 
         wait (!scrbrd_full);
         @(negedge clk); #FFD;
         scrbrd_push = 1;
         @(posedge clk); #FFD;
         scrbrd_push = 0;
      end
   endtask
 
   task insert_scrbrd_incr_data;
      input [ADDR_BITS-1:0]  addr;
      input [LEN_BITS-1:0]   len;
      input [SIZE_BITS-1:0]  size;
 
      integer valid_cnt;
      integer wdata_cnt;
      reg [7:0] data_cnt;
      integer bytes;
      reg [DATA_BITS-1:0] add_data;
      reg [DATA_BITS-1:0] next_data;
      reg [DATA_BITS:0] strb;
      reg [DATA_BITS-1:0] mask;
      reg [ADDR_BITS-1:0] next_addr;
      begin
         valid_cnt = 0;
         while (valid_cnt <= len)
           begin
              bytes = 1'b1 << size;
              wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);
              data_cnt  = ((wdata_cnt)/(DATA_BITS/(bytes*8))) * (DATA_BITS/8);
              add_data  = {DATA_BITS/8{data_cnt}};
              next_data = base_data + add_data;
              next_addr = addr + (bytes * valid_cnt);
              strb = (1 << (bytes*8)) - 1;
              mask = strb << (next_addr[DATA_LOG-1:0]*8);
              insert_scrbrd(next_addr, next_data, mask);
              valid_cnt = valid_cnt+1;
           end
      end
   endtask
 
   task insert_rd_scrbrd;
      input [ADDR_BITS-1:0]  addr;
      input [LEN_BITS-1:0]   len;
      input [SIZE_BITS-1:0]  size;
 
      begin
         insert_scrbrd_incr_data(addr, len, size);
         insert_rd_cmd(addr, len, size);
      end
   endtask
 
   task insert_wr_rd_scrbrd;
      input [ADDR_BITS-1:0]  addr;
      input [LEN_BITS-1:0]   len;
      input [SIZE_BITS-1:0]  size;
 
      begin
         wait_for_write=1;
         insert_wr_incr_data(addr, len, size);
         insert_rd_scrbrd(addr, len, size);
      end
   endtask
 
   task insert_wr_rd_scrbrd_rand;
      reg [ADDR_BITS-1:0]  addr;
      reg [LEN_BITS-1:0]   len;
      reg [SIZE_BITS-1:0]  size;
 
      begin
         len   = rand(len_min, len_max);
         size  = rand(size_min, size_max);
         addr  = rand_align(addr_min, addr_max, 1 << size);
         insert_wr_rd_scrbrd(addr, len, size);
      end
   endtask
 
   task insert_rand_chk;
      input [31:0]  num;
 
      rand_chk_num = num;
   endtask
 
   task insert_rand_chk_loop;
      input [31:0]  num;
 
      integer i;
      begin
         i = 0;
         while (i < num)
           begin
              insert_wr_rd_scrbrd_rand;
              i = i + 1;
           end
      end
   endtask
 
   task insert_wr_single;
      input [ADDR_BITS-1:0]  addr;
      input [DATA_BITS-1:0]  wdata;
 
      reg [SIZE_BITS-1:0] size;
      begin
         size = EXPR((DATA_BITS/32)+1);
         insert_wr_data(wdata);
         insert_wr_cmd(addr, 0, size);
      end
   endtask
 
   task get_rd_resp;
      output [DATA_BITS-1:0] rdata;
      output [1:0] resp;
 
      reg [DATA_BITS-1:0] rdata;
      reg [1:0] resp;
      begin
         wait (!rd_fifo_empty);
         rdata = rd_fifo_data;
         resp = rd_fifo_resp;
         @(negedge clk); #FFD;
         rd_fifo_pop = 1;
         @(posedge clk); #FFD;
         rd_fifo_pop = 0;
      end
   endtask
 
   task get_scrbrd;
      output [ADDR_BITS-1:0] addr;
      output [DATA_BITS-1:0] rdata;
      output [DATA_BITS-1:0] mask;
 
      reg [ADDR_BITS-1:0] addr;
      reg [DATA_BITS-1:0] rdata;
      reg [DATA_BITS-1:0] mask;
      begin
         wait (!scrbrd_empty);
         addr = scrbrd_addr;
         rdata = scrbrd_data;
         mask = scrbrd_mask;
         @(negedge clk); #FFD;
         scrbrd_pop = 1;
         @(posedge clk); #FFD;
         scrbrd_pop = 0;
      end
   endtask
 
   task get_wr_resp;
      output [1:0] resp;
 
      reg [1:0] resp;
      begin
         wait (!wr_resp_empty);
         resp = wr_resp_resp;
         @(negedge clk); #FFD;
         wr_resp_pop = 1;
         @(posedge clk); #FFD;
         wr_resp_pop = 0;
      end
   endtask
 
   task insert_rd_single;
      input [ADDR_BITS-1:0]  addr;
 
      reg [SIZE_BITS-1:0] size;
      begin
         size = EXPR((DATA_BITS/32)+1);
         insert_rd_cmd(addr, 0, size);
      end
   endtask
 
   task read_single_ack;
      input [ADDR_BITS-1:0]  addr;
      output [DATA_BITS-1:0] rdata;
      output [1:0]           resp;
 
      reg [1:0] resp;
      begin
         insert_rd_single(addr);
         get_rd_resp(rdata, resp);
      end
   endtask
 
   task write_single_ack;
      input [ADDR_BITS-1:0]  addr;
      input [DATA_BITS-1:0]  wdata;
      output [1:0]           resp;
 
      reg [1:0] resp;
      begin
         insert_wr_single(addr, wdata);
         get_wr_resp(resp);
      end
   endtask
 
   task read_single;
      input [ADDR_BITS-1:0]  addr;
      output [DATA_BITS-1:0] rdata;
 
      reg [1:0] resp;
      begin
         read_single_ack(addr, rdata, resp);
      end
   endtask
 
   task write_single;
      input [ADDR_BITS-1:0]  addr;
      input [DATA_BITS-1:0]  wdata;
 
      reg [1:0] resp;
      begin
         write_single_ack(addr, wdata, resp);
      end
   endtask
 
   task chk_scrbrd;
      reg [ADDR_BITS-1:0] addr;
      reg [DATA_BITS-1:0] mask;
      reg [DATA_BITS-1:0] expected_data;
      reg [DATA_BITS-1:0] rdata;
      reg [DATA_BITS-1:0] rdata_masked;
      reg [1:0] resp;
 
      begin
         if (!wr_resp_empty) get_wr_resp(resp);
         get_scrbrd(addr, expected_data, mask);
         get_rd_resp(rdata, resp);
         expected_data = expected_data & mask; //TBD insert z as dontcare (for print)
         rdata_masked = rdata & mask;
 
         if (expected_data !== rdata_masked)
           $display("MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);
      end
   endtask
 
   always @(posedge scrbrd_enable)
     begin
        while (scrbrd_enable)
          begin
             chk_scrbrd;
          end
     end
 
 
CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
   prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)
   rd_cmd_list(
               .clk(clk),
               .reset(reset),
               .push(rd_cmd_push),
               .pop(rd_cmd_pop),
               .din({
                     rd_cmd_size_in,
                     rd_cmd_len_in,
                     rd_cmd_addr_in
                     }),
               .dout({
                      rd_cmd_size,
                      rd_cmd_len,
                      rd_cmd_addr
                      }),
               .fullness(rd_cmd_fullness),
               .empty(rd_cmd_empty),
               .full(rd_cmd_full)
               );
 
   prgen_fifo_stub #(ADDR_BITS+SIZE_BITS, MAX_CMDS)
   rd_resp_list(
                .clk(clk),
                .reset(reset),
                .push(rd_resp_push),
                .pop(rd_resp_pop),
                .din({
                      rd_resp_addr_in,
                      rd_resp_size_in
                      }),
                .dout({
                       rd_resp_addr,
                       rd_resp_size
                       }),
                .empty(rd_resp_empty),
                .full(rd_resp_full)
                );
 
   prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)
   wr_cmd_list(
               .clk(clk),
               .reset(reset),
               .push(wr_cmd_push),
               .pop(wr_cmd_pop),
               .din({
                     wr_cmd_size_in,
                     wr_cmd_len_in,
                     wr_cmd_addr_in
                     }),
               .dout({
                      wr_cmd_size,
                      wr_cmd_len,
                      wr_cmd_addr
                      }),
               .fullness(wr_cmd_fullness),
               .empty(wr_cmd_empty),
               .full(wr_cmd_full)
               );
 
   prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)
   wr_data_list(
                .clk(clk),
                .reset(reset),
                .push(wr_data_push),
                .pop(wr_data_pop),
                .din({
                      wr_data_size_in,
                      wr_data_len_in,
                      wr_data_addr_in
                      }),
                .dout({
                       wr_data_size,
                       wr_data_len,
                       wr_data_addr
                       }),
                .fullness(wr_data_fullness),
                .empty(wr_data_empty),
                .full(wr_data_full)
                );
 
   prgen_fifo_stub #(2, MAX_CMDS)
   wr_resp_list(
                .clk(clk),
                .reset(reset),
                .push(wr_resp_push),
                .pop(wr_resp_pop),
                .din(wr_resp_resp_in),
                .dout(wr_resp_resp),
                .empty(wr_resp_empty),
                .full(wr_resp_full)
                );
 
 
   prgen_fifo_stub #(DATA_BITS, MAX_CMDS*EXPR(2^LEN_BITS))
   wr_data_fifo(
                .clk(clk),
                .reset(reset),
                .push(wr_fifo_push),
                .pop(wr_fifo_pop),
                .din(wr_fifo_data_in),
                .dout(wr_fifo_data),
                .empty(wr_fifo_empty),
                .full(wr_fifo_full)
                );
 
   prgen_fifo_stub #(DATA_BITS+2, MAX_CMDS*EXPR(2^LEN_BITS))
   rd_data_fifo(
                .clk(clk),
                .reset(reset),
                .push(rd_fifo_push),
                .pop(rd_fifo_pop),
                .din({
                      rd_fifo_data_in,
                      rd_fifo_resp_in
                      }),
                .dout({
                       rd_fifo_data,
                       rd_fifo_resp
                       }),
                .empty(rd_fifo_empty),
                .full(rd_fifo_full)
                );
 
   prgen_fifo_stub #(ADDR_BITS+2*DATA_BITS, MAX_CMDS*EXPR(2^LEN_BITS))
   scrbrd_fifo(
                .clk(clk),
                .reset(reset),
                .push(scrbrd_push),
                .pop(scrbrd_pop),
               .din({
                     scrbrd_addr_in,
                     scrbrd_data_in,
                     scrbrd_mask_in
                     }),
                .dout({
                       scrbrd_addr,
                       scrbrd_data,
                       scrbrd_mask
                       }),
                .empty(scrbrd_empty),
                .full(scrbrd_full)
                );
 
 
CREATE axi_master_stall.v
   PREFIX_stall
     PREFIX_stall (
                       .clk(clk),
                       .reset(reset),
 
                       .rd_hold(rd_hold),
                       .wr_hold(wr_hold),
 
                       .ARVALID_pre(ARVALID_pre),
                       .RREADY_pre(RREADY_pre),
                       .AWVALID_pre(AWVALID_pre),
                       .WVALID_pre(WVALID_pre),
                       .BREADY_pre(BREADY_pre),
 
                       .ARREADY(ARREADY),
                       .AWREADY(AWREADY),
                       .WREADY(WREADY),
 
                       .ARVALID(ARVALID),
                       .RREADY(RREADY),
                       .AWVALID(AWVALID),
                       .WVALID(WVALID),
                       .BREADY(BREADY)
                       );
 
 
endmodule
 
 

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[/] [axi_master/] [trunk/] [src/] [base/] [axi_master_single.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	eyalhoc	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28			`/////////////////////////////////////////////////////////////////////`
29
30			`OUTFILE PREFIX_single.v`
31
32			`INCLUDE def_axi_master.txt`
33
34			`module PREFIX_single(PORTS);`
35
36			`parameter MASTER_NUM = 0;`
37			`parameter MASTER_ID = 0;`
38			`parameter MASTER_PEND = 0;`
39
40			`include "prgen_rand.v"
41
42			`parameter MAX_CMDS = 16; //Depth of command FIFO`
43			`parameter DATA_LOG = LOG2(EXPR(DATA_BITS/8));`
44			`parameter PEND_BITS =`
45			`(MAX_CMDS <= 16) ? 4 :`
46			`(MAX_CMDS <= 32) ? 5 :`
47			`(MAX_CMDS <= 64) ? 6 :`
48			`(MAX_CMDS <= 128) ? 7 :`
49			`(MAX_CMDS <= 256) ? 8 :`
50			`(MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal`
51
52
53
54			`input clk;`
55			`input reset;`
56
57			`port GROUP_STUB_AXI;`
58
59			`output idle;`
60			`output scrbrd_empty;`
61
62
63
64			`//random parameters`
65			`integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;`
66
67			`reg AWVALID_pre;`
68			`reg WVALID_pre;`
69			`wire BREADY_pre;`
70			`reg ARVALID_pre;`
71			`wire RREADY_pre;`
72
73			`reg enable = 0;`
74			`reg rd_enable = 0;`
75			`reg wr_enable = 0;`
76			`reg wait_for_write = 0;`
77
78			`reg scrbrd_enable = 0;`
79			`reg [LEN_BITS-1:0] wvalid_cnt;`
80
81			`reg rd_cmd_push = 0;`
82			`wire rd_cmd_pop;`
83			`wire [PEND_BITS:0] rd_cmd_fullness;`
84			`wire rd_cmd_empty;`
85			`wire rd_cmd_full;`
86			`reg [ADDR_BITS-1:0] rd_cmd_addr_in;`
87			`reg [LEN_BITS-1:0] rd_cmd_len_in;`
88			`reg [SIZE_BITS-1:0] rd_cmd_size_in;`
89			`wire [ADDR_BITS-1:0] rd_cmd_addr;`
90			`wire [LEN_BITS-1:0] rd_cmd_len;`
91			`wire [SIZE_BITS-1:0] rd_cmd_size;`
92
93			`reg rd_resp_push = 0;`
94			`wire rd_resp_pop;`
95			`wire rd_resp_empty;`
96			`wire rd_resp_full;`
97			`reg [ADDR_BITS-1:0] rd_resp_addr_in;`
98			`reg [SIZE_BITS-1:0] rd_resp_size_in;`
99			`wire [ADDR_BITS-1:0] rd_resp_addr;`
100			`wire [SIZE_BITS-1:0] rd_resp_size;`
101
102			`reg wr_cmd_push = 0;`
103			`wire wr_cmd_pop;`
104			`wire [PEND_BITS:0] wr_cmd_fullness;`
105			`wire wr_cmd_empty;`
106			`wire wr_cmd_full;`
107			`reg [ADDR_BITS-1:0] wr_cmd_addr_in;`
108			`reg [LEN_BITS-1:0] wr_cmd_len_in;`
109			`reg [SIZE_BITS-1:0] wr_cmd_size_in;`
110			`wire [ADDR_BITS-1:0] wr_cmd_addr;`
111			`wire [LEN_BITS-1:0] wr_cmd_len;`
112			`wire [SIZE_BITS-1:0] wr_cmd_size;`
113
114			`reg wr_data_push = 0;`
115			`wire wr_data_pop;`
116			`wire [PEND_BITS:0] wr_data_fullness;`
117			`wire wr_data_empty;`
118			`wire wr_data_full;`
119			`reg [ADDR_BITS-1:0] wr_data_addr_in;`
120			`reg [LEN_BITS-1:0] wr_data_len_in;`
121			`reg [SIZE_BITS-1:0] wr_data_size_in;`
122			`wire [ADDR_BITS-1:0] wr_data_addr;`
123			`wire [LEN_BITS-1:0] wr_data_len;`
124			`wire [SIZE_BITS-1:0] wr_data_size;`
125			`wire [DATA_BITS/8-1:0] wr_data_strb;`
126			`wire [7:0] wr_data_bytes;`
127			`wire [ADDR_BITS-1:0] wr_data_addr_prog;`
128			`wire [7:0] wr_data_offset;`
129
130			`wire wr_resp_push;`
131			`reg wr_resp_pop = 0;`
132			`wire wr_resp_empty;`
133			`wire wr_resp_full;`
134			`wire [1:0] wr_resp_resp_in;`
135			`wire [1:0] wr_resp_resp;`
136
137			`reg wr_fifo_push = 0;`
138			`wire wr_fifo_pop;`
139			`wire wr_fifo_empty;`
140			`wire wr_fifo_full;`
141			`reg [DATA_BITS-1:0] wr_fifo_data_in;`
142			`wire [DATA_BITS-1:0] wr_fifo_data;`
143
144			`wire rd_fifo_push;`
145			`reg rd_fifo_pop = 0;`
146			`wire rd_fifo_empty;`
147			`wire rd_fifo_full;`
148			`wire [DATA_BITS-1:0] rd_fifo_data_in;`
149			`wire [1:0] rd_fifo_resp_in;`
150			`wire [DATA_BITS-1:0] rd_fifo_data;`
151			`wire [1:0] rd_fifo_resp;`
152
153			`reg scrbrd_push = 0;`
154			`reg scrbrd_pop = 0;`
155			`wire scrbrd_empty;`
156			`wire scrbrd_full;`
157			`reg [ADDR_BITS-1:0] scrbrd_addr_in;`
158			`reg [DATA_BITS-1:0] scrbrd_data_in;`
159			`reg [DATA_BITS-1:0] scrbrd_mask_in;`
160			`wire [ADDR_BITS-1:0] scrbrd_addr;`
161			`wire [DATA_BITS-1:0] scrbrd_data;`
162			`wire [DATA_BITS-1:0] scrbrd_mask;`
163
164			`integer wr_fullness;`
165			`integer rd_fullness;`
166			`integer rd_completed;`
167			`integer wr_completed;`
168			`integer wr_pend_max = MASTER_PEND;`
169			`integer rd_pend_max = MASTER_PEND;`
170			`wire wr_hold;`
171			`wire rd_hold;`
172
173			`integer rand_chk_num = 0;`
174
175
176			`assign idle = rd_cmd_empty & rd_resp_empty & wr_cmd_empty & wr_data_empty & wr_resp_empty;`
177
178			`always @(rand_chk_num)`
179			`if (rand_chk_num > 0)`
180			`insert_rand_chk_loop(rand_chk_num);`
181
182			`always @(posedge enable)`
183			`begin`
184			`@(posedge clk);`
185			`wr_enable = 1;`
186			`repeat (50) @(posedge clk);`
187			`rd_enable = 1;`
188			`end`
189
190			`//for incremental data`
191			`reg [DATA_BITS-1:0] base_data = 0;`
192			`integer ww;`
193			`initial`
194			`begin`
195			`ww=0;`
196			`while (ww < DATA_BITS/8)`
197			`begin`
198			`base_data = base_data + ((MASTER_NUM + ww) << (ww*8));`
199			`ww = ww + 1;`
200			`end`
201			`end`
202
203			`assign rd_cmd_pop = ARVALID & ARREADY;`
204			`assign rd_resp_pop = RVALID & RREADY & RLAST;`
205			`assign rd_fifo_push = RVALID & RREADY;`
206			`assign wr_cmd_pop = AWVALID & AWREADY;`
207			`assign wr_data_pop = WVALID & WREADY & WLAST;`
208			`assign wr_fifo_pop = WVALID & WREADY;`
209			`assign wr_resp_push = BVALID & BREADY;`
210
211			`assign RREADY_pre = 1;`
212			`assign BREADY_pre = 1;`
213
214
215			`always @(posedge clk or posedge reset)`
216			`if (reset)`
217			`AWVALID_pre <= #FFD 1'b0;`
218			`else if ((wr_cmd_fullness == 1) & wr_cmd_pop)`
219			`AWVALID_pre <= #FFD 1'b0;`
220			`else if ((!wr_cmd_empty) & wr_enable)`
221			`AWVALID_pre <= #FFD 1'b1;`
222
223
224			`assign AWADDR = wr_cmd_addr;`
225			`assign AWLEN = wr_cmd_len;`
226			`assign AWSIZE = wr_cmd_size;`
227			`assign AWID = MASTER_ID;`
228			`assign AWBURST = 2'd1; //INCR only`
229			`assign AWCACHE = 4'd0; //not supported`
230			`assign AWPROT = 4'd0; //not supported`
231			`assign AWLOCK = 2'd0; //not supported`
232
233			`always @(posedge clk or posedge reset)`
234			`if (reset)`
235			`ARVALID_pre <= #FFD 1'b0;`
236			`else if (((rd_cmd_fullness == 1)) & rd_cmd_pop)`
237			`ARVALID_pre <= #FFD 1'b0;`
238			`else if ((!rd_cmd_empty) & rd_enable)`
239			`ARVALID_pre <= #FFD 1'b1;`
240
241			`assign ARADDR = rd_cmd_addr;`
242			`assign ARLEN = rd_cmd_len;`
243			`assign ARSIZE = rd_cmd_size;`
244			`assign ARID = MASTER_ID;`
245			`assign ARBURST = 2'd1; //INCR only`
246			`assign ARCACHE = 4'd0; //not supported`
247			`assign ARPROT = 4'd0; //not supported`
248			`assign ARLOCK = 2'd0; //not supported`
249
250			`assign rd_fifo_data_in = RDATA;`
251			`assign rd_fifo_resp_in = BRESP;`
252
253			`assign wr_data_bytes = 1'b1 << wr_data_size;`
254
255			`assign wr_data_strb =`
256			`wr_data_size == 'd0 ? 1'b1 :`
257			`wr_data_size == 'd1 ? 2'b11 :`
258			`wr_data_size == 'd2 ? 4'b1111 :`
259			`wr_data_size == 'd3 ? {8{1'b1}} :`
260			`wr_data_size == 'd4 ? {16{1'b1}} : 'd0;`
261
262			`assign wr_data_addr_prog = wr_data_addr + (wvalid_cnt * wr_data_bytes);`
263
264			`always @(posedge clk or posedge reset)`
265			`if (reset)`
266			`WVALID_pre <= #FFD 1'b0;`
267			`else if ((wr_data_fullness == 1) & wr_data_pop)`
268			`WVALID_pre <= #FFD 1'b0;`
269			`else if ((!wr_data_empty) & wr_enable)`
270			`WVALID_pre <= #FFD 1'b1;`
271
272
273			`assign wr_data_offset = wr_data_addr_prog[DATA_LOG-1:0];`
274
275			`assign WID = MASTER_ID;`
276			`assign WDATA = wr_fifo_empty ? 0 : wr_fifo_data;`
277			`assign WSTRB = wr_data_strb << wr_data_offset;`
278
279
280			`always @(posedge clk or posedge reset)`
281			`if (reset)`
282			`wvalid_cnt <= #FFD {LEN_BITS{1'b0}};`
283			`else if (wr_data_pop)`
284			`wvalid_cnt <= #FFD {LEN_BITS{1'b0}};`
285			`else if (WVALID & WREADY)`
286			`wvalid_cnt <= #FFD wvalid_cnt + 1'b1;`
287
288			`assign WLAST = WVALID & (wvalid_cnt == wr_data_len);`
289
290			`assign wr_resp_resp_in = BRESP;`
291
292			`always @(posedge clk or posedge reset)`
293			`if (reset)`
294			`begin`
295			`wr_fullness <= #FFD 0;`
296			`rd_fullness <= #FFD 0;`
297			`rd_completed <= #FFD 0;`
298			`wr_completed <= #FFD 0;`
299			`end`
300			`else`
301			`begin`
302			`wr_fullness <= #FFD wr_fullness + wr_cmd_pop - wr_resp_push;`
303			`rd_fullness <= #FFD rd_fullness + rd_cmd_pop - rd_resp_pop;`
304			`rd_completed <= #FFD rd_completed + rd_resp_pop;`
305			`wr_completed <= #FFD wr_completed + wr_resp_push;`
306			`end`
307
308			`assign wr_hold = wr_fullness >= wr_pend_max;`
309			`assign rd_hold = (rd_fullness >= rd_pend_max) \| (wait_for_write & (wr_completed <= rd_completed + rd_fullness));`
310
311
312
313			`task insert_rd_cmd;`
314			`input [ADDR_BITS-1:0] addr;`
315			`input [LEN_BITS-1:0] len;`
316			`input [SIZE_BITS-1:0] size;`
317
318			`begin`
319			`rd_cmd_addr_in = addr;`
320			`rd_cmd_len_in = len;`
321			`rd_cmd_size_in = size;`
322			`rd_resp_addr_in = addr;`
323			`rd_resp_size_in = size;`
324
325			`if (rd_cmd_full) enable = 1; //start stub not started yet`
326
327			`wait ((!rd_cmd_full) & (!rd_resp_full));`
328			`@(negedge clk); #FFD;`
329			`rd_cmd_push = 1;`
330			`rd_resp_push = 1;`
331			`@(posedge clk); #FFD;`
332			`rd_cmd_push = 0;`
333			`rd_resp_push = 0;`
334			`end`
335			`endtask`
336
337			`task insert_wr_cmd;`
338			`input [ADDR_BITS-1:0] addr;`
339			`input [LEN_BITS-1:0] len;`
340			`input [SIZE_BITS-1:0] size;`
341
342			`begin`
343			`wr_cmd_addr_in = addr;`
344			`wr_cmd_len_in = len;`
345			`wr_cmd_size_in = size;`
346			`wr_data_addr_in = addr;`
347			`wr_data_len_in = len;`
348			`wr_data_size_in = size;`
349
350			`if (wr_cmd_full) enable = 1; //start stub not started yet`
351
352			`wait ((!wr_cmd_full) & (!wr_data_full));`
353			`@(negedge clk); #FFD;`
354			`wr_cmd_push = 1;`
355			`wr_data_push = 1;`
356			`@(posedge clk); #FFD;`
357			`wr_cmd_push = 0;`
358			`wr_data_push = 0;`
359			`end`
360			`endtask`
361
362			`task insert_wr_data;`
363			`input [DATA_BITS-1:0] wdata;`
364
365			`begin`
366			`wr_fifo_data_in = wdata;`
367
368			`wait (!wr_fifo_full);`
369			`@(negedge clk); #FFD;`
370			`wr_fifo_push = 1;`
371			`@(posedge clk); #FFD;`
372			`wr_fifo_push = 0;`
373			`end`
374			`endtask`
375
376			`task insert_wr_incr_data;`
377			`input [ADDR_BITS-1:0] addr;`
378			`input [LEN_BITS-1:0] len;`
379			`input [SIZE_BITS-1:0] size;`
380
381			`integer valid_cnt;`
382			`integer wdata_cnt;`
383			`reg [7:0] data_cnt;`
384			`integer bytes;`
385			`reg [DATA_BITS-1:0] add_data;`
386			`reg [DATA_BITS-1:0] next_data;`
387			`begin`
388			`//insert data`
389			`valid_cnt = 0;`
390			`while (valid_cnt <= len)`
391			`begin`
392			`bytes = 1'b1 << size;`
393			`wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);`
394			`data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes8))) (DATA_BITS/8);`
395			`add_data = {DATA_BITS/8{data_cnt}};`
396			`next_data = base_data + add_data;`
397			`insert_wr_data(next_data);`
398			`valid_cnt = valid_cnt+1;`
399			`end`
400			`//insert command`
401			`insert_wr_cmd(addr, len, size);`
402			`end`
403			`endtask`
404
405			`task insert_scrbrd;`
406			`input [ADDR_BITS-1:0] addr;`
407			`input [DATA_BITS-1:0] data;`
408			`input [DATA_BITS-1:0] mask;`
409			`begin`
410			`scrbrd_enable = 1;`
411			`scrbrd_addr_in = addr;`
412			`scrbrd_data_in = data;`
413			`scrbrd_mask_in = mask;`
414
415			`wait (!scrbrd_full);`
416			`@(negedge clk); #FFD;`
417			`scrbrd_push = 1;`
418			`@(posedge clk); #FFD;`
419			`scrbrd_push = 0;`
420			`end`
421			`endtask`
422
423			`task insert_scrbrd_incr_data;`
424			`input [ADDR_BITS-1:0] addr;`
425			`input [LEN_BITS-1:0] len;`
426			`input [SIZE_BITS-1:0] size;`
427
428			`integer valid_cnt;`
429			`integer wdata_cnt;`
430			`reg [7:0] data_cnt;`
431			`integer bytes;`
432			`reg [DATA_BITS-1:0] add_data;`
433			`reg [DATA_BITS-1:0] next_data;`
434			`reg [DATA_BITS:0] strb;`
435			`reg [DATA_BITS-1:0] mask;`
436			`reg [ADDR_BITS-1:0] next_addr;`
437			`begin`
438			`valid_cnt = 0;`
439			`while (valid_cnt <= len)`
440			`begin`
441			`bytes = 1'b1 << size;`
442			`wdata_cnt = valid_cnt+(addr[DATA_LOG-1:0]/bytes);`
443			`data_cnt = ((wdata_cnt)/(DATA_BITS/(bytes8))) (DATA_BITS/8);`
444			`add_data = {DATA_BITS/8{data_cnt}};`
445			`next_data = base_data + add_data;`
446			`next_addr = addr + (bytes * valid_cnt);`
447			`strb = (1 << (bytes*8)) - 1;`
448			`mask = strb << (next_addr[DATA_LOG-1:0]*8);`
449			`insert_scrbrd(next_addr, next_data, mask);`
450			`valid_cnt = valid_cnt+1;`
451			`end`
452			`end`
453			`endtask`
454
455			`task insert_rd_scrbrd;`
456			`input [ADDR_BITS-1:0] addr;`
457			`input [LEN_BITS-1:0] len;`
458			`input [SIZE_BITS-1:0] size;`
459
460			`begin`
461			`insert_scrbrd_incr_data(addr, len, size);`
462			`insert_rd_cmd(addr, len, size);`
463			`end`
464			`endtask`
465
466			`task insert_wr_rd_scrbrd;`
467			`input [ADDR_BITS-1:0] addr;`
468			`input [LEN_BITS-1:0] len;`
469			`input [SIZE_BITS-1:0] size;`
470
471			`begin`
472			`wait_for_write=1;`
473			`insert_wr_incr_data(addr, len, size);`
474			`insert_rd_scrbrd(addr, len, size);`
475			`end`
476			`endtask`
477
478			`task insert_wr_rd_scrbrd_rand;`
479			`reg [ADDR_BITS-1:0] addr;`
480			`reg [LEN_BITS-1:0] len;`
481			`reg [SIZE_BITS-1:0] size;`
482
483			`begin`
484			`len = rand(len_min, len_max);`
485			`size = rand(size_min, size_max);`
486			`addr = rand_align(addr_min, addr_max, 1 << size);`
487			`insert_wr_rd_scrbrd(addr, len, size);`
488			`end`
489			`endtask`
490
491			`task insert_rand_chk;`
492			`input [31:0] num;`
493
494			`rand_chk_num = num;`
495			`endtask`
496
497			`task insert_rand_chk_loop;`
498			`input [31:0] num;`
499
500			`integer i;`
501			`begin`
502			`i = 0;`
503			`while (i < num)`
504			`begin`
505			`insert_wr_rd_scrbrd_rand;`
506			`i = i + 1;`
507			`end`
508			`end`
509			`endtask`
510
511			`task insert_wr_single;`
512			`input [ADDR_BITS-1:0] addr;`
513			`input [DATA_BITS-1:0] wdata;`
514
515			`reg [SIZE_BITS-1:0] size;`
516			`begin`
517			`size = EXPR((DATA_BITS/32)+1);`
518			`insert_wr_data(wdata);`
519			`insert_wr_cmd(addr, 0, size);`
520			`end`
521			`endtask`
522
523			`task get_rd_resp;`
524			`output [DATA_BITS-1:0] rdata;`
525			`output [1:0] resp;`
526
527			`reg [DATA_BITS-1:0] rdata;`
528			`reg [1:0] resp;`
529			`begin`
530			`wait (!rd_fifo_empty);`
531			`rdata = rd_fifo_data;`
532			`resp = rd_fifo_resp;`
533			`@(negedge clk); #FFD;`
534			`rd_fifo_pop = 1;`
535			`@(posedge clk); #FFD;`
536			`rd_fifo_pop = 0;`
537			`end`
538			`endtask`
539
540			`task get_scrbrd;`
541			`output [ADDR_BITS-1:0] addr;`
542			`output [DATA_BITS-1:0] rdata;`
543			`output [DATA_BITS-1:0] mask;`
544
545			`reg [ADDR_BITS-1:0] addr;`
546			`reg [DATA_BITS-1:0] rdata;`
547			`reg [DATA_BITS-1:0] mask;`
548			`begin`
549			`wait (!scrbrd_empty);`
550			`addr = scrbrd_addr;`
551			`rdata = scrbrd_data;`
552			`mask = scrbrd_mask;`
553			`@(negedge clk); #FFD;`
554			`scrbrd_pop = 1;`
555			`@(posedge clk); #FFD;`
556			`scrbrd_pop = 0;`
557			`end`
558			`endtask`
559
560			`task get_wr_resp;`
561			`output [1:0] resp;`
562
563			`reg [1:0] resp;`
564			`begin`
565			`wait (!wr_resp_empty);`
566			`resp = wr_resp_resp;`
567			`@(negedge clk); #FFD;`
568			`wr_resp_pop = 1;`
569			`@(posedge clk); #FFD;`
570			`wr_resp_pop = 0;`
571			`end`
572			`endtask`
573
574			`task insert_rd_single;`
575			`input [ADDR_BITS-1:0] addr;`
576
577			`reg [SIZE_BITS-1:0] size;`
578			`begin`
579			`size = EXPR((DATA_BITS/32)+1);`
580			`insert_rd_cmd(addr, 0, size);`
581			`end`
582			`endtask`
583
584			`task read_single_ack;`
585			`input [ADDR_BITS-1:0] addr;`
586			`output [DATA_BITS-1:0] rdata;`
587			`output [1:0] resp;`
588
589			`reg [1:0] resp;`
590			`begin`
591			`insert_rd_single(addr);`
592			`get_rd_resp(rdata, resp);`
593			`end`
594			`endtask`
595
596			`task write_single_ack;`
597			`input [ADDR_BITS-1:0] addr;`
598			`input [DATA_BITS-1:0] wdata;`
599			`output [1:0] resp;`
600
601			`reg [1:0] resp;`
602			`begin`
603			`insert_wr_single(addr, wdata);`
604			`get_wr_resp(resp);`
605			`end`
606			`endtask`
607
608			`task read_single;`
609			`input [ADDR_BITS-1:0] addr;`
610			`output [DATA_BITS-1:0] rdata;`
611
612			`reg [1:0] resp;`
613			`begin`
614			`read_single_ack(addr, rdata, resp);`
615			`end`
616			`endtask`
617
618			`task write_single;`
619			`input [ADDR_BITS-1:0] addr;`
620			`input [DATA_BITS-1:0] wdata;`
621
622			`reg [1:0] resp;`
623			`begin`
624			`write_single_ack(addr, wdata, resp);`
625			`end`
626			`endtask`
627
628			`task chk_scrbrd;`
629			`reg [ADDR_BITS-1:0] addr;`
630			`reg [DATA_BITS-1:0] mask;`
631			`reg [DATA_BITS-1:0] expected_data;`
632			`reg [DATA_BITS-1:0] rdata;`
633			`reg [DATA_BITS-1:0] rdata_masked;`
634			`reg [1:0] resp;`
635
636			`begin`
637			`if (!wr_resp_empty) get_wr_resp(resp);`
638			`get_scrbrd(addr, expected_data, mask);`
639			`get_rd_resp(rdata, resp);`
640			`expected_data = expected_data & mask; //TBD insert z as dontcare (for print)`
641			`rdata_masked = rdata & mask;`
642
643			`if (expected_data !== rdata_masked)`
644			`$display("MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);`
645			`end`
646			`endtask`
647
648			`always @(posedge scrbrd_enable)`
649			`begin`
650			`while (scrbrd_enable)`
651			`begin`
652			`chk_scrbrd;`
653			`end`
654			`end`
655
656
657			`CREATE prgen_fifo.v DEFCMD(DEFINE STUB)`
658			`prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)`
659			`rd_cmd_list(`
660			`.clk(clk),`
661			`.reset(reset),`
662			`.push(rd_cmd_push),`
663			`.pop(rd_cmd_pop),`
664			`.din({`
665			`rd_cmd_size_in,`
666			`rd_cmd_len_in,`
667			`rd_cmd_addr_in`
668			`}),`
669			`.dout({`
670			`rd_cmd_size,`
671			`rd_cmd_len,`
672			`rd_cmd_addr`
673			`}),`
674			`.fullness(rd_cmd_fullness),`
675			`.empty(rd_cmd_empty),`
676			`.full(rd_cmd_full)`
677			`);`
678
679			`prgen_fifo_stub #(ADDR_BITS+SIZE_BITS, MAX_CMDS)`
680			`rd_resp_list(`
681			`.clk(clk),`
682			`.reset(reset),`
683			`.push(rd_resp_push),`
684			`.pop(rd_resp_pop),`
685			`.din({`
686			`rd_resp_addr_in,`
687			`rd_resp_size_in`
688			`}),`
689			`.dout({`
690			`rd_resp_addr,`
691			`rd_resp_size`
692			`}),`
693			`.empty(rd_resp_empty),`
694			`.full(rd_resp_full)`
695			`);`
696
697			`prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)`
698			`wr_cmd_list(`
699			`.clk(clk),`
700			`.reset(reset),`
701			`.push(wr_cmd_push),`
702			`.pop(wr_cmd_pop),`
703			`.din({`
704			`wr_cmd_size_in,`
705			`wr_cmd_len_in,`
706			`wr_cmd_addr_in`
707			`}),`
708			`.dout({`
709			`wr_cmd_size,`
710			`wr_cmd_len,`
711			`wr_cmd_addr`
712			`}),`
713			`.fullness(wr_cmd_fullness),`
714			`.empty(wr_cmd_empty),`
715			`.full(wr_cmd_full)`
716			`);`
717
718			`prgen_fifo_stub #(ADDR_BITS+LEN_BITS+SIZE_BITS, MAX_CMDS)`
719			`wr_data_list(`
720			`.clk(clk),`
721			`.reset(reset),`
722			`.push(wr_data_push),`
723			`.pop(wr_data_pop),`
724			`.din({`
725			`wr_data_size_in,`
726			`wr_data_len_in,`
727			`wr_data_addr_in`
728			`}),`
729			`.dout({`
730			`wr_data_size,`
731			`wr_data_len,`
732			`wr_data_addr`
733			`}),`
734			`.fullness(wr_data_fullness),`
735			`.empty(wr_data_empty),`
736			`.full(wr_data_full)`
737			`);`
738
739			`prgen_fifo_stub #(2, MAX_CMDS)`
740			`wr_resp_list(`
741			`.clk(clk),`
742			`.reset(reset),`
743			`.push(wr_resp_push),`
744			`.pop(wr_resp_pop),`
745			`.din(wr_resp_resp_in),`
746			`.dout(wr_resp_resp),`
747			`.empty(wr_resp_empty),`
748			`.full(wr_resp_full)`
749			`);`
750
751
752			`prgen_fifo_stub #(DATA_BITS, MAX_CMDS*EXPR(2^LEN_BITS))`
753			`wr_data_fifo(`
754			`.clk(clk),`
755			`.reset(reset),`
756			`.push(wr_fifo_push),`
757			`.pop(wr_fifo_pop),`
758			`.din(wr_fifo_data_in),`
759			`.dout(wr_fifo_data),`
760			`.empty(wr_fifo_empty),`
761			`.full(wr_fifo_full)`
762			`);`
763
764			`prgen_fifo_stub #(DATA_BITS+2, MAX_CMDS*EXPR(2^LEN_BITS))`
765			`rd_data_fifo(`
766			`.clk(clk),`
767			`.reset(reset),`
768			`.push(rd_fifo_push),`
769			`.pop(rd_fifo_pop),`
770			`.din({`
771			`rd_fifo_data_in,`
772			`rd_fifo_resp_in`
773			`}),`
774			`.dout({`
775			`rd_fifo_data,`
776			`rd_fifo_resp`
777			`}),`
778			`.empty(rd_fifo_empty),`
779			`.full(rd_fifo_full)`
780			`);`
781
782			`prgen_fifo_stub #(ADDR_BITS+2DATA_BITS, MAX_CMDSEXPR(2^LEN_BITS))`
783			`scrbrd_fifo(`
784			`.clk(clk),`
785			`.reset(reset),`
786			`.push(scrbrd_push),`
787			`.pop(scrbrd_pop),`
788			`.din({`
789			`scrbrd_addr_in,`
790			`scrbrd_data_in,`
791			`scrbrd_mask_in`
792			`}),`
793			`.dout({`
794			`scrbrd_addr,`
795			`scrbrd_data,`
796			`scrbrd_mask`
797			`}),`
798			`.empty(scrbrd_empty),`
799			`.full(scrbrd_full)`
800			`);`
801
802
803			`CREATE axi_master_stall.v`
804			`PREFIX_stall`
805			`PREFIX_stall (`
806			`.clk(clk),`
807			`.reset(reset),`
808
809			`.rd_hold(rd_hold),`
810			`.wr_hold(wr_hold),`
811
812			`.ARVALID_pre(ARVALID_pre),`
813			`.RREADY_pre(RREADY_pre),`
814			`.AWVALID_pre(AWVALID_pre),`
815			`.WVALID_pre(WVALID_pre),`
816			`.BREADY_pre(BREADY_pre),`
817
818			`.ARREADY(ARREADY),`
819			`.AWREADY(AWREADY),`
820			`.WREADY(WREADY),`
821
822			`.ARVALID(ARVALID),`
823			`.RREADY(RREADY),`
824			`.AWVALID(AWVALID),`
825			`.WVALID(WVALID),`
826			`.BREADY(BREADY)`
827			`);`
828
829
830			`endmodule`
831
832