Subversion Repositories axi_master

<##//////////////////////////////////////////////////////////////////

////                                                             ////

////  Author: Eyal Hochberg                                      ////

////          eyal@provartec.com                                 ////

////                                                             ////

////  Downloaded from: http://www.opencores.org                  ////

/////////////////////////////////////////////////////////////////////

////                                                             ////

//// Copyright (C) 2010 Provartec LTD                            ////

//// www.provartec.com                                           ////

//// info@provartec.com                                          ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

////                                                             ////

//// This source file is free software; you can redistribute it  ////

//// and/or modify it under the terms of the GNU Lesser General  ////

//// Public License as published by the Free Software Foundation.////

////                                                             ////

//// This source is distributed in the hope that it will be      ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////

//// PURPOSE.  See the GNU Lesser General Public License for more////

//// details. http://www.gnu.org/licenses/lgpl.html              ////

////                                                             ////

//////////////////////////////////////////////////////////////////##>

VERIFY (DATA_BITS <= 64) else stub supports 32 or 64 bits data bus

VERIFY (SIZE_BITS <= 3) else stub supports 32 or 64 bits data bus

GROUP STUB_AXI_A is {

    ID       ID_BITS                output

    ADDR     ADDR_BITS              output

    LEN      LEN_BITS               output

    SIZE     SIZE_BITS              output

    BURST    2                      output

    CACHE    4                      output

    PROT     3                      output

    LOCK     2                      output

    VALID    1                      output

    READY    1                      input

}

GROUP STUB_AXI_W is {

    ID        ID_BITS                output

    DATA      DATA_BITS              output

    STRB      DATA_BITS/8            output

    LAST      1                      output

    VALID     1                      output

    READY     1                      input

}

GROUP STUB_AXI_B is {

    ID        ID_BITS                input

    RESP      2                      input

    VALID     1                      input

    READY     1                      output

}

GROUP STUB_AXI_R is {

    ID        ID_BITS                input

    DATA      DATA_BITS              input

    RESP      2                      input

    LAST      1                      input

    VALID     1                      input

    READY     1                      output

}

GROUP STUB_AXI joins {

    GROUP STUB_AXI_A prefix_AW

    GROUP STUB_AXI_W prefix_W

    GROUP STUB_AXI_B prefix_B

    GROUP STUB_AXI_A prefix_AR

    GROUP STUB_AXI_R prefix_R

}

GROUP AXI_MASTER_RAND is {

   use_addr_base   SON(DEFAULT 0)

   len_min     SON(DEFAULT 0)

   len_max     SON(DEFAULT 15)

   size_min    SON(DEFAULT 0)

   size_max    SON(DEFAULT 3)

   addr_min    SON(DEFAULT 0)

   addr_max    SON(DEFAULT {DATA_BITS{1'b1}})

}