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[/] [axi_master/] [trunk/] [src/] [base/] [def_ic_static.txt] - Blame information for rev 16

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1 2 eyalhoc 
<##//////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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//////////////////////////////////////////////////////////////////##>
29 16 eyalhoc 
 
30 15 eyalhoc 
SWAP.GLOBAL MODEL_NAME AXI interconnect fabric
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32 2 eyalhoc 
SWAP MSTRS MASTER_NUM
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SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))
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LOOP MX MSTRS
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LOOP SX SLVS
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SWAP MSTR_BITS LOG2(MSTRS)
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SWAP SLV_BITS  LOG2(SLVS)
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SWAP SERR EXPR(SLVS-1)
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GROUP IC_AXI_A is {
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    ID       ID_BITS                input
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    ADDR     ADDR_BITS              input
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    LEN      4                      input
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    SIZE     2                      input
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    BURST    2                      input
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    CACHE    4                      input
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    PROT     3                      input
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    LOCK     2                      input
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    USER     USER_BITS              input
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    VALID    1                      input
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    READY    1                      output
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}
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GROUP IC_AXI_W is {
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    ID        ID_BITS                input
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    DATA      DATA_BITS              input
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    STRB      DATA_BITS/8            input
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    LAST      1                      input
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    USER      USER_BITS              input
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    VALID     1                      input
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    READY     1                      output
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}
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GROUP IC_AXI_B is {
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    ID        ID_BITS                output
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    RESP      2                      output
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    USER      USER_BITS              output
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    VALID     1                      output
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    READY     1                      input
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}
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GROUP IC_AXI_R is {
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    ID        ID_BITS                output
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    DATA      DATA_BITS              output
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    RESP      2                      output
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    LAST      1                      output
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    USER      USER_BITS              output
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    VALID     1                      output
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    READY     1                      input
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}
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GROUP IC_AXI joins {
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    GROUP IC_AXI_A prefix_AW
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    GROUP IC_AXI_W prefix_W
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    GROUP IC_AXI_B prefix_B
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    GROUP IC_AXI_A prefix_AR
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    GROUP IC_AXI_R prefix_R
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}
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GROUP IC_AXI_CMD is {
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    SLV       SLV_BITS               input
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    ID        ID_BITS                input
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    VALID     1                      input
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    READY     1                      input
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}

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