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[/] [axi_master/] [trunk/] [src/] [base/] [ic_arbiter.v] - Blame information for rev 17

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<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE PREFIX_ic_MSTR_SLV_arbiter.v
 
ITER MX MSTRNUM
ITER SX SLVNUM
 
module PREFIX_ic_MSTR_SLV_arbiter(PORTS);
 
   input                              clk;
   input                              reset;
 
   input [MSTRNUM-1:0]         M_last;
   input [MSTRNUM-1:0]         M_req;
   input [MSTRNUM-1:0]         M_grant;
 
   input [LOG2(SLVNUM)-1:0]            MMX_slave;
 
   output [MSTRNUM-1:0]        SSX_master;
 
 
 
   reg [MSTRNUM:0]                     SSX_master_prio_reg;
   wire [MSTRNUM-1:0]                  SSX_master_prio;
   reg [MSTRNUM-1:0]                   SSX_master_d;
 
   wire [MSTRNUM-1:0]                  M_SSX;
   wire [MSTRNUM-1:0]                  M_SSX_valid;
   wire [MSTRNUM-1:0]                  M_SSX_prio;
   reg [MSTRNUM-1:0]                   M_SSX_burst;
 
 
 
 
   parameter                          MASTER_NONE = BIN(0 MSTRNUM);
   parameter                          MASTERMX    = BIN(EXPR(2^MX) MSTRNUM);
 
 
 
 
IFDEF DEF_PRIO
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          SSX_master_prio_reg[MSTRNUM:1] <= #FFD {MSTRNUM{1'b0}};
          SSX_master_prio_reg[0]          <= #FFD 1'b1;
       end
     else if (|(M_req & M_grant & M_last))
       begin
          SSX_master_prio_reg[MSTRNUM:1] <= #FFD SSX_master_prio_reg[MSTRNUM-1:0];
          SSX_master_prio_reg[0]          <= #FFD SSX_master_prio_reg[MSTRNUM-1];
       end
 
   assign SSX_master_prio = SSX_master_prio_reg[MSTRNUM-1:0];
 
   assign M_SSX_prio      = M_SSX_valid & SSX_master_prio;
ENDIF DEF_PRIO
 
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          SSX_master_d <= #FFD {MSTRNUM{1'b0}};
       end
     else
       begin
          SSX_master_d <= #FFD SSX_master;
       end
 
   LOOP MX MSTRNUM
     always @(posedge clk or posedge reset)
       if (reset)
         begin
            M_SSX_burst[MX] <= #FFD 1'b0;
         end
       else if (M_req[MX])
         begin
            M_SSX_burst[MX] <= #FFD SSX_master[MX] & (M_grant[MX] ? (~M_last[MX]) : 1'b1);
         end
 
   ENDLOOP MX
 
     assign                              M_SSX = {CONCAT(MMX_slave == 'dSX ,)};
 
   assign                                M_SSX_valid = M_SSX & M_req;
 
 
   LOOP SX SLVNUM
     assign                            SSX_master =
                                                    M_SSX_burst[MX] ? SSX_master_d :
                                       IF DEF_PRIO          M_SSX_prio[MX]  ? MASTERMX :
                                                    M_SSX_valid[MX] ? MASTERMX :
                                                    MASTER_NONE;
 
   ENDLOOP SX
 
     endmodule
 

Line No.	Rev	Author	Line
1	2	eyalhoc	`<##//////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28			`//////////////////////////////////////////////////////////////////##>`
29
30			`OUTFILE PREFIX_ic_MSTR_SLV_arbiter.v`
31
32			`ITER MX MSTRNUM`
33			`ITER SX SLVNUM`
34
35			`module PREFIX_ic_MSTR_SLV_arbiter(PORTS);`
36
37			`input clk;`
38			`input reset;`
39
40			`input [MSTRNUM-1:0] M_last;`
41			`input [MSTRNUM-1:0] M_req;`
42			`input [MSTRNUM-1:0] M_grant;`
43
44			`input [LOG2(SLVNUM)-1:0] MMX_slave;`
45
46			`output [MSTRNUM-1:0] SSX_master;`
47
48
49
50			`reg [MSTRNUM:0] SSX_master_prio_reg;`
51			`wire [MSTRNUM-1:0] SSX_master_prio;`
52			`reg [MSTRNUM-1:0] SSX_master_d;`
53
54			`wire [MSTRNUM-1:0] M_SSX;`
55			`wire [MSTRNUM-1:0] M_SSX_valid;`
56			`wire [MSTRNUM-1:0] M_SSX_prio;`
57			`reg [MSTRNUM-1:0] M_SSX_burst;`
58
59
60
61
62			`parameter MASTER_NONE = BIN(0 MSTRNUM);`
63			`parameter MASTERMX = BIN(EXPR(2^MX) MSTRNUM);`
64
65
66
67
68			`IFDEF DEF_PRIO`
69			`always @(posedge clk or posedge reset)`
70			`if (reset)`
71			`begin`
72			`SSX_master_prio_reg[MSTRNUM:1] <= #FFD {MSTRNUM{1'b0}};`
73			`SSX_master_prio_reg[0] <= #FFD 1'b1;`
74			`end`
75			`else if (\|(M_req & M_grant & M_last))`
76			`begin`
77			`SSX_master_prio_reg[MSTRNUM:1] <= #FFD SSX_master_prio_reg[MSTRNUM-1:0];`
78			`SSX_master_prio_reg[0] <= #FFD SSX_master_prio_reg[MSTRNUM-1];`
79			`end`
80
81			`assign SSX_master_prio = SSX_master_prio_reg[MSTRNUM-1:0];`
82
83			`assign M_SSX_prio = M_SSX_valid & SSX_master_prio;`
84			`ENDIF DEF_PRIO`
85
86
87
88			`always @(posedge clk or posedge reset)`
89			`if (reset)`
90			`begin`
91			`SSX_master_d <= #FFD {MSTRNUM{1'b0}};`
92			`end`
93			`else`
94			`begin`
95			`SSX_master_d <= #FFD SSX_master;`
96			`end`
97
98			`LOOP MX MSTRNUM`
99			`always @(posedge clk or posedge reset)`
100			`if (reset)`
101			`begin`
102			`M_SSX_burst[MX] <= #FFD 1'b0;`
103			`end`
104			`else if (M_req[MX])`
105			`begin`
106			`M_SSX_burst[MX] <= #FFD SSX_master[MX] & (M_grant[MX] ? (~M_last[MX]) : 1'b1);`
107			`end`
108
109			`ENDLOOP MX`
110
111			`assign M_SSX = {CONCAT(MMX_slave == 'dSX ,)};`
112
113			`assign M_SSX_valid = M_SSX & M_req;`
114
115
116			`LOOP SX SLVNUM`
117			`assign SSX_master =`
118			`M_SSX_burst[MX] ? SSX_master_d :`
119			`IF DEF_PRIO M_SSX_prio[MX] ? MASTERMX :`
120			`M_SSX_valid[MX] ? MASTERMX :`
121			`MASTER_NONE;`
122
123			`ENDLOOP SX`
124
125			`endmodule`
126

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[/] [axi_master/] [trunk/] [src/] [base/] [ic_arbiter.v] - Blame information for rev 17