OpenCores
URL https://opencores.org/ocsvn/axi_master/axi_master/trunk

Subversion Repositories axi_master

[/] [axi_master/] [trunk/] [src/] [base/] [ic_decerr.v] - Blame information for rev 21

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 21 eyalhoc 
<##//////////////////////////////////////////////////////////////////
2 
////                                                             ////
3 
////  Author: Eyal Hochberg                                      ////
4 
////          eyal@provartec.com                                 ////
5 
////                                                             ////
6 
////  Downloaded from: http://www.opencores.org                  ////
7 
/////////////////////////////////////////////////////////////////////
8 
////                                                             ////
9 
//// Copyright (C) 2010 Provartec LTD                            ////
10 
//// www.provartec.com                                           ////
11 
//// info@provartec.com                                          ////
12 
////                                                             ////
13 
//// This source file may be used and distributed without        ////
14 
//// restriction provided that this copyright statement is not   ////
15 
//// removed from the file and that any derivative work contains ////
16 
//// the original copyright notice and the associated disclaimer.////
17 
////                                                             ////
18 
//// This source file is free software; you can redistribute it  ////
19 
//// and/or modify it under the terms of the GNU Lesser General  ////
20 
//// Public License as published by the Free Software Foundation.////
21 
////                                                             ////
22 
//// This source is distributed in the hope that it will be      ////
23 
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
24 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
25 
//// PURPOSE.  See the GNU Lesser General Public License for more////
26 
//// details. http://www.gnu.org/licenses/lgpl.html              ////
27 
////                                                             ////
28 
//////////////////////////////////////////////////////////////////##>
29 2 eyalhoc 
 
30 
OUTFILE PREFIX_ic_decerr.v
31 
 
32 
module PREFIX_ic_decerr(PORTS);
33 
 
34 
   input                          clk;
35 
   input                          reset;
36 
 
37 
   input                          AWIDOK;
38 
   input                          ARIDOK;
39 
   port                           GROUP_IC_AXI;
40 
 
41 
 
42 
   parameter                      RESP_SLVERR = 2'b10;
43 
   parameter                      RESP_DECERR = 2'b11;
44 
 
45 
 
46 
   reg                            AWREADY;
47 
   reg [ID_BITS-1:0]               BID;
48 
   reg [1:0]                       BRESP;
49 
   reg                            BVALID;
50 
   reg                            ARREADY;
51 
   reg [ID_BITS-1:0]               RID;
52 
   reg [1:0]                       RRESP;
53 
   reg                            RVALID;
54 7 eyalhoc 
   reg [4-1:0]                    rvalid_cnt;
55 2 eyalhoc 
 
56 7 eyalhoc 
IFDEF TRUE (USER_BITS>0)
57 2 eyalhoc 
   assign                         BUSER = 'd0;
58 
   assign                         RUSER = 'd0;
59 7 eyalhoc 
ENDIF TRUE (USER_BITS>0)
60 
 
61 2 eyalhoc 
   assign                         RDATA = {DATA_BITS{1'b0}};
62 
 
63 
 
64 
   //WRITE
65 
   assign                         WREADY = 1'b1;
66 
 
67 
   always @(posedge clk or posedge reset)
68 
     if (reset)
69 
       begin
70 
          AWREADY <= #FFD 1'b1;
71 
          BID     <= #FFD {ID_BITS{1'b0}};
72 
          BRESP   <= #FFD 2'b00;
73 
       end
74 
     else if (BVALID & BREADY)
75 
       begin
76 
          AWREADY <= #FFD 1'b1;
77 
       end
78 
     else if (AWVALID & AWREADY)
79 
       begin
80 
          AWREADY <= #FFD 1'b0;
81 
          BID     <= #FFD AWID;
82 
          BRESP   <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;
83 
       end
84 
 
85 
   always @(posedge clk or posedge reset)
86 
     if (reset)
87 
       BVALID <= #FFD 1'b0;
88 
     else if (WVALID & WREADY & WLAST)
89 
       BVALID <= #FFD 1'b1;
90 
     else if (BVALID & BREADY)
91 
       BVALID <= #FFD 1'b0;
92 
 
93 
 
94 
   //READ
95 
   always @(posedge clk or posedge reset)
96 
     if (reset)
97 
       begin
98 
          ARREADY <= #FFD 1'b1;
99 
          RID     <= #FFD {ID_BITS{1'b0}};
100 
          RRESP   <= #FFD 2'b00;
101 
       end
102 
     else if (RVALID & RREADY & RLAST)
103 
       begin
104 
          ARREADY <= #FFD 1'b1;
105 
       end
106 
     else if (ARVALID & ARREADY)
107 
       begin
108 
          ARREADY <= #FFD 1'b0;
109 
          RID     <= #FFD ARID;
110 
          RRESP   <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;
111 
       end
112 
 
113 
 
114 
   always @(posedge clk or posedge reset)
115 
     if (reset)
116 
       rvalid_cnt <= #FFD {4{1'b0}};
117 
     else if (RVALID & RREADY & RLAST)
118 
       rvalid_cnt <= #FFD {4{1'b0}};
119 
     else if (RVALID & RREADY)
120 
       rvalid_cnt <= #FFD rvalid_cnt - 1'b1;
121 
     else if (ARVALID & ARREADY)
122 
       rvalid_cnt <= #FFD ARLEN;
123 
 
124 
 
125 
   always @(posedge clk or posedge reset)
126 
     if (reset)
127 
       RVALID <= #FFD 1'b0;
128 
     else if (RVALID & RREADY & RLAST)
129 
       RVALID <= #FFD 1'b0;
130 
     else if (ARVALID & ARREADY)
131 
       RVALID <= #FFD 1'b1;
132 
 
133 
   assign RLAST = (rvalid_cnt == 'd0) & RVALID;
134 
 
135 
 
136 
 
137 
 
138 
 
139 
 
140 
endmodule
141 
 
142 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.