OpenCores
URL https://opencores.org/ocsvn/axi_master/axi_master/trunk

Subversion Repositories axi_master

[/] [axi_master/] [trunk/] [src/] [base/] [ic_registry_wr.v] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 eyalhoc
<##//////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  Author: Eyal Hochberg                                      ////
4
////          eyal@provartec.com                                 ////
5
////                                                             ////
6
////  Downloaded from: http://www.opencores.org                  ////
7
/////////////////////////////////////////////////////////////////////
8
////                                                             ////
9
//// Copyright (C) 2010 Provartec LTD                            ////
10
//// www.provartec.com                                           ////
11
//// info@provartec.com                                          ////
12
////                                                             ////
13
//// This source file may be used and distributed without        ////
14
//// restriction provided that this copyright statement is not   ////
15
//// removed from the file and that any derivative work contains ////
16
//// the original copyright notice and the associated disclaimer.////
17
////                                                             ////
18
//// This source file is free software; you can redistribute it  ////
19
//// and/or modify it under the terms of the GNU Lesser General  ////
20
//// Public License as published by the Free Software Foundation.////
21
////                                                             ////
22
//// This source is distributed in the hope that it will be      ////
23
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
24
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
25
//// PURPOSE.  See the GNU Lesser General Public License for more////
26
//// details. http://www.gnu.org/licenses/lgpl.html              ////
27
////                                                             ////
28
//////////////////////////////////////////////////////////////////##>
29
 
30
OUTFILE PREFIX_ic_registry_wr.v
31
 
32
ITER MX
33
ITER SX
34
 
35
module PREFIX_ic_registry_wr(PORTS);
36
 
37
 
38
 
39
   input                            clk;
40
   input                            reset;
41
 
42
   port                             MMX_AWGROUP_IC_AXI_CMD;
43
 
44 14 eyalhoc
   input [ID_BITS-1:0]              MMX_WID;
45 2 eyalhoc
   input                            MMX_WVALID;
46
   input                            MMX_WREADY;
47
   input                            MMX_WLAST;
48 14 eyalhoc
   output [SLV_BITS-1:0]            MMX_WSLV;
49 2 eyalhoc
   output                           MMX_WOK;
50
 
51
   input                            SSX_AWVALID;
52
   input                            SSX_AWREADY;
53 14 eyalhoc
   input [MSTR_BITS-1:0]            SSX_AWMSTR;
54 2 eyalhoc
   input                            SSX_WVALID;
55
   input                            SSX_WREADY;
56
   input                            SSX_WLAST;
57
 
58
 
59 14 eyalhoc
   wire                             AWmatch_MMX_IDGROUP_MMX_ID.IDX;
60
   wire                             Wmatch_MMX_IDGROUP_MMX_ID.IDX;
61 2 eyalhoc
 
62
   wire                             cmd_push_MMX;
63 14 eyalhoc
   wire                             cmd_push_MMX_IDGROUP_MMX_ID.IDX;
64 2 eyalhoc
 
65
   wire                             cmd_pop_MMX;
66 14 eyalhoc
   wire                             cmd_pop_MMX_IDGROUP_MMX_ID.IDX;
67 2 eyalhoc
 
68 18 eyalhoc
   wire                             slave_empty_MMX;
69 14 eyalhoc
   wire [SLV_BITS-1:0]              slave_in_MMX_IDGROUP_MMX_ID.IDX;
70
   wire [SLV_BITS-1:0]              slave_out_MMX_IDGROUP_MMX_ID.IDX;
71
   wire                             slave_empty_MMX_IDGROUP_MMX_ID.IDX;
72
   wire                             slave_full_MMX_IDGROUP_MMX_ID.IDX;
73 2 eyalhoc
 
74
   wire                             cmd_push_SSX;
75
   wire                             cmd_pop_SSX;
76 14 eyalhoc
   wire [MSTR_BITS-1:0]             master_in_SSX;
77
   wire [MSTR_BITS-1:0]             master_out_SSX;
78 2 eyalhoc
   wire                             master_empty_SSX;
79
   wire                             master_full_SSX;
80
 
81 14 eyalhoc
   reg [SLV_BITS-1:0]               MMX_WSLV;
82 2 eyalhoc
   reg                              MMX_WOK;
83
 
84 18 eyalhoc
   reg                              MMX_pending;
85
   reg                              MMX_pending_d;
86
   wire                             MMX_pending_rise;
87 2 eyalhoc
 
88
 
89
 
90 17 eyalhoc
   assign                           AWmatch_MMX_IDGROUP_MMX_ID.IDX  = MMX_AWID == ID_BITS'bADD_IDGROUP_MMX_ID;
91 2 eyalhoc
 
92 17 eyalhoc
   assign                           Wmatch_MMX_IDGROUP_MMX_ID.IDX   = MMX_WID == ID_BITS'bADD_IDGROUP_MMX_ID;
93 2 eyalhoc
 
94
 
95 18 eyalhoc
   assign                           cmd_push_MMX           = MMX_AWVALID & (MMX_pending ? MMX_pending_rise : MMX_AWREADY);
96 14 eyalhoc
   assign                           cmd_push_MMX_IDGROUP_MMX_ID.IDX = cmd_push_MMX & AWmatch_MMX_IDGROUP_MMX_ID.IDX;
97 2 eyalhoc
   assign                           cmd_pop_MMX            = MMX_WVALID & MMX_WREADY & MMX_WLAST;
98 14 eyalhoc
   assign                           cmd_pop_MMX_IDGROUP_MMX_ID.IDX  = cmd_pop_MMX & Wmatch_MMX_IDGROUP_MMX_ID.IDX;
99 2 eyalhoc
 
100
   assign                           cmd_push_SSX           = SSX_AWVALID & SSX_AWREADY;
101
   assign                           cmd_pop_SSX            = SSX_WVALID & SSX_WREADY & SSX_WLAST;
102
   assign                           master_in_SSX          = SSX_AWMSTR;
103
 
104 14 eyalhoc
   assign                           slave_in_MMX_IDGROUP_MMX_ID.IDX = MMX_AWSLV;
105 2 eyalhoc
 
106 18 eyalhoc
 
107
   assign                           MMX_pending_rise = MMX_pending & (~MMX_pending_d);
108 2 eyalhoc
 
109 18 eyalhoc
   always @(posedge clk or posedge reset)
110
     if (reset)
111
       begin
112
          MMX_pending   <= #FFD 1'b0;
113
          MMX_pending_d <= #FFD 1'b0;
114
       end
115
     else
116
       begin
117
          MMX_pending   <= #FFD MMX_AWVALID & (~MMX_AWREADY);
118
          MMX_pending_d <= #FFD MMX_pending;
119
       end
120
 
121
 
122 2 eyalhoc
   LOOP MX
123 14 eyalhoc
   always @(*)
124 2 eyalhoc
     begin
125 17 eyalhoc
        case (MMX_WID)
126
          ID_BITS'bADD_IDGROUP_MMX_ID : MMX_WSLV = slave_out_MMX_IDGROUP_MMX_ID.IDX;
127 2 eyalhoc
          default : MMX_WSLV = SERR;
128
        endcase
129
     end
130
 
131 14 eyalhoc
   always @(*)
132 2 eyalhoc
     begin
133
        case (MMX_WSLV)
134 18 eyalhoc
          SLV_BITS'dSX : MMX_WOK = (master_out_SSX == MSTR_BITS'dMX) & (~slave_empty_MMX);
135 2 eyalhoc
          default : MMX_WOK = 1'b0;
136
        endcase
137
     end
138
 
139
   ENDLOOP MX
140
 
141
LOOP MX
142 18 eyalhoc
  assign slave_empty_MMX = GONCAT(slave_empty_MMX_IDGROUP_MMX_ID.IDX &);
143 14 eyalhoc
 LOOP IX GROUP_MMX_ID.NUM
144 18 eyalhoc
 
145 2 eyalhoc
   prgen_fifo #(SLV_BITS, CMD_DEPTH)
146 14 eyalhoc
   slave_fifo_MMX_IDIX(
147
                       .clk(clk),
148
                       .reset(reset),
149
                       .push(cmd_push_MMX_IDIX),
150
                       .pop(cmd_pop_MMX_IDIX),
151
                       .din(slave_in_MMX_IDIX),
152
                       .dout(slave_out_MMX_IDIX),
153
                       .empty(slave_empty_MMX_IDIX),
154
                       .full(slave_full_MMX_IDIX)
155
                       );
156 2 eyalhoc
 
157 14 eyalhoc
 ENDLOOP IX
158
ENDLOOP MX
159 2 eyalhoc
 
160
 
161
 
162 14 eyalhoc
LOOP SX
163 18 eyalhoc
   prgen_fifo #(MSTR_BITS, SLV_DEPTH)
164 2 eyalhoc
   master_fifo_SSX(
165
                   .clk(clk),
166
                   .reset(reset),
167
                   .push(cmd_push_SSX),
168
                   .pop(cmd_pop_SSX),
169
                   .din(master_in_SSX),
170
                   .dout(master_out_SSX),
171
                   .empty(master_empty_SSX),
172
                   .full(master_full_SSX)
173
                   );
174
 
175 14 eyalhoc
ENDLOOP SX
176 2 eyalhoc
 
177
endmodule
178
 
179
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.