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[/] [axi_master/] [trunk/] [src/] [base/] [ic_wdata.v] - Blame information for rev 16

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1 2 eyalhoc
<##//////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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//////////////////////////////////////////////////////////////////##>
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30 16 eyalhoc
 
31 2 eyalhoc
OUTFILE PREFIX_ic_wdata.v
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ITER MX
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ITER SX
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module PREFIX_ic_wdata (PORTS);
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   parameter                              STRB_BITS  = DATA_BITS/8;
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   input                                      clk;
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   input                                      reset;
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   port                                       MMX_AWGROUP_IC_AXI_CMD;
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   port                                       MMX_WGROUP_IC_AXI_W;
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   revport                                    SSX_WGROUP_IC_AXI_W;
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   input                                      SSX_AWVALID;
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   input                                      SSX_AWREADY;
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   input [MSTR_BITS-1:0]      SSX_AWMSTR;
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   parameter                              WBUS_WIDTH = GONCAT(GROUP_IC_AXI_W.IN.WIDTH +);
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   wire [WBUS_WIDTH-1:0]           SSX_WBUS;
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   wire [WBUS_WIDTH-1:0]           MMX_WBUS;
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   wire [SLV_BITS-1:0]             MMX_WSLV;
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   wire                                       MMX_WOK;
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   wire                                       SSX_MMX;
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   CREATE ic_registry_wr.v def_ic.txt
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   PREFIX_ic_registry_wr
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     PREFIX_ic_registry_wr (
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                            .clk(clk),
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                            .reset(reset),
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                            .MMX_AWSLV(MMX_AWSLV),
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                            .MMX_AWID(MMX_AWID),
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                            .MMX_AWVALID(MMX_AWVALID),
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                            .MMX_AWREADY(MMX_AWREADY),
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                            .MMX_WID(MMX_WID),
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                            .MMX_WVALID(MMX_WVALID),
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                            .MMX_WREADY(MMX_WREADY),
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                            .MMX_WLAST(MMX_WLAST),
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                            .MMX_WSLV(MMX_WSLV),
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                            .MMX_WOK(MMX_WOK),
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                        .SSX_AWVALID(SSX_AWVALID),
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                        .SSX_AWREADY(SSX_AWREADY),
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                            .SSX_AWMSTR(SSX_AWMSTR),
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                        .SSX_WVALID(SSX_WVALID),
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                        .SSX_WREADY(SSX_WREADY),
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                        .SSX_WLAST(SSX_WLAST),
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                            STOMP ,
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                            );
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   assign                               SSX_MMX  = (MMX_WSLV == 'dSX) & MMX_WOK & MMX_WVALID;
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   assign                               MMX_WBUS = {GONCAT(MMX_WGROUP_IC_AXI_W.IN ,)};
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   assign                               SSX_WBUS = CONCAT((MMX_WBUS & {WBUS_WIDTH{SSX_MMX}}) |);
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   assign                               {GONCAT(SSX_WGROUP_IC_AXI_W.IN ,)} = SSX_WBUS;
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LOOP MX
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   assign                               MMX_WREADY =
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                                        SSX_MMX ? SSX_WREADY :
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                                        1'b0;
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ENDLOOP MX
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endmodule
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