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[/] [axi_vga/] [trunk/] [model/] [axi_hp_slave.v] - Blame information for rev 4

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1 3 hugoliu
 
2
`define read_ready_time  10
3
`define read_ready_timeX  5
4
`define write_ready_time 3
5
//Author: Hugoliu Date:20160904
6
//The test model for AXI3 slave port
7
 
8
module HP_slave(
9
    S_AXI_ARESETN,
10
    S_AXI_ACLK,
11
 
12
//Slave port    
13
    S_AXI_HP_araddr,
14
    S_AXI_HP_arburst,
15
    S_AXI_HP_arcache,
16
    S_AXI_HP_arid,
17
    S_AXI_HP_arlen,
18
    S_AXI_HP_arlock,
19
    S_AXI_HP_arprot,
20
    S_AXI_HP_arqos,
21
    S_AXI_HP_arready,
22
    S_AXI_HP_arsize,
23
    S_AXI_HP_arvalid,
24
    S_AXI_HP_awaddr,
25
    S_AXI_HP_awburst,
26
    S_AXI_HP_awcache,
27
    S_AXI_HP_awid,
28
    S_AXI_HP_awlen,
29
    S_AXI_HP_awlock,
30
    S_AXI_HP_awprot,
31
    S_AXI_HP_awqos,
32
    S_AXI_HP_awready,
33
    S_AXI_HP_awsize,
34
    S_AXI_HP_awvalid,
35
    S_AXI_HP_bid,
36
    S_AXI_HP_bready,
37
    S_AXI_HP_bresp,
38
    S_AXI_HP_bvalid,
39
    S_AXI_HP_rdata,
40
    S_AXI_HP_rid,
41
    S_AXI_HP_rlast,
42
    S_AXI_HP_rready,
43
    S_AXI_HP_rresp,
44
    S_AXI_HP_rvalid,
45
    S_AXI_HP_wdata,
46
    S_AXI_HP_wid,
47
    S_AXI_HP_wlast,
48
    S_AXI_HP_wready,
49
    S_AXI_HP_wstrb,
50
    S_AXI_HP_wvalid,
51
//Slave port    
52
    S_AXI_HP1_araddr,
53
    S_AXI_HP1_arburst,
54
    S_AXI_HP1_arcache,
55
    S_AXI_HP1_arid,
56
    S_AXI_HP1_arlen,
57
    S_AXI_HP1_arlock,
58
    S_AXI_HP1_arprot,
59
    S_AXI_HP1_arqos,
60
    S_AXI_HP1_arready,
61
    S_AXI_HP1_arsize,
62
    S_AXI_HP1_arvalid,
63
    S_AXI_HP1_awaddr,
64
    S_AXI_HP1_awburst,
65
    S_AXI_HP1_awcache,
66
    S_AXI_HP1_awid,
67
    S_AXI_HP1_awlen,
68
    S_AXI_HP1_awlock,
69
    S_AXI_HP1_awprot,
70
    S_AXI_HP1_awqos,
71
    S_AXI_HP1_awready,
72
    S_AXI_HP1_awsize,
73
    S_AXI_HP1_awvalid,
74
    S_AXI_HP1_bid,
75
    S_AXI_HP1_bready,
76
    S_AXI_HP1_bresp,
77
    S_AXI_HP1_bvalid,
78
    S_AXI_HP1_rdata,
79
    S_AXI_HP1_rid,
80
    S_AXI_HP1_rlast,
81
    S_AXI_HP1_rready,
82
    S_AXI_HP1_rresp,
83
    S_AXI_HP1_rvalid,
84
    S_AXI_HP1_wdata,
85
    S_AXI_HP1_wid,
86
    S_AXI_HP1_wlast,
87
    S_AXI_HP1_wready,
88
    S_AXI_HP1_wstrb,
89
    S_AXI_HP1_wvalid
90
 
91
 
92
                 );
93
//system signal
94
input     S_AXI_ARESETN,
95
          S_AXI_ACLK;
96
 
97
 
98
  // Slave Interface Write Address channel Ports
99
//HP slave port
100
//write address phase
101
  input [31:0] S_AXI_HP_awaddr;
102
  input [1:0]  S_AXI_HP_awburst;
103
  input [3:0]  S_AXI_HP_awcache;
104
  input [5:0]  S_AXI_HP_awid;
105
  input [3:0]  S_AXI_HP_awlen;
106
  input [1:0]  S_AXI_HP_awlock;
107
  input [2:0]  S_AXI_HP_awprot;
108
  input [3:0]  S_AXI_HP_awqos;
109
  output       S_AXI_HP_awready;
110
  input [2:0]  S_AXI_HP_awsize;
111
  input        S_AXI_HP_awvalid;
112
//write response phase 
113
  output [5:0] S_AXI_HP_bid;
114
  input        S_AXI_HP_bready;
115
  output [1:0] S_AXI_HP_bresp;
116
  output       S_AXI_HP_bvalid;
117
  //write data phase
118
  input [63:0] S_AXI_HP_wdata;
119
  input [5:0]  S_AXI_HP_wid;
120
  input        S_AXI_HP_wlast;
121
  output       S_AXI_HP_wready;
122
  input [7:0]  S_AXI_HP_wstrb;
123
  input        S_AXI_HP_wvalid;
124
 
125
//read address pahse
126
  input [31:0] S_AXI_HP_araddr;
127
  input [1:0]  S_AXI_HP_arburst;
128
  input [3:0]  S_AXI_HP_arcache;
129
  input [5:0]  S_AXI_HP_arid;
130
  input [3:0]  S_AXI_HP_arlen;
131
  input [1:0]  S_AXI_HP_arlock;
132
  input [2:0]  S_AXI_HP_arprot;
133
  input [3:0]  S_AXI_HP_arqos;
134
  output       S_AXI_HP_arready;
135
  input [2:0]  S_AXI_HP_arsize;
136
  input        S_AXI_HP_arvalid;
137
//read data phase  
138
  output [63:0]S_AXI_HP_rdata;
139
  output [5:0] S_AXI_HP_rid;
140
  output       S_AXI_HP_rlast;
141
  input        S_AXI_HP_rready;
142
  output [1:0] S_AXI_HP_rresp;
143
  output       S_AXI_HP_rvalid;
144
//////////////////////////////////////////////
145
//HP1 slave port
146
//write address phase
147
  input [31:0] S_AXI_HP1_awaddr;
148
  input [1:0]  S_AXI_HP1_awburst;
149
  input [3:0]  S_AXI_HP1_awcache;
150
  input [5:0]  S_AXI_HP1_awid;
151
  input [3:0]  S_AXI_HP1_awlen;
152
  input [1:0]  S_AXI_HP1_awlock;
153
  input [2:0]  S_AXI_HP1_awprot;
154
  input [3:0]  S_AXI_HP1_awqos;
155
  output       S_AXI_HP1_awready;
156
  input [2:0]  S_AXI_HP1_awsize;
157
  input        S_AXI_HP1_awvalid;
158
//write response phase 
159
  output [5:0] S_AXI_HP1_bid;
160
  input        S_AXI_HP1_bready;
161
  output [1:0] S_AXI_HP1_bresp;
162
  output       S_AXI_HP1_bvalid;
163
  //write data phase
164
  input [63:0] S_AXI_HP1_wdata;
165
  input [5:0]  S_AXI_HP1_wid;
166
  input        S_AXI_HP1_wlast;
167
  output       S_AXI_HP1_wready;
168
  input [7:0]  S_AXI_HP1_wstrb;
169
  input        S_AXI_HP1_wvalid;
170
 
171
//read address pahse
172
  input [31:0] S_AXI_HP1_araddr;
173
  input [1:0]  S_AXI_HP1_arburst;
174
  input [3:0]  S_AXI_HP1_arcache;
175
  input [5:0]  S_AXI_HP1_arid;
176
  input [3:0]  S_AXI_HP1_arlen;
177
  input [1:0]  S_AXI_HP1_arlock;
178
  input [2:0]  S_AXI_HP1_arprot;
179
  input [3:0]  S_AXI_HP1_arqos;
180
  output       S_AXI_HP1_arready;
181
  input [2:0]  S_AXI_HP1_arsize;
182
  input        S_AXI_HP1_arvalid;
183
//read data phase  
184
  output [63:0]S_AXI_HP1_rdata;
185
  output [5:0] S_AXI_HP1_rid;
186
  output       S_AXI_HP1_rlast;
187
  input        S_AXI_HP1_rready;
188
  output [1:0] S_AXI_HP1_rresp;
189
  output       S_AXI_HP1_rvalid;
190
 
191
// 
192
//read phase
193
wire [1:0] S_AXI_HP_rresp = 2'b0;
194
reg S_AXI_HP_arready;
195
wire [63:0]S_AXI_HP_rdata;
196
wire [5:0] S_AXI_HP_rid;
197
wire      S_AXI_HP_rlast;
198
reg       S_AXI_HP_rvalid;
199
//control
200
reg [3:0] read_addr_count_w, read_addr_count_r;
201
reg [3:0] read_data_count;
202
reg [5:0] space_count;
203
reg       ready_for_read;
204
//FIFO keep
205
reg [31:0] s_axi_araddr[31:0];
206
reg [5:0] s_axi_arid[15:0];
207
 
208
wire [3:0] stop_addr_read_ok2 = (read_addr_count_r - 2);
209
wire [3:0] stop_addr_read_ok = (read_addr_count_r - 1);
210
wire stop_addr_read1 = (read_addr_count_w == stop_addr_read_ok2);
211
wire stop_addr_read = (read_addr_count_w == stop_addr_read_ok);
212
 
213
wire read_data_finish = ((read_addr_count_w -1) == read_addr_count_r) & S_AXI_HP_rlast;
214
wire read_data_go = (space_count == `read_ready_timeX);
215
reg first_read_addr, first_read_addr_d;
216
 
217
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
218
   if (!S_AXI_ARESETN)                         S_AXI_HP_arready <= 1'b1;
219
   else if (stop_addr_read | stop_addr_read1)  S_AXI_HP_arready <= 1'b0;
220
   else if (S_AXI_HP_arvalid)                  S_AXI_HP_arready <= 1'b1;
221
end
222
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
223
   if (!S_AXI_ARESETN)                             read_addr_count_w <= 0;
224
   else if (read_data_finish)                      read_addr_count_w <= 0;
225
   else if (stop_addr_read)                        read_addr_count_w <= read_addr_count_w;
226
   else if (S_AXI_HP_arvalid & S_AXI_HP_arready)   read_addr_count_w <= read_addr_count_w + 1;
227
end
228
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
229
   if (!S_AXI_ARESETN)                             read_addr_count_r <= 0;
230
   else if (read_data_finish & first_read_addr)    read_addr_count_r <= 0; //read_addr_count_r;
231
   else if (S_AXI_HP_rlast)                        read_addr_count_r <= read_addr_count_r + 1;
232
end
233
always @(posedge S_AXI_ACLK) begin
234
   if (S_AXI_HP_arready & S_AXI_HP_arvalid)  begin
235
          s_axi_araddr[read_addr_count_w] <= S_AXI_HP_araddr;
236
          s_axi_arid[read_addr_count_w]   <= S_AXI_HP_arid;
237
   end
238
end
239
//
240
 
241
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
242
   if (!S_AXI_ARESETN)                              first_read_addr <= 0;
243
   else if (read_data_finish)                       first_read_addr <= 0;
244
   else if (S_AXI_HP_arvalid & S_AXI_HP_arready)    first_read_addr <= 1;
245
end
246
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
247
   if (!S_AXI_ARESETN)   first_read_addr_d <= 0;
248
   else                  first_read_addr_d <= first_read_addr;
249
end
250
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
251
   if (!S_AXI_ARESETN)                              ready_for_read <= 0;
252
   else if (space_count == `read_ready_timeX)       ready_for_read <= 0;
253
   else if (first_read_addr & !first_read_addr_d)   ready_for_read <= 1;
254
   else if (S_AXI_HP_rlast)                         ready_for_read <= 1;
255
end
256
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
257
   if (!S_AXI_ARESETN)                              space_count <= 0;
258
   else if (ready_for_read)                         space_count <= space_count + 1;
259
   else                                             space_count <= 0;
260
end
261
//
262
wire read_data_ok = S_AXI_HP_rvalid & S_AXI_HP_rready;
263
assign S_AXI_HP_rlast = (read_data_count == S_AXI_HP_arlen) & read_data_ok;
264
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
265
   if (!S_AXI_ARESETN)                              S_AXI_HP_rvalid <= 0;
266
   else if (S_AXI_HP_rlast | read_data_finish)      S_AXI_HP_rvalid <= 0;
267
   else if (read_data_go)                           S_AXI_HP_rvalid <= 1;
268
end
269
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
270
   if (!S_AXI_ARESETN)                              read_data_count <= 0;
271
   else if (S_AXI_HP_rlast)                         read_data_count <= 0;
272
   else if (read_data_ok)                           read_data_count <= read_data_count + 1;
273
end
274
//
275
assign S_AXI_HP_rid = s_axi_arid[read_addr_count_r];
276
wire [31:0] tmp_read_addr = s_axi_araddr[read_addr_count_r];
277
//////////////////////////////////////////////////////////////////////////
278
///////////////////////////////////////////////////////////////////////////////////////////////
279
// write phase
280
///////////////////////////////////////////////////////////////////////////////////////////////
281
//write address phase
282
  wire  [31:0] S_AXI_HP_awaddr;
283
  wire  [1:0]  S_AXI_HP_awburst;
284
  wire  [3:0]  S_AXI_HP_awcache;
285
  wire  [5:0]  S_AXI_HP_awid;
286
  wire  [3:0]  S_AXI_HP_awlen;
287
  wire  [1:0]  S_AXI_HP_awlock;
288
  wire  [2:0]  S_AXI_HP_awprot;
289
  wire  [3:0]  S_AXI_HP_awqos;
290
  reg          S_AXI_HP_awready;
291
  wire  [2:0]  S_AXI_HP_awsize;
292
  wire         S_AXI_HP_awvalid;
293
//write response phase 
294
  wire  [5:0]  S_AXI_HP_bid;
295
  wire         S_AXI_HP_bready;
296
  wire   [1:0] S_AXI_HP_bresp = 2'b0;
297
  reg          S_AXI_HP_bvalid;
298
  //write data phase
299
  wire  [63:0] S_AXI_HP_wdata;
300
  wire  [5:0]  S_AXI_HP_wid;
301
  wire         S_AXI_HP_wlast;
302
  reg          S_AXI_HP_wready;
303
  wire  [7:0]  S_AXI_HP_wstrb;
304
  wire         S_AXI_HP_wvalid;
305
 
306
//////////////////////////////////////////////////////
307
//control
308
reg [3:0] write_addr_count_w, write_addr_count_r;
309
reg [3:0] write_data_count;
310
reg [5:0] w_space_count;
311
reg       ready_for_write;
312
//FIFO keep
313
reg [31:0] s_axi_awaddr[31:0];
314
reg [5:0]  s_axi_awid[15:0];
315
 
316
wire [3:0] stop_addr_write_ok2 = (write_addr_count_r - 2);
317
wire [3:0] stop_addr_write_ok = (write_addr_count_r - 1);
318
wire stop_addr_write1 = (write_addr_count_w == stop_addr_write_ok2);
319
wire stop_addr_write  = (write_addr_count_w == stop_addr_write_ok);
320
 
321
wire write_data_finish = ((write_addr_count_w) == write_addr_count_r) & (write_addr_count_w != 0);
322
wire write_data_go     = (w_space_count == `write_ready_time);
323
reg  first_write_addr, first_write_addr_d;
324
 
325
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
326
   if (!S_AXI_ARESETN)                              S_AXI_HP_awready <= 1'b1;
327
   else if (stop_addr_write | stop_addr_write1)     S_AXI_HP_awready <= 1'b0;
328
   else if (S_AXI_HP_awvalid)                       S_AXI_HP_awready <= 1'b1;
329
end
330
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
331
   if (!S_AXI_ARESETN)                              write_addr_count_w <= 0;
332
   else if (stop_addr_write)                        write_addr_count_w <= write_addr_count_w;
333
   else if (S_AXI_HP_awvalid & S_AXI_HP_awready)    write_addr_count_w <= write_addr_count_w + 1;
334
end
335
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
336
   if (!S_AXI_ARESETN)                              write_addr_count_r <= 0;
337
   else if (write_data_finish & first_write_addr)   write_addr_count_r <= write_addr_count_r;
338
   else if (S_AXI_HP_wlast)                         write_addr_count_r <= write_addr_count_r + 1;
339
end
340
always @(posedge S_AXI_ACLK) begin
341
   if (S_AXI_HP_awready & S_AXI_HP_awvalid)  begin
342
          s_axi_awaddr[write_addr_count_w] <= S_AXI_HP_awaddr;
343
          s_axi_awid[write_addr_count_w]   <= S_AXI_HP_awid;
344
   end
345
end
346
//
347
 
348
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
349
   if (!S_AXI_ARESETN)                              first_write_addr <= 0;
350
   else if (write_data_finish)                      first_write_addr <= 0;
351
   else if (S_AXI_HP_awvalid & S_AXI_HP_awready)    first_write_addr <= 1;
352
end
353
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
354
   if (!S_AXI_ARESETN)   first_write_addr_d <= 0;
355
   else                  first_write_addr_d <= first_write_addr;
356
end
357
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
358
   if (!S_AXI_ARESETN)                               ready_for_write <= 0;
359
   else if (w_space_count == `write_ready_time)      ready_for_write <= 0;
360
   else if (first_write_addr & !first_write_addr_d)  ready_for_write <= 1;
361
   else if (S_AXI_HP_bvalid)                         ready_for_write <= 1;
362
end
363
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
364
   if (!S_AXI_ARESETN)                              w_space_count <= 0;
365
   else if (ready_for_write)                        w_space_count <= w_space_count + 1;
366
   else                                             w_space_count <= 0;
367
end
368
//
369
reg [2:0] write_data_resp;
370
wire write_data_ok = S_AXI_HP_wvalid & S_AXI_HP_wready;
371
//assign S_AXI_HP_bvalid = (write_data_count == S_AXI_HP_awlen) & (write_data_resp == 3'h7);
372
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
373
   if (!S_AXI_ARESETN)                              S_AXI_HP_bvalid <= 0;
374
   else                                             S_AXI_HP_bvalid <= S_AXI_HP_wlast;
375
end
376
 
377
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
378
   if (!S_AXI_ARESETN)                              S_AXI_HP_wready <= 0;
379
   else if (S_AXI_HP_bvalid | write_data_finish)    S_AXI_HP_wready <= 0;
380
   else if (write_data_go)                          S_AXI_HP_wready <= 1;
381
end
382
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
383
   if (!S_AXI_ARESETN)                              write_data_count <= 0;
384
   else if (S_AXI_HP_wlast)                         write_data_count <= 0;
385
   else if (write_data_ok)                          write_data_count <= write_data_count + 1;
386
end
387
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
388
   if (!S_AXI_ARESETN)                              write_data_resp <= 0;
389
   else if (write_data_finish)                      write_data_resp <= 0;
390
   else if (S_AXI_HP_wlast )                        write_data_resp <= write_data_resp + 1;
391
//   else                                             write_data_resp <= 0;
392
end
393
assign S_AXI_HP_bid = s_axi_awid[write_addr_count_r];
394
wire [31:0] tmp_write_addr = s_axi_awaddr[write_addr_count_r];
395
////////////////////////////////////////////////////////////////////////////////////////////
396
///HP1
397
////////////////////////////////////////////////////////////////////////////////////////////
398
//read phase
399
wire [1:0] S_AXI_HP1_rresp = 2'b0;
400
reg        S_AXI_HP1_arready;
401
wire [63:0]S_AXI_HP1_rdata;
402
wire [5:0] S_AXI_HP1_rid;
403
wire       S_AXI_HP1_rlast;
404
reg        S_AXI_HP1_rvalid;
405
//control
406
reg [3:0] read1_addr_count_w, read1_addr_count_r;
407
reg [3:0] read1_data_count;
408
reg [5:0] space1_count;
409
reg       ready1_for_read;
410
//FIFO keep
411
reg [31:0] s_axi1_araddr[31:0];
412
reg [5:0] s_axi1_arid[15:0];
413
 
414
wire [3:0] stop1_addr_read_ok2 = (read1_addr_count_r - 2);
415
wire [3:0] stop1_addr_read_ok  = (read1_addr_count_r - 1);
416
wire stop1_addr_read1          = (read1_addr_count_w == stop1_addr_read_ok2);
417
wire stop1_addr_read           = (read1_addr_count_w == stop1_addr_read_ok);
418
 
419
//wire read1_data_finish = ((read1_addr_count_w -1) == read1_addr_count_r);
420
wire read1_data_finish = ((read1_addr_count_w ) == read1_addr_count_r);
421
wire read1_data_go     = (space1_count == `read_ready_time);
422
reg first1_read_addr, first1_read_addr_d;
423
 
424
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
425
   if (!S_AXI_ARESETN)                              S_AXI_HP1_arready <= 1'b1;
426
   else if (stop1_addr_read | stop1_addr_read1)     S_AXI_HP1_arready <= 1'b0;
427
   else if (S_AXI_HP1_arvalid)                      S_AXI_HP1_arready <= 1'b1;
428
end
429
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
430
   if (!S_AXI_ARESETN)                              read1_addr_count_w <= 0;
431
   else if (stop1_addr_read)                        read1_addr_count_w <= read1_addr_count_w;
432
   else if (S_AXI_HP1_arvalid & S_AXI_HP1_arready)  read1_addr_count_w <= read1_addr_count_w + 1;
433
end
434
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
435
   if (!S_AXI_ARESETN)                            read1_addr_count_r <= 0;
436
   else if (read1_data_finish & first1_read_addr) read1_addr_count_r <= read1_addr_count_r;
437
   else if (S_AXI_HP1_rlast)                      read1_addr_count_r <= read1_addr_count_r + 1;
438
end
439
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
440
   if (!S_AXI_ARESETN)  begin
441
          s_axi1_araddr[0] <= 0;
442
          s_axi1_arid[0]   <= 0;
443
   end else if (S_AXI_HP1_arready & S_AXI_HP1_arvalid)  begin
444
          s_axi1_araddr[read1_addr_count_w] <= S_AXI_HP1_araddr;
445
          s_axi1_arid[read1_addr_count_w]   <= S_AXI_HP1_arid;
446
   end
447
end
448
//
449
 
450
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
451
   if (!S_AXI_ARESETN)                               first1_read_addr <= 0;
452
   else if (read1_data_finish)                       first1_read_addr <= 0;
453
   else if (S_AXI_HP1_arvalid & S_AXI_HP1_arready)   first1_read_addr <= 1;
454
end
455
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
456
   if (!S_AXI_ARESETN)   first1_read_addr_d <= 0;
457
   else                  first1_read_addr_d <= first1_read_addr;
458
end
459
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
460
   if (!S_AXI_ARESETN)                               ready1_for_read <= 0;
461
   else if (space1_count == `read_ready_time)        ready1_for_read <= 0;
462
   else if (first1_read_addr & !first1_read_addr_d)  ready1_for_read <= 1;
463
   else if (S_AXI_HP1_rlast)                         ready1_for_read <= 1;
464
end
465
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
466
   if (!S_AXI_ARESETN)                           space1_count <= 0;
467
   else if (ready1_for_read)                     space1_count <= space1_count + 1;
468
   else                                          space1_count <= 0;
469
end
470
//
471
wire read1_data_ok = S_AXI_HP1_rvalid & S_AXI_HP1_rready;
472
assign S_AXI_HP1_rlast = (read1_data_count == S_AXI_HP1_arlen) & read1_data_ok;
473
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
474
   if (!S_AXI_ARESETN)                              S_AXI_HP1_rvalid <= 0;
475
   else if (S_AXI_HP1_rlast | read1_data_finish)    S_AXI_HP1_rvalid <= 0;
476
   else if (read1_data_go)                          S_AXI_HP1_rvalid <= 1;
477
end
478
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
479
   if (!S_AXI_ARESETN)                            read1_data_count <= 0;
480
   else if (S_AXI_HP1_rlast)                      read1_data_count <= 0;
481
   else if (read1_data_ok)                        read1_data_count <= read1_data_count + 1;
482
end
483
//
484
assign S_AXI_HP1_rid = s_axi1_arid[read1_addr_count_r];
485
wire [31:0] tmp1_read_addr = s_axi1_araddr[read1_addr_count_r];
486
//////////////////////////////////////////////////////////////////////////
487
///////////////////////////////////////////////////////////////////////////////////////////////
488
// write phase
489
///////////////////////////////////////////////////////////////////////////////////////////////
490
//write address phase
491
  wire  [31:0] S_AXI_HP1_awaddr;
492
  wire  [1:0]  S_AXI_HP1_awburst;
493
  wire  [3:0]  S_AXI_HP1_awcache;
494
  wire  [5:0]  S_AXI_HP1_awid;
495
  wire  [3:0]  S_AXI_HP1_awlen;
496
  wire  [1:0]  S_AXI_HP1_awlock;
497
  wire  [2:0]  S_AXI_HP1_awprot;
498
  wire  [3:0]  S_AXI_HP1_awqos;
499
  reg          S_AXI_HP1_awready;
500
  wire  [2:0]  S_AXI_HP1_awsize;
501
  wire         S_AXI_HP1_awvalid;
502
//write response phase 
503
  wire  [5:0]  S_AXI_HP1_bid;
504
  wire         S_AXI_HP1_bready;
505
  wire   [1:0] S_AXI_HP1_bresp = 2'b0;
506
  reg          S_AXI_HP1_bvalid;
507
  //write data phase   
508
  wire  [63:0] S_AXI_HP1_wdata;
509
  wire  [5:0]  S_AXI_HP1_wid;
510
  wire         S_AXI_HP1_wlast;
511
  reg          S_AXI_HP1_wready;
512
  wire  [7:0]  S_AXI_HP1_wstrb;
513
  wire         S_AXI_HP1_wvalid;
514
//////////////////////////////////////////////////////
515
//control
516
reg [3:0] write_addr_count1_w, write_addr_count1_r;
517
reg [3:0] write_data_count1;
518
reg [5:0] w_space_count1;
519
reg       ready_for_write1;
520
//FIFO keep
521
reg [31:0] s_axi_awaddr1[31:0];
522
reg [5:0]  s_axi_awid1[15:0];
523
 
524
wire [3:0] stop_addr_write1_ok2 = (write_addr_count1_r - 2);
525
wire [3:0] stop_addr_write1_ok = (write_addr_count1_r - 1);
526
wire stop_addr_write1_1 = (write_addr_count1_w == stop_addr_write1_ok2);
527
wire stop_addr_write_1  = (write_addr_count1_w == stop_addr_write1_ok);
528
 
529
//wire write_data1_finish = ((write_addr_count1_w -1) == write_addr_count1_r);
530
wire write_data1_finish = ((write_addr_count1_w) == write_addr_count1_r) & (write_addr_count1_w != 0);
531
wire write_data1_go     = (w_space_count1 == `write_ready_time);
532
reg  first1_write_addr, first1_write_addr_d;
533
 
534
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
535
   if (!S_AXI_ARESETN)                              S_AXI_HP1_awready <= 1'b1;
536
   else if (stop_addr_write_1 | stop_addr_write1_1) S_AXI_HP1_awready <= 1'b0;
537
   else if (S_AXI_HP1_awvalid)                      S_AXI_HP1_awready <= 1'b1;
538
end
539
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
540
   if (!S_AXI_ARESETN)                                write_addr_count1_w <= 0;
541
   else if (stop_addr_write_1)                        write_addr_count1_w <= write_addr_count1_w;
542
   else if (S_AXI_HP1_awvalid & S_AXI_HP1_awready)    write_addr_count1_w <= write_addr_count1_w + 1;
543
end
544
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
545
   if (!S_AXI_ARESETN)                              write_addr_count1_r <= 0;
546
   else if (write_data1_finish & first1_write_addr) write_addr_count1_r <= write_addr_count1_r;
547
   else if (S_AXI_HP1_wlast & S_AXI_HP1_wvalid & S_AXI_HP1_wready) write_addr_count1_r <= write_addr_count1_r + 1;
548
end
549
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
550
   if (!S_AXI_ARESETN) begin
551
          s_axi_awaddr1[0] <= 0;
552
          s_axi_awid1[0]    <= 0;
553
   end else if (S_AXI_HP1_awready & S_AXI_HP1_awvalid)  begin
554
          s_axi_awaddr1[write_addr_count1_w] <= S_AXI_HP1_awaddr;
555
          s_axi_awid1[write_addr_count1_w]    <= S_AXI_HP1_awid;
556
   end
557
end
558
//To check addr and data count
559
reg [31:0] count_addr, count_data;
560
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
561
   if (!S_AXI_ARESETN)                              count_addr <= 0;
562
   else if (S_AXI_HP1_awvalid & S_AXI_HP1_awready)  count_addr <= count_addr + 1;
563
end
564
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
565
   if (!S_AXI_ARESETN)                                             count_data <= 0;
566
   else if (S_AXI_HP1_wlast & S_AXI_HP1_wvalid & S_AXI_HP1_wready) count_data <= count_data + 1;
567
end
568
 
569
//
570
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
571
   if (!S_AXI_ARESETN)                              first1_write_addr <= 0;
572
   else if (write_data1_finish)                      first1_write_addr <= 0;
573
   else if (S_AXI_HP1_awvalid & S_AXI_HP1_awready)  first1_write_addr <= 1;
574
end
575
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
576
   if (!S_AXI_ARESETN)   first1_write_addr_d <= 0;
577
   else                  first1_write_addr_d <= first1_write_addr;
578
end
579
 
580
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
581
   if (!S_AXI_ARESETN)                                ready_for_write1 <= 0;
582
   else if (w_space_count1 == `write_ready_time)      ready_for_write1 <= 0;
583
   else if (first1_write_addr & !first1_write_addr_d) ready_for_write1 <= 1;
584
   else if (S_AXI_HP1_bvalid)                         ready_for_write1 <= 1;
585
end
586
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
587
   if (!S_AXI_ARESETN)                              w_space_count1 <= 0;
588
   else if (ready_for_write1)                       w_space_count1 <= w_space_count1 + 1;
589
   else                                             w_space_count1 <= 0;
590
end
591
//
592
reg [2:0] write_data1_resp;
593
wire write_data1_ok = S_AXI_HP1_wvalid & S_AXI_HP1_wready;
594
//assign S_AXI_HP_bvalid = (write_data_count == S_AXI_HP_awlen) & (write_data_resp == 3'h7);
595
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
596
   if (!S_AXI_ARESETN)                              S_AXI_HP1_bvalid <= 0;
597
   else                                             S_AXI_HP1_bvalid <= S_AXI_HP1_wlast;
598
end
599
 
600
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
601
   if (!S_AXI_ARESETN)                               S_AXI_HP1_wready <= 0;
602
   else if (S_AXI_HP1_bvalid | write_data1_finish)   S_AXI_HP1_wready <= 0;
603
   else if (write_data1_go)                          S_AXI_HP1_wready <= 1;
604
end
605
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
606
   if (!S_AXI_ARESETN)                              write_data_count1 <= 0;
607
   else if (S_AXI_HP1_wlast)                        write_data_count1 <= 0;
608
   else if (write_data1_ok)                         write_data_count1 <= write_data_count1 + 1;
609
end
610
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
611
   if (!S_AXI_ARESETN)                              write_data1_resp <= 0;
612
   else if (write_data1_finish)                     write_data1_resp <= 0;
613
   else if (S_AXI_HP1_wlast )                       write_data1_resp <= write_data1_resp + 1;
614
//   else                                             write_data_resp <= 0;
615
end
616
assign S_AXI_HP1_bid = s_axi_awid1[write_addr_count1_r];
617
wire [31:0] tmp_write_addr1 = s_axi_awaddr1[write_addr_count1_r];
618
 
619
//
620
sram U_sram(
621
     .clk     (S_AXI_ACLK),
622
     //port0
623
     .we      (write_data_ok ),
624
     .a       ({tmp_write_addr[26:3] + write_data_count}),
625
     .dpra    ({tmp_read_addr[26:3] + read_data_count}),
626
     .di      (S_AXI_HP_wdata),
627
     .dpo     (S_AXI_HP_rdata),
628
     //port1
629
     .dpra1   ({tmp1_read_addr[26:3] + read1_data_count}),
630
     .dpo1    (S_AXI_HP1_rdata),
631
     .a1       ({tmp_write_addr1[26:3] + write_data_count1}),
632
     .we1      (write_data1_ok ),
633
     .di1      (S_AXI_HP1_wdata)
634
     );
635
 
636
endmodule

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