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[/] [axi_vga/] [trunk/] [model/] [sram.v] - Blame information for rev 3

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1 3 hugoliu
`define ram_len 24
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//`define ram_dep (16*1024 * 1024)  //2^12
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`define ram_dep (1024 * 1024)  //2^12
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module sram (clk, we, a, dpra, di, dpo,
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             dpra1, dpo1, we1, a1, di1
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              );
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input clk;
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//input [1:0] we;
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input  we;
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input  [`ram_len - 1:0] a;
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input  [`ram_len - 1:0] dpra;
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input  [63:0] di;
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//output [63:0] spo;
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output [63:0] dpo;
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//port1
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input  [`ram_len - 1:0] dpra1;
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output [63:0] dpo1;
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input  we1;
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input  [`ram_len - 1:0] a1;
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input  [63:0] di1;
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//
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reg     [63:0] ram [`ram_dep-1:0];
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initial begin
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   $readmemh("test.txt", ram);
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end
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//
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always @(posedge clk) begin
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   if (we) ram[a] <= di;
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   if (we1) ram[a1] <= di1;
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end
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assign dpo = ram[dpra];
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assign dpo1 = ram[dpra1];
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endmodule

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