Subversion Repositories axi_vga

`define ram_len 24

//`define ram_dep (16*1024 * 1024)  //2^12

`define ram_dep (1024 * 1024)  //2^12

module sram (clk, we, a, dpra, di, dpo,

             dpra1, dpo1, we1, a1, di1

              );

input clk;

//input [1:0] we;

input  we;

input  [`ram_len - 1:0] a;

input  [`ram_len - 1:0] dpra;

input  [63:0] di;

//output [63:0] spo;

output [63:0] dpo;

//port1

input  [`ram_len - 1:0] dpra1;

output [63:0] dpo1;

input  we1;

input  [`ram_len - 1:0] a1;

input  [63:0] di1;

//

reg     [63:0] ram [`ram_dep-1:0];

initial begin

   $readmemh("test.txt", ram);

end

//

always @(posedge clk) begin

   if (we) ram[a] <= di;

   if (we1) ram[a1] <= di1;

end

assign dpo = ram[dpra];

assign dpo1 = ram[dpra1];

endmodule