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[/] [axi_vga/] [trunk/] [model/] [vga_test.v] - Blame information for rev 3

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`define ram_dep (1024 * 1024)  //2^12
 
module vga_test (
         reset_n   ,
         pixel_clk ,
         hsync     ,
         vsync                  ,
         de                              ,
         r8        ,
         g8        ,
         b8
   );
input reset_n, pixel_clk, hsync,vsync,de;
input [7:0] r8, g8, b8;
 
reg     [63:0] ram [`ram_dep-1:0];
initial begin
$readmemh("test.txt", ram);
end
 
reg vsync_d, hsync_d;
reg [15:0] countX, countY, count_de;
reg [23:0] count_data;
reg [7:0] r8_d, g8_d, b8_d;
wire vsync_high_puls = vsync & !vsync_d;
wire hsync_high_puls = hsync & !hsync_d;
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n) count_de <= 0;
       else if (de)  count_de <= count_de +1;
       else          count_de <= 0;
end
wire active_line_err = (count_de > 800);
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               count_data <= 0;
       else if (vsync_high_puls)   count_data <= 0;
       else if (de)  count_data <= count_data +1;
end
always @(posedge pixel_clk) vsync_d <= vsync;
always @(posedge pixel_clk) hsync_d <= hsync;
 
reg data_err;
always @(posedge pixel_clk) if (de) r8_d <= r8;
always @(posedge pixel_clk) if (de) g8_d <= g8;
always @(posedge pixel_clk) if (de) b8_d <= b8;
wire [63:0] data_in = {8'h0, r8,g8,b8, 8'h0,r8_d,g8_d,b8_d};
wire [63:0] data_check = ram[count_data[23:1]];
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n) data_err <= 0;
       else if (de)  begin
            if (count_data[0]) begin
                  data_err <= (data_in != data_check);
            end
            else data_err <= 0;
       end
       else data_err <= 0;
end
 
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               countY <= 0;
       else if (vsync_high_puls)   countY <= 0;
       else if (hsync_high_puls)   countY <= countY +1;
end
reg [15:0] line_no;
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               line_no <= 0;
       else if (vsync_high_puls)   line_no <= countY;
end
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               countX <= 0;
       else if (hsync_high_puls)   countX <= 0;
       else              countX <= countX +1;
end
reg [15:0] pixel_no;
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               pixel_no <= 0;
       else if (hsync_high_puls)   pixel_no <= countX;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	3	hugoliu	`define ram_dep (1024 * 1024) //2^12
2
3			`module vga_test (`
4			`reset_n ,`
5			`pixel_clk ,`
6			`hsync ,`
7			`vsync ,`
8			`de ,`
9			`r8 ,`
10			`g8 ,`
11			`b8`
12			`);`
13			`input reset_n, pixel_clk, hsync,vsync,de;`
14			`input [7:0] r8, g8, b8;`
15
16			reg [63:0] ram [`ram_dep-1:0];
17			`initial begin`
18			`$readmemh("test.txt", ram);`
19			`end`
20
21			`reg vsync_d, hsync_d;`
22			`reg [15:0] countX, countY, count_de;`
23			`reg [23:0] count_data;`
24			`reg [7:0] r8_d, g8_d, b8_d;`
25			`wire vsync_high_puls = vsync & !vsync_d;`
26			`wire hsync_high_puls = hsync & !hsync_d;`
27			`always @(negedge reset_n or posedge pixel_clk) begin`
28			`if (!reset_n) count_de <= 0;`
29			`else if (de) count_de <= count_de +1;`
30			`else count_de <= 0;`
31			`end`
32			`wire active_line_err = (count_de > 800);`
33			`always @(negedge reset_n or posedge pixel_clk) begin`
34			`if (!reset_n) count_data <= 0;`
35			`else if (vsync_high_puls) count_data <= 0;`
36			`else if (de) count_data <= count_data +1;`
37			`end`
38			`always @(posedge pixel_clk) vsync_d <= vsync;`
39			`always @(posedge pixel_clk) hsync_d <= hsync;`
40
41			`reg data_err;`
42			`always @(posedge pixel_clk) if (de) r8_d <= r8;`
43			`always @(posedge pixel_clk) if (de) g8_d <= g8;`
44			`always @(posedge pixel_clk) if (de) b8_d <= b8;`
45			`wire [63:0] data_in = {8'h0, r8,g8,b8, 8'h0,r8_d,g8_d,b8_d};`
46			`wire [63:0] data_check = ram[count_data[23:1]];`
47			`always @(negedge reset_n or posedge pixel_clk) begin`
48			`if (!reset_n) data_err <= 0;`
49			`else if (de) begin`
50			`if (count_data[0]) begin`
51			`data_err <= (data_in != data_check);`
52			`end`
53			`else data_err <= 0;`
54			`end`
55			`else data_err <= 0;`
56			`end`
57
58			`always @(negedge reset_n or posedge pixel_clk) begin`
59			`if (!reset_n) countY <= 0;`
60			`else if (vsync_high_puls) countY <= 0;`
61			`else if (hsync_high_puls) countY <= countY +1;`
62			`end`
63			`reg [15:0] line_no;`
64			`always @(negedge reset_n or posedge pixel_clk) begin`
65			`if (!reset_n) line_no <= 0;`
66			`else if (vsync_high_puls) line_no <= countY;`
67			`end`
68			`always @(negedge reset_n or posedge pixel_clk) begin`
69			`if (!reset_n) countX <= 0;`
70			`else if (hsync_high_puls) countX <= 0;`
71			`else countX <= countX +1;`
72			`end`
73			`reg [15:0] pixel_no;`
74			`always @(negedge reset_n or posedge pixel_clk) begin`
75			`if (!reset_n) pixel_no <= 0;`
76			`else if (hsync_high_puls) pixel_no <= countX;`
77			`end`
78
79
80			`endmodule`

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[/] [axi_vga/] [trunk/] [model/] [vga_test.v] - Blame information for rev 3