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[/] [axi_vga/] [trunk/] [rtl/] [vga_out.v] - Blame information for rev 4

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/****************************8**********
Date: 20191111
Designer: HugoLiu
AXI to VGA frame buffer xr8g8b8 To use the DRAM
To use AUO LCD A070vW05V2 and Xilinx Zynq7020
(c) HugoLiu 2019
*****************************8**********/
`define Hsync_len   1055  //799
`define Hsync_low   840   //656
`define Hsync_high  968   //752
`define Hsync_act   799   //639
 
`define Vsync_len   504   //524
`define Vsync_low   480   //490
`define Vsync_high  483   //492
`define Vsync_act   479   //399
 
`define Hsync_act_d 800 //640
`define Vsync_act_d 480 //400
 
module vga_out(
        S_AXI_ARESETN, S_AXI_ACLK,
 //write address signal        
        M_AXI_AWADDR,  //care
        M_AXI_AWVALID, //care
        M_AXI_AWREADY, //care
        M_AXI_AWID,    //care
        M_AXI_AWBURST,
        M_AXI_AWCACHE,
        M_AXI_AWLEN,
        M_AXI_AWLOCK,
        M_AXI_AWPROT,
        M_AXI_AWQOS,
        M_AXI_AWSIZE,
//write data        
        M_AXI_WDATA,
        M_AXI_WSTRB,
        M_AXI_WVALID,
        M_AXI_WREADY,
        M_AXI_WID,
        M_AXI_WLAST,
//write response
        M_AXI_BID,
        M_AXI_BREADY,
        M_AXI_BRESP,
        M_AXI_BVALID,
//read address signal        
        M_AXI_ARADDR,
        M_AXI_ARVALID,
        M_AXI_ARREADY,
        M_AXI_ARID,
        M_AXI_ARBURST,
        M_AXI_ARCACHE,
        M_AXI_ARLEN,
        M_AXI_ARLOCK,
        M_AXI_ARPROT,
        M_AXI_ARQOS,
        M_AXI_ARSIZE,
//read data
        M_AXI_RDATA,
        M_AXI_RID,
        M_AXI_RLAST,
        M_AXI_RREADY,
        M_AXI_RRESP,
        M_AXI_RVALID,
//setting 
/*
        video_first_addr   ,
        vga_en         ,
        Total_Burst_Per_Frame,
        */
        r8       ,
        g8       ,
        b8       ,
        hsync    ,
        vsync    ,
        de       ,
        pixel_clk
 
);
   //TFT interface
//  input [31:0]  video_first_addr;
//  input         vga_en;
//  input [23:0]  Total_Burst_Per_Frame;
  output [7:0]  r8, g8, b8;
  output        hsync, vsync, de;
  input         pixel_clk;
 
  ///////////////////////////////////////////////
 
  input   S_AXI_ARESETN, S_AXI_ACLK;
  //waddr
  output [31:0]                      M_AXI_AWADDR;
  output [1:0]                       M_AXI_AWBURST;
  output [3:0]                       M_AXI_AWCACHE;
  output [5:0]                       M_AXI_AWID;
  output [3:0]                       M_AXI_AWLEN;
  output [1:0]                       M_AXI_AWLOCK;
  output [2:0]                       M_AXI_AWPROT;
  output [3:0]                       M_AXI_AWQOS;
  input                              M_AXI_AWREADY;
  output [2:0]                       M_AXI_AWSIZE;
  output                             M_AXI_AWVALID;
  //wdata
  output [63:0]                      M_AXI_WDATA;
  output [5:0]                       M_AXI_WID;
  output                             M_AXI_WLAST;
  input                              M_AXI_WREADY;
  output [7:0]                       M_AXI_WSTRB;
  output                             M_AXI_WVALID;
  //w response
  input [5:0]                        M_AXI_BID;
  output                             M_AXI_BREADY;
  input [1:0]                        M_AXI_BRESP;
  input                              M_AXI_BVALID;
  //read addr
  output [31:0]                      M_AXI_ARADDR;
  output [1:0]                       M_AXI_ARBURST;
  output [3:0]                       M_AXI_ARCACHE;
  output [5:0]                       M_AXI_ARID;
  output [3:0]                       M_AXI_ARLEN;
  output [1:0]                       M_AXI_ARLOCK;
  output [2:0]                       M_AXI_ARPROT;
  output [3:0]                       M_AXI_ARQOS;
  input                              M_AXI_ARREADY;
  output [2:0]                       M_AXI_ARSIZE;
  output                             M_AXI_ARVALID;
  //read data    
  input [63:0]                       M_AXI_RDATA;
  input [5:0]                        M_AXI_RID;
  input                              M_AXI_RLAST;
  output                             M_AXI_RREADY;
  input [1:0]                        M_AXI_RRESP;
  input                              M_AXI_RVALID;
//
//
 
//////////////////////////////////////////////////////////////////////
 
//master 0
(*mark_debug = "true"*) reg [31:0]   M_AXI_ARADDR;
  reg [31:0]                         M_AXI_AWADDR;
//master0
//waddr
  reg    [5:0]                       M_AXI_AWID;
  reg                                M_AXI_AWVALID;
  wire                               M_AXI_AWREADY;
  wire   [1:0]                       M_AXI_AWBURST = 2'b01;
  wire   [3:0]                       M_AXI_AWCACHE = 4'b0;
  wire   [3:0]                       M_AXI_AWLEN   = 4'b1111;
  wire   [1:0]                       M_AXI_AWLOCK  = 2'b0;
  wire   [2:0]                       M_AXI_AWPROT  = 3'b1;
  wire   [3:0]                       M_AXI_AWQOS   = 4'b0;
  wire   [2:0]                       M_AXI_AWSIZE  = 3'b011;
  wire   [7:0]                       M_AXI_WSTRB   = 8'hff;
//read
(*mark_debug = "true"*)  wire        M_AXI_ARREADY;
  wire   [1:0]                       M_AXI_ARBURST = 2'b01;
  wire   [3:0]                       M_AXI_ARCACHE = 4'b0;
  wire   [3:0]                       M_AXI_ARLEN   = 4'b1111;
  wire   [1:0]                       M_AXI_ARLOCK  = 2'b0;
  wire   [2:0]                       M_AXI_ARPROT  = 3'b1;
  wire   [3:0]                       M_AXI_ARQOS   = 4'b0;
  wire   [2:0]                       M_AXI_ARSIZE  = 3'b011;
//
(*mark_debug = "true"*) reg          M_AXI_RREADY;
(*mark_debug = "true"*) wire [63:0]  M_AXI_RDATA;
(*mark_debug = "true"*) reg          M_AXI_ARVALID;
(*mark_debug = "true"*) wire         M_AXI_RLAST;
(*mark_debug = "true"*) wire         M_AXI_RVALID;
  wire [5:0]                         M_AXI_RID;
  wire [1:0]                         M_AXI_RRESP;
 
 
  //fifo write data count
//
//
reg M_AXI_BREADY;
(*mark_debug = "true"*) wire [31:0] video_first_addr = 32'h30000000;
//  input [31:0]  video_first_addr;
//  input         vga_en;
//  input [23:0]  Total_Burst_Per_Frame;
wire vga_en = 1;
wire [23:0] axi_master_read_len = 24'h2EE0; //Total_Burst_Per_Frame;
wire read_addr_over;
(*mark_debug = "true"*)reg [23:0] burst_r_count;
 
wire frame_axi_addr_over = (burst_r_count == (axi_master_read_len -1));
reg    axi_master_go_read_d;
reg vga_en_d;
reg vsync, hsync;
reg vsync_syncd1, vsync_syncd2;
 
always @(posedge S_AXI_ACLK) vsync_syncd1 <= vsync;
always @(posedge S_AXI_ACLK) vsync_syncd2 <= vsync_syncd1;
(* keep = "true" *)wire vsync_axi = vsync_syncd1 & vsync_syncd2;
reg vsync_axi_d;
always @(posedge S_AXI_ACLK) vsync_axi_d <= vsync_axi;
(*mark_debug = "true"*)wire raddr_puls = vsync_axi & !vsync_axi_d;
(*mark_debug = "true"*)reg axi_master_active_read;
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin
    if (!S_AXI_ARESETN)     axi_master_active_read <= 0;
    else if (!vsync_axi)    axi_master_active_read <= vga_en;
end
 
assign read_addr_over = (M_AXI_ARVALID & M_AXI_ARREADY);
 
//////////////////////////////////////////////////////////
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK )  begin
    if (!S_AXI_ARESETN)                               M_AXI_ARADDR <= 32'h3000_0000;
    else if (!vsync_axi)                              M_AXI_ARADDR <= video_first_addr;
    else if (read_addr_over)                          M_AXI_ARADDR <= M_AXI_ARADDR + 32'h80;
end
//////////////////////////////////////////////////////////////////////////////////////////////////
(*mark_debug = "true"*) reg full_0, full_1;
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK )  begin
    if (!S_AXI_ARESETN)                                burst_r_count <= 0;
    else if (!axi_master_active_read)                  burst_r_count <= 0;
    else if (frame_axi_addr_over & read_addr_over)     burst_r_count <= 0;
    else if (read_addr_over)                           burst_r_count <= burst_r_count + 1;
end
 
reg video_read_ready;
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK )  begin
    if (!S_AXI_ARESETN)                                 video_read_ready <= 1'b0;
    else if (frame_axi_addr_over & read_addr_over)      video_read_ready <= 1'b0;
    else if (M_AXI_ARVALID)                             video_read_ready <= 1'b0;
    else if (raddr_puls)                                video_read_ready <= 1'b1;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK )  begin
    if (!S_AXI_ARESETN)                                M_AXI_ARVALID <= 1'b0;
    else if (!axi_master_active_read)                  M_AXI_ARVALID <= 1'b0;
    else if (frame_axi_addr_over & read_addr_over)     M_AXI_ARVALID <= 1'b0;
    else if (video_read_ready)                         M_AXI_ARVALID <= 1'b1;
end
reg [5:0] M_AXI_ARID;
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK )  begin
    if (!S_AXI_ARESETN)                                M_AXI_ARID <= 6'h1;
    else if (!axi_master_active_read | raddr_puls)     M_AXI_ARID <= 6'h1;
    else if (read_addr_over)                           M_AXI_ARID <= M_AXI_ARID + 1;
end
 
  //read data    
 
(*mark_debug = "true"*) reg [23:0] burst_r_count_data;
 reg [8:0] r_len;
wire rdata_vaild = (M_AXI_RREADY & M_AXI_RVALID);
wire R_last = rdata_vaild & M_AXI_RLAST;
(* keep = "true" *) wire burst_read_finish = (burst_r_count_data == (axi_master_read_len - 1)) & R_last ;
//(* keep = "true" *) wire real_finish_read_finish = real_finish_data_count_over & R_last ;
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK )  begin
    if (!S_AXI_ARESETN)                        burst_r_count_data <= 0;
    else if (!axi_master_active_read)          burst_r_count_data <= 0;
    else if (raddr_puls)                       burst_r_count_data <= 0;
    else if (burst_read_finish)                burst_r_count_data <= 0;
    else if (R_last)                           burst_r_count_data <= burst_r_count_data + 1;
end
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK )  begin
    if (!S_AXI_ARESETN)                        r_len <= 0;
    else if (raddr_puls)                       r_len <= 0;
    else if (R_last)                           r_len <= 0;
    else if (rdata_vaild)                      r_len <= r_len + 1;
end
 
(*mark_debug = "true"*) reg axi_rdata_act;
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK )  begin
    if (!S_AXI_ARESETN)                        axi_rdata_act <= 0;
    else if (!axi_master_active_read)          axi_rdata_act <= 0;
    else if (burst_read_finish)                axi_rdata_act <= 0;
    else if (M_AXI_ARREADY & M_AXI_ARVALID)    axi_rdata_act <= 1;
end
 
 
wire [4:0] thrould;
wire full_0_high = (rdata_vaild & (r_len == 4'hf) & (thrould[4:0] == 5'hf));
wire full_1_high = (rdata_vaild & (r_len == 4'hf) & (thrould[4:0] == 5'h1f));
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK )  begin
    if (!S_AXI_ARESETN)                                   M_AXI_RREADY <= 1'b0;
    else if (!axi_master_active_read)                     M_AXI_RREADY <= 1'b0;
    else if (raddr_puls)                                  M_AXI_RREADY <= 1'b0;
    else if (full_0 & full_1)                             M_AXI_RREADY <= 1'b0;
    else if (full_0 & full_1_high)                        M_AXI_RREADY <= 1'b0;
    else if (full_1 & full_0_high)                        M_AXI_RREADY <= 1'b0;
    else if (burst_read_finish)                           M_AXI_RREADY <= 1'b0;
    else if (axi_rdata_act)                               M_AXI_RREADY <= 1'b1;
end
 
///////////////////////////////////////////////////////////////////////////
//  The VGA Controller
//////////////////////////////////////////////////////////////////////////
(*mark_debug = "true"*)reg [15:0] counX, counY;
reg vga_en_video, vga_en_video_syncd1, vga_en_video_syncd2;
 
always @(posedge pixel_clk) vga_en_video_syncd1 <= axi_master_active_read;
always @(posedge pixel_clk) vga_en_video_syncd2 <= vga_en_video_syncd1;
 
always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin
       if (!S_AXI_ARESETN) vga_en_video <= 1;
       else vga_en_video <= vga_en_video_syncd1 & vga_en_video_syncd2;
end
 
always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin
       if (!S_AXI_ARESETN)         counX <= `Hsync_high;
       else if (!vga_en_video)     counX <= `Hsync_high;
       else if (counX==`Hsync_len) counX <=0;
       else counX <= counX+1;
end
always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin
      if (!S_AXI_ARESETN) counY <= `Vsync_low;
      else if(counX==`Hsync_len) begin
          if (counY==`Vsync_len) counY <= 0;
          else counY <= counY + 1'b1;
      end
end
reg vsync_pre, hsync_pre;
 
always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin
      if (!S_AXI_ARESETN)   hsync_pre <=0;
      else hsync_pre <= (counX>=`Hsync_low) && (counX<`Hsync_high);
end
always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin
      if (!S_AXI_ARESETN) vsync_pre <=0;
      else vsync_pre <= (counY>=`Vsync_low) && (counY<`Vsync_high);
end
reg [9:0] gadd;
 
always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin
      if (!S_AXI_ARESETN) gadd <= 0;
      else if (vsync_pre)  gadd <= 0;
      else if  ((counY < `Vsync_act_d) && (counX < `Hsync_act_d)) gadd <= gadd + 1;
      //counX[10:1]+{counY[10:1],8'b0}+{counY[10:1],7'b0}+{counY[10:1],4'b0}; //800/2=400=190H
end
// dac
wire [31:0] vga_data;
reg  [7:0] r8, g8, b8;
always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin
      if (!S_AXI_ARESETN)                                r8 <= 0;
      else if ((counX>`Hsync_act) | (counY>`Vsync_act))  r8 <= 0;
      else                                                                                                                                               r8 <= vga_data[23:16];
end
always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin
      if (!S_AXI_ARESETN)                                g8 <= 0;
      else if ((counX>`Hsync_act) | (counY>`Vsync_act))  g8 <= 0;
      else                                                                                                                                               g8 <= vga_data[15:8];
end
always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin
      if (!S_AXI_ARESETN)                                b8 <= 0;
      else if ((counX>`Hsync_act) | (counY>`Vsync_act))  b8 <= 0;
      else                                                                                                                                               b8 <= vga_data[7:0];
end
 
/*
assign r8 = (counX>`Hsync_act) ? 0 : (counY>`Vsync_act) ? 0 :
                  vga_data[23:16];
 
assign g8 = (counX>`Hsync_act) ? 0 : (counY>`Vsync_act) ? 0 :
                  vga_data[15:8];
 
assign b8 = (counX>`Hsync_act) ? 0 : (counY>`Vsync_act) ? 0 :
            vga_data[ 7: 0];
  */
always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin
     if (!S_AXI_ARESETN)   hsync <= 0;
     else                 hsync <= ~hsync_pre;
end
always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin
     if (!S_AXI_ARESETN)   vsync <= 0;
     else if (hsync_pre)  vsync <= ~vsync_pre;
end
 
reg de_pre; // = !vt & (counX < `Hsync_act_d) & hz;
always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin
     if (~S_AXI_ARESETN)     de_pre <=0;
     else if ((counY < `Vsync_act_d) & (counX < `Hsync_act_d)) de_pre <= 1;
     else                   de_pre <= 0;
end
reg de;
always @(negedge pixel_clk) de <= de_pre;
 
 
assign thrould = burst_r_count_data[4:0];
reg full_0_low, full_1_low;
reg full_0_low_pre, full_1_low_pre;
reg full_0_sync_d1, full_1_sync_d1;
reg full_0_sync_d2, full_1_sync_d2;
always @(posedge pixel_clk) full_0_sync_d1 <= full_0;
always @(posedge pixel_clk) full_0_sync_d2 <= full_0_sync_d1;
always @(posedge pixel_clk) full_1_sync_d1 <= full_1;
always @(posedge pixel_clk) full_1_sync_d2 <= full_1_sync_d1;
 
always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin
    if (!S_AXI_ARESETN)                          full_0_low_pre <= 0;
    else if (!(full_0_sync_d1 | full_0_sync_d2)) full_0_low_pre <= 0;
    else if (gadd[9:0] == 10'h1ff)               full_0_low_pre <= 1;
end
always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin
    if (!S_AXI_ARESETN)                          full_1_low_pre <= 0;
    else if (!(full_1_sync_d1 | full_1_sync_d2)) full_1_low_pre <= 0;
    else if (gadd[9:0] == 10'h3ff)               full_1_low_pre <= 1;
end
always @(posedge S_AXI_ACLK)  full_0_low <= full_0_low_pre;
always @(posedge S_AXI_ACLK)  full_1_low <= full_1_low_pre;
 
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
    if (!S_AXI_ARESETN)              full_0 <= 0;
    else if (raddr_puls)             full_0 <= 0;
    else if (full_0_high)            full_0 <= 1;
    else if (full_0_low)             full_0 <= 0;
end
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
    if (!S_AXI_ARESETN)              full_1 <= 0;
    else if (raddr_puls)             full_1 <= 0;
    else if (full_1_high)            full_1 <= 1;
    else if (full_1_low)             full_1 <= 0;
end
 
(* keep = "true" *)wire [8:0] vga_write_count =  {burst_r_count_data[4:0], r_len[3:0]};
reg [31:0] Rdata_tmp;
always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin
    if (!S_AXI_ARESETN)                     Rdata_tmp <= 0;
    else Rdata_tmp <= {M_AXI_RDATA[59:52], M_AXI_RDATA[43:36], M_AXI_RDATA[27:20], M_AXI_RDATA[11:4]};
end
 
//
//wire [63:0] Rdata = M_AXI_RDATA;
blk_mem_gen_vga U_VGAMem(
  .clka      (S_AXI_ACLK),
  .wea       (rdata_vaild),
  .addra     (vga_write_count), //{burst_r_count_data[4:0], r_len[3:0]}),
  .dina      (M_AXI_RDATA),
  .douta     (),
  .clkb      (pixel_clk),
  .web       (1'b0),
  .addrb     (gadd[9:0]),
  .dinb      (32'h0),
  .doutb     (vga_data)
);
 
 
endmodule

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[/] [axi_vga/] [trunk/] [rtl/] [vga_out.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	hugoliu
2			`/**************************8********`
3			`Date: 20191111`
4			`Designer: HugoLiu`
5			`AXI to VGA frame buffer xr8g8b8 To use the DRAM`
6			`To use AUO LCD A070vW05V2 and Xilinx Zynq7020`
7			`(c) HugoLiu 2019`
8			`***************************8********/`
9			`define Hsync_len 1055 //799
10			`define Hsync_low 840 //656
11			`define Hsync_high 968 //752
12			`define Hsync_act 799 //639
13
14			`define Vsync_len 504 //524
15			`define Vsync_low 480 //490
16			`define Vsync_high 483 //492
17			`define Vsync_act 479 //399
18
19			`define Hsync_act_d 800 //640
20			`define Vsync_act_d 480 //400
21
22			`module vga_out(`
23			`S_AXI_ARESETN, S_AXI_ACLK,`
24			`//write address signal`
25			`M_AXI_AWADDR, //care`
26			`M_AXI_AWVALID, //care`
27			`M_AXI_AWREADY, //care`
28			`M_AXI_AWID, //care`
29			`M_AXI_AWBURST,`
30			`M_AXI_AWCACHE,`
31			`M_AXI_AWLEN,`
32			`M_AXI_AWLOCK,`
33			`M_AXI_AWPROT,`
34			`M_AXI_AWQOS,`
35			`M_AXI_AWSIZE,`
36			`//write data`
37			`M_AXI_WDATA,`
38			`M_AXI_WSTRB,`
39			`M_AXI_WVALID,`
40			`M_AXI_WREADY,`
41			`M_AXI_WID,`
42			`M_AXI_WLAST,`
43			`//write response`
44			`M_AXI_BID,`
45			`M_AXI_BREADY,`
46			`M_AXI_BRESP,`
47			`M_AXI_BVALID,`
48			`//read address signal`
49			`M_AXI_ARADDR,`
50			`M_AXI_ARVALID,`
51			`M_AXI_ARREADY,`
52			`M_AXI_ARID,`
53			`M_AXI_ARBURST,`
54			`M_AXI_ARCACHE,`
55			`M_AXI_ARLEN,`
56			`M_AXI_ARLOCK,`
57			`M_AXI_ARPROT,`
58			`M_AXI_ARQOS,`
59			`M_AXI_ARSIZE,`
60			`//read data`
61			`M_AXI_RDATA,`
62			`M_AXI_RID,`
63			`M_AXI_RLAST,`
64			`M_AXI_RREADY,`
65			`M_AXI_RRESP,`
66			`M_AXI_RVALID,`
67			`//setting`
68			`/*`
69			`video_first_addr ,`
70			`vga_en ,`
71			`Total_Burst_Per_Frame,`
72			`*/`
73			`r8 ,`
74			`g8 ,`
75			`b8 ,`
76			`hsync ,`
77			`vsync ,`
78			`de ,`
79			`pixel_clk`
80
81			`);`
82			`//TFT interface`
83			`// input [31:0] video_first_addr;`
84			`// input vga_en;`
85			`// input [23:0] Total_Burst_Per_Frame;`
86			`output [7:0] r8, g8, b8;`
87			`output hsync, vsync, de;`
88			`input pixel_clk;`
89
90			`///////////////////////////////////////////////`
91
92			`input S_AXI_ARESETN, S_AXI_ACLK;`
93			`//waddr`
94			`output [31:0] M_AXI_AWADDR;`
95			`output [1:0] M_AXI_AWBURST;`
96			`output [3:0] M_AXI_AWCACHE;`
97			`output [5:0] M_AXI_AWID;`
98			`output [3:0] M_AXI_AWLEN;`
99			`output [1:0] M_AXI_AWLOCK;`
100			`output [2:0] M_AXI_AWPROT;`
101			`output [3:0] M_AXI_AWQOS;`
102			`input M_AXI_AWREADY;`
103			`output [2:0] M_AXI_AWSIZE;`
104			`output M_AXI_AWVALID;`
105			`//wdata`
106			`output [63:0] M_AXI_WDATA;`
107			`output [5:0] M_AXI_WID;`
108			`output M_AXI_WLAST;`
109			`input M_AXI_WREADY;`
110			`output [7:0] M_AXI_WSTRB;`
111			`output M_AXI_WVALID;`
112			`//w response`
113			`input [5:0] M_AXI_BID;`
114			`output M_AXI_BREADY;`
115			`input [1:0] M_AXI_BRESP;`
116			`input M_AXI_BVALID;`
117			`//read addr`
118			`output [31:0] M_AXI_ARADDR;`
119			`output [1:0] M_AXI_ARBURST;`
120			`output [3:0] M_AXI_ARCACHE;`
121			`output [5:0] M_AXI_ARID;`
122			`output [3:0] M_AXI_ARLEN;`
123			`output [1:0] M_AXI_ARLOCK;`
124			`output [2:0] M_AXI_ARPROT;`
125			`output [3:0] M_AXI_ARQOS;`
126			`input M_AXI_ARREADY;`
127			`output [2:0] M_AXI_ARSIZE;`
128			`output M_AXI_ARVALID;`
129			`//read data`
130			`input [63:0] M_AXI_RDATA;`
131			`input [5:0] M_AXI_RID;`
132			`input M_AXI_RLAST;`
133			`output M_AXI_RREADY;`
134			`input [1:0] M_AXI_RRESP;`
135			`input M_AXI_RVALID;`
136			`//`
137			`//`
138
139			`//////////////////////////////////////////////////////////////////////`
140
141			`//master 0`
142			`(mark_debug = "true") reg [31:0] M_AXI_ARADDR;`
143			`reg [31:0] M_AXI_AWADDR;`
144			`//master0`
145			`//waddr`
146			`reg [5:0] M_AXI_AWID;`
147			`reg M_AXI_AWVALID;`
148			`wire M_AXI_AWREADY;`
149			`wire [1:0] M_AXI_AWBURST = 2'b01;`
150			`wire [3:0] M_AXI_AWCACHE = 4'b0;`
151			`wire [3:0] M_AXI_AWLEN = 4'b1111;`
152			`wire [1:0] M_AXI_AWLOCK = 2'b0;`
153			`wire [2:0] M_AXI_AWPROT = 3'b1;`
154			`wire [3:0] M_AXI_AWQOS = 4'b0;`
155			`wire [2:0] M_AXI_AWSIZE = 3'b011;`
156			`wire [7:0] M_AXI_WSTRB = 8'hff;`
157			`//read`
158			`(mark_debug = "true") wire M_AXI_ARREADY;`
159			`wire [1:0] M_AXI_ARBURST = 2'b01;`
160			`wire [3:0] M_AXI_ARCACHE = 4'b0;`
161			`wire [3:0] M_AXI_ARLEN = 4'b1111;`
162			`wire [1:0] M_AXI_ARLOCK = 2'b0;`
163			`wire [2:0] M_AXI_ARPROT = 3'b1;`
164			`wire [3:0] M_AXI_ARQOS = 4'b0;`
165			`wire [2:0] M_AXI_ARSIZE = 3'b011;`
166			`//`
167			`(mark_debug = "true") reg M_AXI_RREADY;`
168			`(mark_debug = "true") wire [63:0] M_AXI_RDATA;`
169			`(mark_debug = "true") reg M_AXI_ARVALID;`
170			`(mark_debug = "true") wire M_AXI_RLAST;`
171			`(mark_debug = "true") wire M_AXI_RVALID;`
172			`wire [5:0] M_AXI_RID;`
173			`wire [1:0] M_AXI_RRESP;`
174
175
176			`//fifo write data count`
177			`//`
178			`//`
179			`reg M_AXI_BREADY;`
180			`(mark_debug = "true") wire [31:0] video_first_addr = 32'h30000000;`
181			`// input [31:0] video_first_addr;`
182			`// input vga_en;`
183			`// input [23:0] Total_Burst_Per_Frame;`
184			`wire vga_en = 1;`
185			`wire [23:0] axi_master_read_len = 24'h2EE0; //Total_Burst_Per_Frame;`
186			`wire read_addr_over;`
187			`(mark_debug = "true")reg [23:0] burst_r_count;`
188
189			`wire frame_axi_addr_over = (burst_r_count == (axi_master_read_len -1));`
190			`reg axi_master_go_read_d;`
191			`reg vga_en_d;`
192			`reg vsync, hsync;`
193			`reg vsync_syncd1, vsync_syncd2;`
194
195			`always @(posedge S_AXI_ACLK) vsync_syncd1 <= vsync;`
196			`always @(posedge S_AXI_ACLK) vsync_syncd2 <= vsync_syncd1;`
197			`(* keep = "true" *)wire vsync_axi = vsync_syncd1 & vsync_syncd2;`
198			`reg vsync_axi_d;`
199			`always @(posedge S_AXI_ACLK) vsync_axi_d <= vsync_axi;`
200			`(mark_debug = "true")wire raddr_puls = vsync_axi & !vsync_axi_d;`
201			`(mark_debug = "true")reg axi_master_active_read;`
202			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
203			`if (!S_AXI_ARESETN) axi_master_active_read <= 0;`
204			`else if (!vsync_axi) axi_master_active_read <= vga_en;`
205			`end`
206
207			`assign read_addr_over = (M_AXI_ARVALID & M_AXI_ARREADY);`
208
209			`//////////////////////////////////////////////////////////`
210
211			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
212			`if (!S_AXI_ARESETN) M_AXI_ARADDR <= 32'h3000_0000;`
213			`else if (!vsync_axi) M_AXI_ARADDR <= video_first_addr;`
214			`else if (read_addr_over) M_AXI_ARADDR <= M_AXI_ARADDR + 32'h80;`
215			`end`
216			`//////////////////////////////////////////////////////////////////////////////////////////////////`
217			`(mark_debug = "true") reg full_0, full_1;`
218
219			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
220			`if (!S_AXI_ARESETN) burst_r_count <= 0;`
221			`else if (!axi_master_active_read) burst_r_count <= 0;`
222			`else if (frame_axi_addr_over & read_addr_over) burst_r_count <= 0;`
223			`else if (read_addr_over) burst_r_count <= burst_r_count + 1;`
224			`end`
225
226			`reg video_read_ready;`
227			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
228			`if (!S_AXI_ARESETN) video_read_ready <= 1'b0;`
229			`else if (frame_axi_addr_over & read_addr_over) video_read_ready <= 1'b0;`
230			`else if (M_AXI_ARVALID) video_read_ready <= 1'b0;`
231			`else if (raddr_puls) video_read_ready <= 1'b1;`
232			`end`
233			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
234			`if (!S_AXI_ARESETN) M_AXI_ARVALID <= 1'b0;`
235			`else if (!axi_master_active_read) M_AXI_ARVALID <= 1'b0;`
236			`else if (frame_axi_addr_over & read_addr_over) M_AXI_ARVALID <= 1'b0;`
237			`else if (video_read_ready) M_AXI_ARVALID <= 1'b1;`
238			`end`
239			`reg [5:0] M_AXI_ARID;`
240			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
241			`if (!S_AXI_ARESETN) M_AXI_ARID <= 6'h1;`
242			`else if (!axi_master_active_read \| raddr_puls) M_AXI_ARID <= 6'h1;`
243			`else if (read_addr_over) M_AXI_ARID <= M_AXI_ARID + 1;`
244			`end`
245
246			`//read data`
247
248			`(mark_debug = "true") reg [23:0] burst_r_count_data;`
249			`reg [8:0] r_len;`
250			`wire rdata_vaild = (M_AXI_RREADY & M_AXI_RVALID);`
251			`wire R_last = rdata_vaild & M_AXI_RLAST;`
252			`(* keep = "true" *) wire burst_read_finish = (burst_r_count_data == (axi_master_read_len - 1)) & R_last ;`
253			`//(* keep = "true" *) wire real_finish_read_finish = real_finish_data_count_over & R_last ;`
254
255			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
256			`if (!S_AXI_ARESETN) burst_r_count_data <= 0;`
257			`else if (!axi_master_active_read) burst_r_count_data <= 0;`
258			`else if (raddr_puls) burst_r_count_data <= 0;`
259			`else if (burst_read_finish) burst_r_count_data <= 0;`
260			`else if (R_last) burst_r_count_data <= burst_r_count_data + 1;`
261			`end`
262
263			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
264			`if (!S_AXI_ARESETN) r_len <= 0;`
265			`else if (raddr_puls) r_len <= 0;`
266			`else if (R_last) r_len <= 0;`
267			`else if (rdata_vaild) r_len <= r_len + 1;`
268			`end`
269
270			`(mark_debug = "true") reg axi_rdata_act;`
271			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
272			`if (!S_AXI_ARESETN) axi_rdata_act <= 0;`
273			`else if (!axi_master_active_read) axi_rdata_act <= 0;`
274			`else if (burst_read_finish) axi_rdata_act <= 0;`
275			`else if (M_AXI_ARREADY & M_AXI_ARVALID) axi_rdata_act <= 1;`
276			`end`
277
278
279			`wire [4:0] thrould;`
280			`wire full_0_high = (rdata_vaild & (r_len == 4'hf) & (thrould[4:0] == 5'hf));`
281			`wire full_1_high = (rdata_vaild & (r_len == 4'hf) & (thrould[4:0] == 5'h1f));`
282
283			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK ) begin`
284			`if (!S_AXI_ARESETN) M_AXI_RREADY <= 1'b0;`
285			`else if (!axi_master_active_read) M_AXI_RREADY <= 1'b0;`
286			`else if (raddr_puls) M_AXI_RREADY <= 1'b0;`
287			`else if (full_0 & full_1) M_AXI_RREADY <= 1'b0;`
288			`else if (full_0 & full_1_high) M_AXI_RREADY <= 1'b0;`
289			`else if (full_1 & full_0_high) M_AXI_RREADY <= 1'b0;`
290			`else if (burst_read_finish) M_AXI_RREADY <= 1'b0;`
291			`else if (axi_rdata_act) M_AXI_RREADY <= 1'b1;`
292			`end`
293
294			`///////////////////////////////////////////////////////////////////////////`
295			`// The VGA Controller`
296			`//////////////////////////////////////////////////////////////////////////`
297			`(mark_debug = "true")reg [15:0] counX, counY;`
298			`reg vga_en_video, vga_en_video_syncd1, vga_en_video_syncd2;`
299
300			`always @(posedge pixel_clk) vga_en_video_syncd1 <= axi_master_active_read;`
301			`always @(posedge pixel_clk) vga_en_video_syncd2 <= vga_en_video_syncd1;`
302
303			`always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin`
304			`if (!S_AXI_ARESETN) vga_en_video <= 1;`
305			`else vga_en_video <= vga_en_video_syncd1 & vga_en_video_syncd2;`
306			`end`
307
308			`always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin`
309			if (!S_AXI_ARESETN) counX <= `Hsync_high;
310			else if (!vga_en_video) counX <= `Hsync_high;
311			else if (counX==`Hsync_len) counX <=0;
312			`else counX <= counX+1;`
313			`end`
314			`always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin`
315			if (!S_AXI_ARESETN) counY <= `Vsync_low;
316			else if(counX==`Hsync_len) begin
317			if (counY==`Vsync_len) counY <= 0;
318			`else counY <= counY + 1'b1;`
319			`end`
320			`end`
321			`reg vsync_pre, hsync_pre;`
322
323			`always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin`
324			`if (!S_AXI_ARESETN) hsync_pre <=0;`
325			else hsync_pre <= (counX>=`Hsync_low) && (counX<`Hsync_high);
326			`end`
327			`always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin`
328			`if (!S_AXI_ARESETN) vsync_pre <=0;`
329			else vsync_pre <= (counY>=`Vsync_low) && (counY<`Vsync_high);
330			`end`
331			`reg [9:0] gadd;`
332
333			`always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin`
334			`if (!S_AXI_ARESETN) gadd <= 0;`
335			`else if (vsync_pre) gadd <= 0;`
336			else if ((counY < `Vsync_act_d) && (counX < `Hsync_act_d)) gadd <= gadd + 1;
337			`//counX[10:1]+{counY[10:1],8'b0}+{counY[10:1],7'b0}+{counY[10:1],4'b0}; //800/2=400=190H`
338			`end`
339			`// dac`
340			`wire [31:0] vga_data;`
341			`reg [7:0] r8, g8, b8;`
342			`always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin`
343			`if (!S_AXI_ARESETN) r8 <= 0;`
344			else if ((counX>`Hsync_act) \| (counY>`Vsync_act)) r8 <= 0;
345			`else r8 <= vga_data[23:16];`
346			`end`
347			`always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin`
348			`if (!S_AXI_ARESETN) g8 <= 0;`
349			else if ((counX>`Hsync_act) \| (counY>`Vsync_act)) g8 <= 0;
350			`else g8 <= vga_data[15:8];`
351			`end`
352			`always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin`
353			`if (!S_AXI_ARESETN) b8 <= 0;`
354			else if ((counX>`Hsync_act) \| (counY>`Vsync_act)) b8 <= 0;
355			`else b8 <= vga_data[7:0];`
356			`end`
357
358			`/*`
359			assign r8 = (counX>`Hsync_act) ? 0 : (counY>`Vsync_act) ? 0 :
360			`vga_data[23:16];`
361
362			assign g8 = (counX>`Hsync_act) ? 0 : (counY>`Vsync_act) ? 0 :
363			`vga_data[15:8];`
364
365			assign b8 = (counX>`Hsync_act) ? 0 : (counY>`Vsync_act) ? 0 :
366			`vga_data[ 7: 0];`
367			`*/`
368			`always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin`
369			`if (!S_AXI_ARESETN) hsync <= 0;`
370			`else hsync <= ~hsync_pre;`
371			`end`
372			`always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin`
373			`if (!S_AXI_ARESETN) vsync <= 0;`
374			`else if (hsync_pre) vsync <= ~vsync_pre;`
375			`end`
376
377			reg de_pre; // = !vt & (counX < `Hsync_act_d) & hz;
378			`always @(negedge S_AXI_ARESETN or negedge pixel_clk) begin`
379			`if (~S_AXI_ARESETN) de_pre <=0;`
380			else if ((counY < `Vsync_act_d) & (counX < `Hsync_act_d)) de_pre <= 1;
381			`else de_pre <= 0;`
382			`end`
383			`reg de;`
384			`always @(negedge pixel_clk) de <= de_pre;`
385
386
387			`assign thrould = burst_r_count_data[4:0];`
388			`reg full_0_low, full_1_low;`
389			`reg full_0_low_pre, full_1_low_pre;`
390			`reg full_0_sync_d1, full_1_sync_d1;`
391			`reg full_0_sync_d2, full_1_sync_d2;`
392			`always @(posedge pixel_clk) full_0_sync_d1 <= full_0;`
393			`always @(posedge pixel_clk) full_0_sync_d2 <= full_0_sync_d1;`
394			`always @(posedge pixel_clk) full_1_sync_d1 <= full_1;`
395			`always @(posedge pixel_clk) full_1_sync_d2 <= full_1_sync_d1;`
396
397			`always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin`
398			`if (!S_AXI_ARESETN) full_0_low_pre <= 0;`
399			`else if (!(full_0_sync_d1 \| full_0_sync_d2)) full_0_low_pre <= 0;`
400			`else if (gadd[9:0] == 10'h1ff) full_0_low_pre <= 1;`
401			`end`
402			`always @(negedge S_AXI_ARESETN or posedge pixel_clk) begin`
403			`if (!S_AXI_ARESETN) full_1_low_pre <= 0;`
404			`else if (!(full_1_sync_d1 \| full_1_sync_d2)) full_1_low_pre <= 0;`
405			`else if (gadd[9:0] == 10'h3ff) full_1_low_pre <= 1;`
406			`end`
407			`always @(posedge S_AXI_ACLK) full_0_low <= full_0_low_pre;`
408			`always @(posedge S_AXI_ACLK) full_1_low <= full_1_low_pre;`
409
410			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin`
411			`if (!S_AXI_ARESETN) full_0 <= 0;`
412			`else if (raddr_puls) full_0 <= 0;`
413			`else if (full_0_high) full_0 <= 1;`
414			`else if (full_0_low) full_0 <= 0;`
415			`end`
416			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin`
417			`if (!S_AXI_ARESETN) full_1 <= 0;`
418			`else if (raddr_puls) full_1 <= 0;`
419			`else if (full_1_high) full_1 <= 1;`
420			`else if (full_1_low) full_1 <= 0;`
421			`end`
422
423			`(* keep = "true" *)wire [8:0] vga_write_count = {burst_r_count_data[4:0], r_len[3:0]};`
424			`reg [31:0] Rdata_tmp;`
425			`always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin`
426			`if (!S_AXI_ARESETN) Rdata_tmp <= 0;`
427			`else Rdata_tmp <= {M_AXI_RDATA[59:52], M_AXI_RDATA[43:36], M_AXI_RDATA[27:20], M_AXI_RDATA[11:4]};`
428			`end`
429
430			`//`
431			`//wire [63:0] Rdata = M_AXI_RDATA;`
432			`blk_mem_gen_vga U_VGAMem(`
433			`.clka (S_AXI_ACLK),`
434			`.wea (rdata_vaild),`
435			`.addra (vga_write_count), //{burst_r_count_data[4:0], r_len[3:0]}),`
436			`.dina (M_AXI_RDATA),`
437			`.douta (),`
438			`.clkb (pixel_clk),`
439			`.web (1'b0),`
440			`.addrb (gadd[9:0]),`
441			`.dinb (32'h0),`
442			`.doutb (vga_data)`
443			`);`
444
445
446			`endmodule`