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Subversion Repositories axi_vga

[/] [axi_vga/] [trunk/] [sim/] [modelsim.do] - Blame information for rev 2

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#vlib work
#vdel �Vlib work �Vall
vlib work
#vlog  $env(XILINX)/verilog/src/glbl.v
 
vlog +define+SIM_RTL -f files.list
vsim -t ps  work.testbench  -l vsim.log
 

Line No.	Rev	Author	Line
1	2	hugoliu	`#vlib work`
2			`#vdel �Vlib work �Vall`
3			`vlib work`
4			`#vlog $env(XILINX)/verilog/src/glbl.v`
5
6			`vlog +define+SIM_RTL -f files.list`
7			`vsim -t ps work.testbench -l vsim.log`
8

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Subversion Repositories axi_vga

[/] [axi_vga/] [trunk/] [sim/] [modelsim.do] - Blame information for rev 2