Subversion Repositories axi_vga

`timescale 1ns/10ps

/*

Author: HugoLiu

E-mail: liu_xinghou@yahoo.com.tw

*/

module testbench;

reg pixel_clk;

initial begin

    pixel_clk <= 0;

end

always #15 pixel_clk <= ~pixel_clk;

reg FCLK_CLK0, FCLK_RESET0_N;

initial begin

    FCLK_CLK0 <= 0;

    FCLK_RESET0_N = 1;

  #14  FCLK_RESET0_N = 0;

  #32 FCLK_RESET0_N = 1;

end

always #5 FCLK_CLK0 <= ~FCLK_CLK0;

  //HP0  

  wire [31:0]S_AXI_HP0_araddr;

  wire [1:0]S_AXI_HP0_arburst;

  wire [3:0]S_AXI_HP0_arcache;

  wire [5:0]S_AXI_HP0_arid;

  wire [3:0]S_AXI_HP0_arlen;

  wire [1:0]S_AXI_HP0_arlock;

  wire [2:0]S_AXI_HP0_arprot;

  wire [3:0]S_AXI_HP0_arqos;

  wire S_AXI_HP0_arready;

  wire [2:0]S_AXI_HP0_arsize;

  wire S_AXI_HP0_arvalid;

  wire [31:0]S_AXI_HP0_awaddr;

  wire [1:0]S_AXI_HP0_awburst;

  wire [3:0]S_AXI_HP0_awcache;

  wire [5:0]S_AXI_HP0_awid;

  wire [3:0]S_AXI_HP0_awlen;

  wire [1:0]S_AXI_HP0_awlock;

  wire [2:0]S_AXI_HP0_awprot;

  wire [3:0]S_AXI_HP0_awqos;

  wire S_AXI_HP0_awready;

  wire [2:0]S_AXI_HP0_awsize;

  wire S_AXI_HP0_awvalid;

  wire [5:0]S_AXI_HP0_bid;

  wire S_AXI_HP0_bready;

  wire [1:0]S_AXI_HP0_bresp;

  wire S_AXI_HP0_bvalid;

  wire [63:0]S_AXI_HP0_rdata;

  wire [5:0]S_AXI_HP0_rid;

  wire S_AXI_HP0_rlast;

  wire S_AXI_HP0_rready;

  wire [1:0]S_AXI_HP0_rresp;

  wire S_AXI_HP0_rvalid;

  wire [63:0]S_AXI_HP0_wdata;

  wire [5:0]S_AXI_HP0_wid;

  wire S_AXI_HP0_wlast;

  wire S_AXI_HP0_wready;

  wire [7:0]S_AXI_HP0_wstrb;

  wire S_AXI_HP0_wvalid;

  //HP1 Read

  wire [31:0]S_AXI_HP1_araddr;

  wire [1:0]S_AXI_HP1_arburst;

  wire [3:0]S_AXI_HP1_arcache;

  wire [5:0]S_AXI_HP1_arid;

  wire [3:0]S_AXI_HP1_arlen;

  wire [1:0]S_AXI_HP1_arlock;

  wire [2:0]S_AXI_HP1_arprot;

  wire [3:0]S_AXI_HP1_arqos;

  wire S_AXI_HP1_arready;

  wire [2:0]S_AXI_HP1_arsize;

  wire S_AXI_HP1_arvalid;

  wire [63:0]S_AXI_HP1_rdata;

  wire [5:0]S_AXI_HP1_rid;

  wire S_AXI_HP1_rlast;

  wire S_AXI_HP1_rready;

  wire [1:0]S_AXI_HP1_rresp;

  wire S_AXI_HP1_rvalid;

  //HP1 Write

  wire [31:0]S_AXI_HP1_awaddr;

  wire [1:0] S_AXI_HP1_awburst;

  wire [3:0] S_AXI_HP1_awcache;

  wire [5:0] S_AXI_HP1_awid;

  wire [3:0] S_AXI_HP1_awlen;

  wire [1:0] S_AXI_HP1_awlock;

  wire [2:0] S_AXI_HP1_awprot;

  wire [3:0] S_AXI_HP1_awqos;

  wire       S_AXI_HP1_awready;

  wire [2:0] S_AXI_HP1_awsize;

  wire       S_AXI_HP1_awvalid;

  wire [5:0] S_AXI_HP1_bid;

  wire       S_AXI_HP1_bready;

  wire [1:0] S_AXI_HP1_bresp;

  wire       S_AXI_HP1_bvalid;

  wire [63:0]S_AXI_HP1_wdata;

  wire [5:0] S_AXI_HP1_wid;

  wire       S_AXI_HP1_wlast;

  wire       S_AXI_HP1_wready;

  wire [7:0] S_AXI_HP1_wstrb;

  wire       S_AXI_HP1_wvalid;

  //HP1_1 Write

  wire [31:0]S_AXI_HP1_1_awaddr;

  wire [1:0] S_AXI_HP1_1_awburst;

  wire [3:0] S_AXI_HP1_1_awcache;

  wire [5:0] S_AXI_HP1_1_awid;

  wire [3:0] S_AXI_HP1_1_awlen;

  wire [1:0] S_AXI_HP1_1_awlock;

  wire [2:0] S_AXI_HP1_1_awprot;

  wire [3:0] S_AXI_HP1_1_awqos;

  wire       S_AXI_HP1_1_awready;

  wire [2:0] S_AXI_HP1_1_awsize;

  wire       S_AXI_HP1_1_awvalid;

  wire [5:0] S_AXI_HP1_1_bid;

  wire       S_AXI_HP1_1_bready;

  wire [1:0] S_AXI_HP1_1_bresp;

  wire       S_AXI_HP1_1_bvalid;

  wire [63:0]S_AXI_HP1_1_wdata;

  wire [5:0] S_AXI_HP1_1_wid;

  wire       S_AXI_HP1_1_wlast;

  wire       S_AXI_HP1_1_wready;

  wire [7:0] S_AXI_HP1_1_wstrb;

  wire       S_AXI_HP1_1_wvalid;

HP_slave u_HP(

    .S_AXI_ARESETN      (FCLK_RESET0_N),

    .S_AXI_ACLK         (FCLK_CLK0),

//Slave port    

        .S_AXI_HP_araddr (S_AXI_HP0_araddr),

        .S_AXI_HP_arburst(S_AXI_HP0_arburst),

        .S_AXI_HP_arcache(S_AXI_HP0_arcache),

        .S_AXI_HP_arid(S_AXI_HP0_arid),

        .S_AXI_HP_arlen(S_AXI_HP0_arlen),

        .S_AXI_HP_arlock(S_AXI_HP0_arlock),

        .S_AXI_HP_arprot(S_AXI_HP0_arprot),

        .S_AXI_HP_arqos(S_AXI_HP0_arqos),

        .S_AXI_HP_arready(S_AXI_HP0_arready),

        .S_AXI_HP_arsize(S_AXI_HP0_arsize),

        .S_AXI_HP_arvalid(S_AXI_HP0_arvalid),

        .S_AXI_HP_awaddr(S_AXI_HP0_awaddr),

        .S_AXI_HP_awburst(S_AXI_HP0_awburst),

        .S_AXI_HP_awcache(S_AXI_HP0_awcache),

        .S_AXI_HP_awid(S_AXI_HP0_awid),

        .S_AXI_HP_awlen(S_AXI_HP0_awlen),

        .S_AXI_HP_awlock(S_AXI_HP0_awlock),

        .S_AXI_HP_awprot(S_AXI_HP0_awprot),

        .S_AXI_HP_awqos(S_AXI_HP0_awqos),

        .S_AXI_HP_awready(S_AXI_HP0_awready),

        .S_AXI_HP_awsize(S_AXI_HP0_awsize),

        .S_AXI_HP_awvalid(S_AXI_HP0_awvalid),

        .S_AXI_HP_bid(S_AXI_HP0_bid),

        .S_AXI_HP_bready(S_AXI_HP0_bready),

        .S_AXI_HP_bresp(S_AXI_HP0_bresp),

        .S_AXI_HP_bvalid(S_AXI_HP0_bvalid),

        .S_AXI_HP_rdata(S_AXI_HP0_rdata),

        .S_AXI_HP_rid(S_AXI_HP0_rid),

        .S_AXI_HP_rlast(S_AXI_HP0_rlast),

        .S_AXI_HP_rready(S_AXI_HP0_rready),

        .S_AXI_HP_rresp(S_AXI_HP0_rresp),

        .S_AXI_HP_rvalid(S_AXI_HP0_rvalid),

        .S_AXI_HP_wdata(S_AXI_HP0_wdata),

        .S_AXI_HP_wid(S_AXI_HP0_wid),

        .S_AXI_HP_wlast(S_AXI_HP0_wlast),

        .S_AXI_HP_wready(S_AXI_HP0_wready),

        .S_AXI_HP_wstrb(S_AXI_HP0_wstrb),

        .S_AXI_HP_wvalid(S_AXI_HP0_wvalid),

        .S_AXI_HP1_araddr(S_AXI_HP1_araddr),

        .S_AXI_HP1_arburst(S_AXI_HP1_arburst),

        .S_AXI_HP1_arcache(S_AXI_HP1_arcache),

        .S_AXI_HP1_arid(S_AXI_HP1_arid),

        .S_AXI_HP1_arlen(S_AXI_HP1_arlen),

        .S_AXI_HP1_arlock(S_AXI_HP1_arlock),

        .S_AXI_HP1_arprot(S_AXI_HP1_arprot),

        .S_AXI_HP1_arqos(S_AXI_HP1_arqos),

        .S_AXI_HP1_arready(S_AXI_HP1_arready),

        .S_AXI_HP1_arsize(S_AXI_HP1_arsize),

        .S_AXI_HP1_arvalid(S_AXI_HP1_arvalid),

        .S_AXI_HP1_awaddr(S_AXI_HP1_awaddr),

        .S_AXI_HP1_awburst(S_AXI_HP1_awburst),

        .S_AXI_HP1_awcache(S_AXI_HP1_awcache),

        .S_AXI_HP1_awid(S_AXI_HP1_awid),

        .S_AXI_HP1_awlen(S_AXI_HP1_awlen),

        .S_AXI_HP1_awlock(S_AXI_HP1_awlock),

        .S_AXI_HP1_awprot(S_AXI_HP1_awprot),

        .S_AXI_HP1_awqos(S_AXI_HP1_awqos),

        .S_AXI_HP1_awready(S_AXI_HP1_awready),

        .S_AXI_HP1_awsize(S_AXI_HP1_awsize),

        .S_AXI_HP1_awvalid(S_AXI_HP1_awvalid),

        .S_AXI_HP1_bid(S_AXI_HP1_bid),

        .S_AXI_HP1_bready(S_AXI_HP1_bready),

        .S_AXI_HP1_bresp(S_AXI_HP1_bresp),

        .S_AXI_HP1_bvalid(S_AXI_HP1_bvalid),

        .S_AXI_HP1_rdata(S_AXI_HP1_rdata),

        .S_AXI_HP1_rid(S_AXI_HP1_rid),

        .S_AXI_HP1_rlast(S_AXI_HP1_rlast),

        .S_AXI_HP1_rready(S_AXI_HP1_rready),

        .S_AXI_HP1_rresp(S_AXI_HP1_rresp),

        .S_AXI_HP1_rvalid(S_AXI_HP1_rvalid),

        .S_AXI_HP1_wdata(S_AXI_HP1_wdata),

        .S_AXI_HP1_wid(S_AXI_HP1_wid),

        .S_AXI_HP1_wlast(S_AXI_HP1_wlast),

        .S_AXI_HP1_wready(S_AXI_HP1_wready),

        .S_AXI_HP1_wstrb(S_AXI_HP1_wstrb),

        .S_AXI_HP1_wvalid(S_AXI_HP1_wvalid)

                 );

wire [7:0] r8,g8,b8;

       vga_out U_axi_vga(

             .S_AXI_ACLK         (FCLK_CLK0),

             .S_AXI_ARESETN      (FCLK_RESET0_N),

     //master

     //write

             .M_AXI_AWADDR     (S_AXI_HP1_awaddr),

             .M_AXI_AWBURST    (S_AXI_HP1_awburst),

             .M_AXI_AWCACHE    (S_AXI_HP1_awcache),

             .M_AXI_AWID       (S_AXI_HP1_awid),

             .M_AXI_AWLEN      (S_AXI_HP1_awlen),

             .M_AXI_AWLOCK     (S_AXI_HP1_awlock),

             .M_AXI_AWPROT     (S_AXI_HP1_awprot),

             .M_AXI_AWQOS      (S_AXI_HP1_awqos),

             .M_AXI_AWREADY    (S_AXI_HP1_awready),

             .M_AXI_AWSIZE     (S_AXI_HP1_awsize),

             .M_AXI_AWVALID    (S_AXI_HP1_awvalid),

             .M_AXI_WDATA      (S_AXI_HP1_wdata),

             .M_AXI_WID        (S_AXI_HP1_wid),

             .M_AXI_WLAST      (S_AXI_HP1_wlast),

             .M_AXI_WREADY     (S_AXI_HP1_wready),

             .M_AXI_WSTRB      (S_AXI_HP1_wstrb),

             .M_AXI_WVALID     (S_AXI_HP1_wvalid),

             .M_AXI_BID        (S_AXI_HP1_bid),

             .M_AXI_BREADY     (S_AXI_HP1_bready),

             .M_AXI_BRESP      (S_AXI_HP1_bresp),

             .M_AXI_BVALID     (S_AXI_HP1_bvalid),

      //read                                  1

             .M_AXI_ARADDR     (S_AXI_HP1_araddr),

             .M_AXI_ARBURST    (S_AXI_HP1_arburst),

             .M_AXI_ARCACHE    (S_AXI_HP1_arcache),

             .M_AXI_ARID       (S_AXI_HP1_arid),

             .M_AXI_ARLEN      (S_AXI_HP1_arlen),

             .M_AXI_ARLOCK     (S_AXI_HP1_arlock),

             .M_AXI_ARPROT     (S_AXI_HP1_arprot),

             .M_AXI_ARQOS      (S_AXI_HP1_arqos),

             .M_AXI_ARREADY    (S_AXI_HP1_arready),

             .M_AXI_ARSIZE     (S_AXI_HP1_arsize),

             .M_AXI_ARVALID    (S_AXI_HP1_arvalid),

             .M_AXI_RDATA      (S_AXI_HP1_rdata),

             .M_AXI_RID        (S_AXI_HP1_rid),

             .M_AXI_RLAST      (S_AXI_HP1_rlast),

             .M_AXI_RREADY     (S_AXI_HP1_rready),

             .M_AXI_RRESP      (S_AXI_HP1_rresp),

             .M_AXI_RVALID     (S_AXI_HP1_rvalid),

             .r8     (r8),

             .g8     (g8),

             .b8     (b8),

             .hsync  (hsync),

             .vsync  (vsync),

             .de     (de),

             .pixel_clk  (pixel_clk)

             );

 //debug

 reg [3:0] vcount;

 reg vhsync_d;

 always @(posedge FCLK_CLK0) vhsync_d <= vsync;

 always @(negedge FCLK_RESET0_N or posedge pixel_clk) begin

       if (!FCLK_RESET0_N) vcount <= 0;

       else if (vsync & !vhsync_d) vcount <= vcount +1;

 end

////////////////////////////////////////////////////////////////////////

// model

////////////////////////////////////////////

vga_test U_vga_test(

         .reset_n         (FCLK_RESET0_N),

         .pixel_clk       (pixel_clk),

         .hsync           (hsync),

         .vsync                                         (vsync),

         .de                                                    (de),

         .r8              (r8),

         .g8              (g8),

         .b8              (b8)

   );

endmodule