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amulcock |
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---- ----
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---- ----
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---- This file is part of the big_counter project ----
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---- http://www.opencores.org/cores/big_counter ----
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---- ----
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---- Description ----
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---- Implementation of a large counter made of SRL's ----
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---- ----
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---- ----
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---- To Do: ----
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---- NA ----
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---- ----
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---- Author(s): ----
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---- Andrew Mulcock, amulcock@opencores.org ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2007 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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-- ----
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-- CVS Revision History ----
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-- ----
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-- $Log: not supported by cvs2svn $ ----
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-- ----
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library ieee;
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use ieee.std_logic_1164.all;
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entity am_srl_counter_rtl is
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generic (
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no_of_stages : integer := 200
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);
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port( clk : in std_logic;
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en_in : in std_logic;
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rco : out std_logic_vector ( no_of_stages - 1 downto 0)
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);
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end am_srl_counter_rtl;
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architecture Behavioral of am_srl_counter_rtl is
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type shift_counter_type is array ( no_of_stages - 1 downto 0 ) of STD_LOGIC_VECTOR ( 15 downto 0 ) ;
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signal shift_srl : shift_counter_type := ( others => X"0001" );
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signal clk_en : std_logic_vector ( no_of_stages - 1 downto 0) := ( others => '0');
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signal rco_int : std_logic_vector ( no_of_stages - 1 downto 0) := ( others => '0');
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begin
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gen_srls : for n in 0 to no_of_stages - 1 generate
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tap_a: if n = 0 generate
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clk_en(n) <= en_in;
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srl_proc_a :process (clk)
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begin
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if rising_edge( clk ) then
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if clk_en(n) = '1' then
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shift_srl(n) <= shift_srl(n)(shift_srl(n)'left-1 downto 0) & shift_srl(n)(shift_srl(n)'left);
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end if;
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end if;
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end process srl_proc_a;
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rco_int(n) <= shift_srl(n)(shift_srl(n)'left);
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end generate tap_a;
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tap_b: if n = 1 generate
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clk_en(n) <= rco_int(n-1) and en_in;
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srl_proc_b :process (clk)
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begin
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if rising_edge( clk) then
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if clk_en(n) = '1' then
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shift_srl(n) <= shift_srl(n)(shift_srl(n)'left-1 downto 0) & shift_srl(n)(shift_srl(n)'left);
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end if;
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end if;
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end process srl_proc_b;
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rco_int(n) <= en_in and shift_srl(n)(shift_srl(n)'left);
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end generate tap_b;
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tap_cp: if n > 1 generate
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clk_en(n) <= rco_int(n-1) and rco_int(0);
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srl_proc_c :process (clk)
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begin
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if rising_edge( clk) then
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if clk_en(n) = '1' then
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shift_srl(n) <= shift_srl(n)(shift_srl(n)'left-1 downto 0) & shift_srl(n)(shift_srl(n)'left);
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end if;
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end if;
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end process srl_proc_c;
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rco_int(n) <= rco_int(n-1) and shift_srl(n)(shift_srl(n)'left);
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end generate tap_cp;
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rco <= rco_int;
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end generate gen_srls;
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end Behavioral;
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