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howe.r.j.8 |
-- File: bit.vhd
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-- Author: Richard James Howe
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-- Repository: https://github.com/howerj/bit-serial
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-- License: MIT
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-- Description: An N-bit, simple and small bit serial CPU
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library ieee, work, std;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all; -- for debug only, not needed for synthesis
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-- The bit-serial CPU itself, the interface is bit-serial as well as the
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-- CPU itself, address and data are N bits wide. The enable lines are held
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-- high for N cycles when data is clocked in or out, and a complete read or
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-- write consists of N cycles (although those cycles may not be contiguous,
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-- it is up to the BCPU). The three enable lines are mutually exclusive,
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-- only one will be active at any time.
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--
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-- There are a few configurable items, but the defaults should work fine.
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entity bcpu is
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generic (
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asynchronous_reset: boolean := true; -- use asynchronous reset if true, synchronous if false
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delay: time := 0 ns; -- simulation only, gate delay
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N: positive := 16; -- size the CPU, minimum is 8
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parity: std_ulogic := '0'; -- set parity (even = '0'/odd = '1') of parity flag
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jumpz: std_ulogic := '1'; -- jump on zero = '1', jump on non-zero = '0'
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debug: natural := 0); -- debug level, 0 = off
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port (
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clk, rst: in std_ulogic;
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i: in std_ulogic;
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o, a: out std_ulogic;
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oe, ie, ae: buffer std_ulogic;
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stop: out std_ulogic);
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end;
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architecture rtl of bcpu is
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type state_t is (RESET, FETCH, INDIRECT, OPERAND, EXECUTE, STORE, LOAD, ADVANCE, HALT);
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type cmd_t is (
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iOR, iAND, iXOR, iADD,
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iLSHIFT, iRSHIFT, iLOAD, iSTORE,
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iLOADC, iSTOREC, iLITERAL, iUNUSED,
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iJUMP, iJUMPZ, iSET, iGET);
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constant Cy: integer := 0; -- Carry; set by addition
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constant Z: integer := 1; -- Accumulator is zero
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constant Ng: integer := 2; -- Accumulator is negative
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constant R: integer := 3; -- Reset CPU
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constant HLT: integer := 4; -- Halt CPU
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type registers_t is record
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state: state_t; -- state machine register
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choice: state_t; -- computed next state
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first: boolean; -- First flag, for setting up an instruction
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last4: boolean; -- Are we processing the last 4 bits of the instruction?
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indir: boolean; -- does the instruction require indirection of the operand?
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tcarry: std_ulogic; -- temporary carry flag
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dline: std_ulogic_vector(N - 1 downto 0); -- delay line, 16 cycles, our timer
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acc: std_ulogic_vector(N - 1 downto 0); -- accumulator
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pc: std_ulogic_vector(N - 1 downto 0); -- program counter
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op: std_ulogic_vector(N - 1 downto 0); -- operand to instruction
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flags: std_ulogic_vector(N - 1 downto 0); -- flags register
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cmd: std_ulogic_vector(3 downto 0); -- instruction
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end record;
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constant registers_default: registers_t := (
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state => RESET,
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choice => RESET,
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first => true,
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last4 => false,
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indir => false,
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tcarry => 'X',
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dline => (others => '0'),
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acc => (others => 'X'),
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pc => (others => 'X'),
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op => (others => 'X'),
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flags => (others => 'X'),
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cmd => (others => 'X'));
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signal c, f: registers_t := registers_default; -- BCPU registers, all of them.
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-- These signals are not used to hold state. The 'c' and 'f' registers
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-- do that.
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signal cmd: cmd_t; -- Shows up nicely in traces as an enumerated value
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signal add1, add2, acin, ares, acout: std_ulogic; -- shared adder signals
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signal last4, last: std_ulogic; -- state sequence signals
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-- 'adder' implements a full adder, which is all we need to implement
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-- N-bit addition in a bit serial architecture. It is used in the instruction
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-- and to increment the program counter.
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procedure adder (x, y, cin: in std_ulogic; signal sum, cout: out std_ulogic) is
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begin
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sum <= x xor y xor cin after delay;
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cout <= (x and y) or (cin and (x xor y)) after delay;
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end procedure;
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-- 'bit_count' is used for assertions and nothing else. It counts the
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-- number of bits in a 'std_ulogic_vector'.
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function bit_count(bc: in std_ulogic_vector) return natural is
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variable count: natural := 0;
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begin
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for index in bc'range loop
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if bc(index) = '1' then
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count := count + 1;
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end if;
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end loop;
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return count;
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end function;
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-- Obviously this does not synthesis, which is why synthesis is turned
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-- off for the body of this function, it does make debugging much easier
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-- though, we will be able to see which instructions are executed and do so
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-- by name.
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procedure print_debug_info is
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variable ll: line;
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function hx(slv: in std_ulogic_vector) return string is -- std_ulogic_vector to hex string
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constant cv: string := "0123456789ABCDEF";
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constant qu: integer := slv'length / 4;
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constant rm: integer := slv'length mod 4;
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variable rs: string(1 to qu);
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variable sl: std_ulogic_vector(3 downto 0);
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begin
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assert rm = 0 severity failure;
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for l in 0 to qu - 1 loop
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sl := slv((l * 4) + 3 downto (l * 4));
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rs(qu - l) := cv(to_integer(unsigned(sl)) + 1);
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end loop;
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return rs;
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end function;
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function yn(sl: std_ulogic; ch: character) return string is -- print a flag
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variable rs: string(1 to 2) := "- ";
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begin
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if sl = '1' then
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rs(1) := ch;
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end if;
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return rs;
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end function;
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begin
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-- synthesis translate_off
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if debug > 0 then
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if c.state = EXECUTE and c.first then
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write(ll, hx(c.pc) & ": ");
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write(ll, cmd_t'image(cmd) & HT);
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write(ll, hx(c.acc) & " ");
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write(ll, hx(c.op) & " ");
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write(ll, hx(c.flags) & " ");
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write(ll, yn(c.flags(Cy), 'C'));
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write(ll, yn(c.flags(Z), 'Z'));
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write(ll, yn(c.flags(Ng), 'N'));
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write(ll, yn(c.flags(R), 'R'));
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write(ll, yn(c.flags(HLT), 'H'));
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writeline(OUTPUT, ll);
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end if;
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if debug > 1 and last = '1' then
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write(ll, state_t'image(c.state) & " => ");
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write(ll, state_t'image(f.state));
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writeline(OUTPUT, ll);
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end if;
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end if;
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-- synthesis translate_on
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end procedure;
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begin
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assert N >= 8 report "CPU Width too small: N >= 8" severity failure;
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assert not (ie = '1' and oe = '1') report "input/output at the same time" severity failure;
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assert not (ie = '1' and ae = '1') report "input whilst changing address" severity failure;
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assert not (oe = '1' and ae = '1') report "output whilst changing address" severity failure;
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adder (add1, add2, acin, ares, acout); -- shared adder
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cmd <= cmd_t'val(to_integer(unsigned(c.cmd))); -- used for debug purposes
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last4 <= c.dline(c.dline'high - 4) after delay; -- processing last four bits?
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last <= c.dline(c.dline'high) after delay; -- processing last bit?
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process (clk, rst) begin
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if rst = '1' and asynchronous_reset then
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c.dline <= (others => '0') after delay; -- parallel reset!
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c.state <= RESET after delay;
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elsif rising_edge(clk) then
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c <= f after delay;
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if rst = '1' and not asynchronous_reset then
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c.dline <= (others => '0') after delay;
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c.state <= RESET after delay;
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else
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-- These are just assertions/debug logging, they are not required for
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-- running, but we can make sure there are no unexpected state transitions,
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-- and report on the internal state.
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print_debug_info;
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if c.state = RESET and last = '1' then assert f.state = FETCH; end if;
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if c.state = LOAD and last = '1' then assert f.state = ADVANCE; end if;
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if c.state = STORE and last = '1' then assert f.state = ADVANCE; end if;
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if c.state = ADVANCE and last = '1' then assert f.state = FETCH; end if;
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if c.state = HALT then assert f.state = HALT; end if;
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if c.state = EXECUTE and last = '1' then
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assert f.state = ADVANCE or f.state = LOAD or f.state = STORE or f.state = FETCH;
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end if;
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end if;
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assert not (c.first xor f.dline(0) = '1') report "first/dline";
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end if;
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end process;
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process (i, c, cmd, ares, acout, last, last4) begin
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o <= '0' after delay;
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a <= '0' after delay;
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ie <= '0' after delay;
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ae <= '0' after delay;
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oe <= '0' after delay;
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stop <= '0' after delay;
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add1 <= '0' after delay;
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add2 <= '0' after delay;
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acin <= '0' after delay;
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f <= c after delay;
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f.dline <= c.dline(c.dline'high - 1 downto 0) & "0" after delay;
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-- Our delay line should only contain zero on one bit at a time
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if c.first then
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assert bit_count(c.dline) = 0 report "too many dline bits";
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else
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assert bit_count(c.dline) = 1 report "missing dline bit";
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end if;
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-- The processor works by using a delay line (shift register) to
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-- sequence actions, the top four bits are used for the
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-- instruction (and if the highest bit is set indirection
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-- is _not_ allowed), with the lowest twelve bits as an operand
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-- to use as a literal value or an address.
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--
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-- As such, we will want to trigger actions when processing the first
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-- bit, the last four bits and the last bit.
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--
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-- This delay line is used to save gates as opposed using a counter,
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-- which would require an adder (but not a comparator - we could check
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-- whether individual bits are set because all the comparisons are
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-- against power of two values).
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--
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if last = '1' then
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f.state <= c.choice after delay;
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f.first <= true after delay;
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f.last4 <= false after delay;
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-- This is a bit of a hack, in order to place it in its proper
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-- place within the 'FETCH' state we would need to move the
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-- 'indirection allowed on instruction' bit from the highest
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-- bit to a lower bit so we can perform the state decision before
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-- the bit is being processed.
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if i = '0' and c.state = FETCH then
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f.indir <= true;
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f.state <= INDIRECT; -- Override FETCH Choice!
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end if;
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elsif last4 = '1' then
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f.last4 <= true after delay;
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end if;
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-- Each state lasts N (which defaults to 16) + 1 cycles.
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-- Of note: we could make the FETCH state last only 4 + 1 cycles
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-- and merge the operand fetching in FETCH (and OPERAND state) into
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-- the 'EXECUTE' state.
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case c.state is
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when RESET =>
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f.choice <= FETCH;
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if c.first then
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f.dline(0) <= '1' after delay;
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f.first <= false after delay;
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else
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ae <= '1' after delay;
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f.acc <= "0" & c.acc(c.acc'high downto 1) after delay;
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f.pc <= "0" & c.pc (c.pc'high downto 1) after delay;
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f.op <= "0" & c.op (c.op'high downto 1) after delay;
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f.flags <= "0" & c.flags(c.flags'high downto 1) after delay;
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end if;
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-- When in the running state all state transitions pass through FETCH.
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-- FETCH does what you expect from it, it fetches the instruction. It also
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-- partially decodes it and sets flags that the accumulator depends on.
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--
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-- What is meant by partially decoding is this; it is determined if we
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-- should go to the INDIRECT state next or to the EXECUTE state, also
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-- it is determined whether an I/O operation should be performed for those
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-- instructions capable of doing I/O.
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when FETCH =>
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if c.first then
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f.dline(0) <= '1' after delay;
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f.first <= false after delay;
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f.indir <= false after delay;
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f.flags(Z) <= '1' after delay;
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else
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ie <= '1' after delay;
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if c.acc(0) = '1' then -- determine flag status before EXECUTE
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f.flags(Z) <= '0' after delay;
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end if;
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f.acc <= c.acc(0) & c.acc(c.acc'high downto 1) after delay;
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if not c.last4 then
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f.op <= i & c.op(c.op'high downto 1) after delay;
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else
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f.cmd <= i & c.cmd(c.cmd'high downto 1) after delay;
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f.op <= "0" & c.op (c.op'high downto 1) after delay;
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end if;
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end if;
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f.flags(Ng) <= c.acc(0) after delay; -- contains highest bit when 'last' is true
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-- NB. 'f.choice' may be overwritten for INDIRECT.
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| 301 |
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if c.flags(HLT) = '1' then
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f.choice <= HALT after delay;
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elsif c.flags(R) = '1' then
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f.choice <= RESET after delay;
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|
else
|
| 306 |
|
|
f.choice <= EXECUTE after delay;
|
| 307 |
|
|
end if;
|
| 308 |
|
|
-- INDIRECT is only used instruction allows for indirection
|
| 309 |
|
|
-- (ie. All those instructions in which the top bit is not set).
|
| 310 |
|
|
-- The indirection add 2*(N+1) cycles to the instruction so is quite expensive.
|
| 311 |
|
|
--
|
| 312 |
|
|
-- We could avoid having this state and CPU functionality if we were to
|
| 313 |
|
|
-- make use of self-modifying code, however that would make programming the CPU
|
| 314 |
|
|
-- more difficult.
|
| 315 |
|
|
--
|
| 316 |
|
|
when INDIRECT =>
|
| 317 |
|
|
assert c.cmd(c.cmd'high) = '0' severity error;
|
| 318 |
|
|
f.choice <= EXECUTE after delay;
|
| 319 |
|
|
if c.first then
|
| 320 |
|
|
f.dline(0) <= '1' after delay;
|
| 321 |
|
|
f.first <= false after delay;
|
| 322 |
|
|
else
|
| 323 |
|
|
ae <= '1' after delay;
|
| 324 |
|
|
a <= c.op(0) after delay;
|
| 325 |
|
|
f.op <= "0" & c.op(c.op'high downto 1) after delay;
|
| 326 |
|
|
f.choice <= OPERAND after delay;
|
| 327 |
|
|
end if;
|
| 328 |
|
|
-- OPERAND fetches the operand *again*, this time using the operand
|
| 329 |
|
|
-- acquired in EXECUTE, the address being set in the previous INDIRECT state.
|
| 330 |
|
|
when OPERAND =>
|
| 331 |
|
|
f.choice <= EXECUTE after delay;
|
| 332 |
|
|
if c.first then
|
| 333 |
|
|
f.dline(0) <= '1' after delay;
|
| 334 |
|
|
f.first <= false after delay;
|
| 335 |
|
|
else
|
| 336 |
|
|
ie <= '1' after delay;
|
| 337 |
|
|
f.op <= i & c.op(c.op'high downto 1) after delay;
|
| 338 |
|
|
end if;
|
| 339 |
|
|
-- The EXECUTE state implements the ALU. It is the most seemingly the
|
| 340 |
|
|
-- most complex state, but it is not (FETCH is more difficult to
|
| 341 |
|
|
-- understand).
|
| 342 |
|
|
when EXECUTE =>
|
| 343 |
|
|
assert not (c.flags(Z) = '1' and c.flags(Ng) = '1') report "zero and negative?";
|
| 344 |
|
|
f.choice <= ADVANCE after delay;
|
| 345 |
|
|
if c.first then
|
| 346 |
|
|
f.dline(0) <= '1' after delay;
|
| 347 |
|
|
f.first <= false after delay;
|
| 348 |
|
|
if cmd = iADD then f.flags(Cy) <= '0' after delay; end if;
|
| 349 |
|
|
-- 'tcarry' is added to the program counter in the ADVANCE
|
| 350 |
|
|
-- state, instructions that affect the program counter clear
|
| 351 |
|
|
-- it (such as iJUMP, and iJUMPZ/iSET (conditionally).
|
| 352 |
|
|
f.tcarry <= '1' after delay;
|
| 353 |
|
|
else
|
| 354 |
|
|
case cmd is -- ALU
|
| 355 |
|
|
when iOR =>
|
| 356 |
|
|
f.op <= "0" & c.op (c.op'high downto 1) after delay;
|
| 357 |
|
|
f.acc <= (c.op(0) or c.acc(0)) & c.acc(c.acc'high downto 1) after delay;
|
| 358 |
|
|
when iAND =>
|
| 359 |
|
|
f.acc <= c.acc(0) & c.acc(c.acc'high downto 1) after delay;
|
| 360 |
|
|
if (not c.last4) or c.indir then
|
| 361 |
|
|
f.op <= "0" & c.op (c.op'high downto 1) after delay;
|
| 362 |
|
|
f.acc <= (c.op(0) and c.acc(0)) & c.acc(c.acc'high downto 1) after delay;
|
| 363 |
|
|
end if;
|
| 364 |
|
|
when iXOR =>
|
| 365 |
|
|
f.op <= "0" & c.op (c.op'high downto 1) after delay;
|
| 366 |
|
|
f.acc <= (c.op(0) xor c.acc(0)) & c.acc(c.acc'high downto 1) after delay;
|
| 367 |
|
|
when iADD =>
|
| 368 |
|
|
f.acc <= "0" & c.acc(c.acc'high downto 1) after delay;
|
| 369 |
|
|
f.op <= "0" & c.op(c.op'high downto 1) after delay;
|
| 370 |
|
|
add1 <= c.acc(0) after delay;
|
| 371 |
|
|
add2 <= c.op(0) after delay;
|
| 372 |
|
|
acin <= c.flags(Cy) after delay;
|
| 373 |
|
|
f.acc(f.acc'high) <= ares after delay;
|
| 374 |
|
|
f.flags(Cy) <= acout after delay;
|
| 375 |
|
|
-- A barrel shifter is usually quite an expensive piece of hardware,
|
| 376 |
|
|
-- but it ends up being quite cheap for obvious reasons. If we really
|
| 377 |
|
|
-- needed to we could dispense with the right shift, we could mask off
|
| 378 |
|
|
-- low bits and rotate (either way) to emulate it.
|
| 379 |
|
|
when iLSHIFT =>
|
| 380 |
|
|
if c.op(0) = '1' then
|
| 381 |
|
|
f.acc <= c.acc(c.acc'high - 1 downto 0) & "0" after delay;
|
| 382 |
|
|
end if;
|
| 383 |
|
|
f.op <= "0" & c.op (c.op'high downto 1) after delay;
|
| 384 |
|
|
when iRSHIFT =>
|
| 385 |
|
|
if c.op(0) = '1' then
|
| 386 |
|
|
f.acc <= "0" & c.acc(c.acc'high downto 1) after delay;
|
| 387 |
|
|
end if;
|
| 388 |
|
|
f.op <= "0" & c.op (c.op'high downto 1) after delay;
|
| 389 |
|
|
-- We have two sets of LOAD/STORE instructions, one set which
|
| 390 |
|
|
-- optionally respects the indirect flag, and one set (the latter)
|
| 391 |
|
|
-- which never does. This allows us to perform direct LOAD/STORES
|
| 392 |
|
|
-- when the indirect flag is on.
|
| 393 |
|
|
when iLOAD =>
|
| 394 |
|
|
ae <= '1' after delay;
|
| 395 |
|
|
a <= c.op(0) after delay;
|
| 396 |
|
|
f.op <= c.op(0) & c.op(c.op'high downto 1) after delay;
|
| 397 |
|
|
f.choice <= LOAD after delay;
|
| 398 |
|
|
when iSTORE =>
|
| 399 |
|
|
ae <= '1' after delay;
|
| 400 |
|
|
a <= c.op(0) after delay;
|
| 401 |
|
|
f.op <= "0" & c.op(c.op'high downto 1) after delay;
|
| 402 |
|
|
f.choice <= STORE after delay;
|
| 403 |
|
|
when iLOADC =>
|
| 404 |
|
|
ae <= '1' after delay;
|
| 405 |
|
|
a <= c.op(0) after delay;
|
| 406 |
|
|
f.op <= c.op(0) & c.op(c.op'high downto 1) after delay;
|
| 407 |
|
|
f.choice <= LOAD after delay;
|
| 408 |
|
|
when iSTOREC =>
|
| 409 |
|
|
ae <= '1' after delay;
|
| 410 |
|
|
a <= c.op(0) after delay;
|
| 411 |
|
|
f.op <= "0" & c.op(c.op'high downto 1) after delay;
|
| 412 |
|
|
f.choice <= STORE after delay;
|
| 413 |
|
|
when iLITERAL =>
|
| 414 |
|
|
f.acc <= c.op(0) & c.acc(c.acc'high downto 1) after delay;
|
| 415 |
|
|
f.op <= "0" & c.op (c.op'high downto 1) after delay;
|
| 416 |
|
|
when iUNUSED =>
|
| 417 |
|
|
-- We could use this if we need to extend the instruction set
|
| 418 |
|
|
-- for any reason. I cannot think of a good one that justifies the
|
| 419 |
|
|
-- cost of a new instruction. So this will remain blank for now.
|
| 420 |
|
|
--
|
| 421 |
|
|
-- Candidates for an instruction include:
|
| 422 |
|
|
--
|
| 423 |
|
|
-- * Arithmetic Right Shift
|
| 424 |
|
|
-- * Subtraction
|
| 425 |
|
|
-- * Swap Low/High Byte (may be difficult to implement)
|
| 426 |
|
|
--
|
| 427 |
|
|
-- However, this instruction may not have its indirection bit set,
|
| 428 |
|
|
-- This would not be a problem for the swap instruction. Alternatively
|
| 429 |
|
|
-- an 'add-constant' could be added.
|
| 430 |
|
|
--
|
| 431 |
|
|
when iJUMP =>
|
| 432 |
|
|
ae <= '1' after delay;
|
| 433 |
|
|
a <= c.op(0) after delay;
|
| 434 |
|
|
f.op <= "0" & c.op(c.op'high downto 1) after delay;
|
| 435 |
|
|
f.pc <= c.op(0) & c.pc(c.pc'high downto 1) after delay;
|
| 436 |
|
|
f.choice <= FETCH after delay;
|
| 437 |
|
|
when iJUMPZ =>
|
| 438 |
|
|
if c.flags(Z) = jumpz then
|
| 439 |
|
|
ae <= '1' after delay;
|
| 440 |
|
|
a <= c.op(0) after delay;
|
| 441 |
|
|
f.op <= "0" & c.op(c.op'high downto 1) after delay;
|
| 442 |
|
|
f.pc <= c.op(0) & c.pc(c.pc'high downto 1) after delay;
|
| 443 |
|
|
f.choice <= FETCH after delay;
|
| 444 |
|
|
end if;
|
| 445 |
|
|
-- NB. We could probably eliminate these instructions by mapping
|
| 446 |
|
|
-- the registers into the memory address space, this would free
|
| 447 |
|
|
-- up another two instructions, and potentially simplify the CPU.
|
| 448 |
|
|
--
|
| 449 |
|
|
when iSET =>
|
| 450 |
|
|
if c.op(0) = '0' then
|
| 451 |
|
|
-- NB. We could set the address directly here and
|
| 452 |
|
|
-- go to FETCH but that costs us too much time and gates.
|
| 453 |
|
|
f.pc <= c.acc(0) & c.pc(c.pc'high downto 1) after delay;
|
| 454 |
|
|
f.tcarry <= '0' after delay;
|
| 455 |
|
|
else
|
| 456 |
|
|
f.flags <= c.acc(0) & c.flags(c.flags'high downto 1) after delay;
|
| 457 |
|
|
end if;
|
| 458 |
|
|
f.acc <= c.acc(0) & c.acc(c.acc'high downto 1) after delay;
|
| 459 |
|
|
when iGET =>
|
| 460 |
|
|
if c.op(0) = '0' then
|
| 461 |
|
|
f.acc <= c.pc(0) & c.acc(c.acc'high downto 1) after delay;
|
| 462 |
|
|
f.pc <= c.pc(0) & c.pc(c.pc'high downto 1) after delay;
|
| 463 |
|
|
else
|
| 464 |
|
|
f.acc <= c.flags(0) & c.acc(c.acc'high downto 1) after delay;
|
| 465 |
|
|
f.flags <= c.flags(0) & c.flags(c.flags'high downto 1) after delay;
|
| 466 |
|
|
end if;
|
| 467 |
|
|
end case;
|
| 468 |
|
|
end if;
|
| 469 |
|
|
-- Unfortunately we cannot perform a load or a store whilst we are
|
| 470 |
|
|
-- performing an EXECUTE, so we require STORE and LOAD states to do
|
| 471 |
|
|
-- more work after a LOAD or STORE instruction.
|
| 472 |
|
|
when STORE =>
|
| 473 |
|
|
f.choice <= ADVANCE after delay;
|
| 474 |
|
|
if c.first then
|
| 475 |
|
|
f.dline(0) <= '1' after delay;
|
| 476 |
|
|
f.first <= false after delay;
|
| 477 |
|
|
else
|
| 478 |
|
|
o <= c.acc(0) after delay;
|
| 479 |
|
|
oe <= '1' after delay;
|
| 480 |
|
|
f.acc <= c.acc(0) & c.acc(c.acc'high downto 1) after delay;
|
| 481 |
|
|
end if;
|
| 482 |
|
|
when LOAD =>
|
| 483 |
|
|
f.choice <= ADVANCE after delay;
|
| 484 |
|
|
if c.first then
|
| 485 |
|
|
f.dline(0) <= '1' after delay;
|
| 486 |
|
|
f.first <= false after delay;
|
| 487 |
|
|
else
|
| 488 |
|
|
ie <= '1' after delay;
|
| 489 |
|
|
f.acc <= i & c.acc(c.acc'high downto 1) after delay;
|
| 490 |
|
|
end if;
|
| 491 |
|
|
-- ADVANCE reuses our adder in iADD to add one to the program counter
|
| 492 |
|
|
-- this state *is* reached when we do a iJUMP, iJUMPZ or an iSET on the
|
| 493 |
|
|
-- program counter, those instructions clear the 'tcarry', which is
|
| 494 |
|
|
-- normally '1'.
|
| 495 |
|
|
when ADVANCE =>
|
| 496 |
|
|
f.choice <= FETCH after delay;
|
| 497 |
|
|
if c.first then
|
| 498 |
|
|
f.dline(0) <= '1' after delay;
|
| 499 |
|
|
f.first <= false after delay;
|
| 500 |
|
|
else
|
| 501 |
|
|
f.pc <= "0" & c.pc(c.pc'high downto 1) after delay;
|
| 502 |
|
|
add1 <= c.pc(0) after delay;
|
| 503 |
|
|
-- A 'skip' facility could be made by optionally setting this to '1'
|
| 504 |
|
|
-- for the first cycle, incrementing the program counter by 2.
|
| 505 |
|
|
add2 <= '0' after delay;
|
| 506 |
|
|
acin <= c.tcarry after delay;
|
| 507 |
|
|
f.pc(f.pc'high) <= ares after delay;
|
| 508 |
|
|
a <= ares after delay;
|
| 509 |
|
|
f.tcarry <= acout after delay;
|
| 510 |
|
|
ae <= '1' after delay;
|
| 511 |
|
|
end if;
|
| 512 |
|
|
when HALT => stop <= '1' after delay;
|
| 513 |
|
|
end case;
|
| 514 |
|
|
end process;
|
| 515 |
|
|
end architecture;
|
| 516 |
|
|
|
