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wd5gnr |
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Generating Report ...
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Number of warnings: 0
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Total time: 2 secs
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Started process "Generate Programming File".
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INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
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with the CLKFX and CLKFX180 outputs of the DCM comp
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CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
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Interactive Data Sheet.
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Project Navigator Auto-Make Log File
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-------------------------------------
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Started process "Map".
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Using target part "3s200ft256-4".
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Running related packing...
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Design Summary:
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Number of errors: 0
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Number of warnings: 5
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Logic Utilization:
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Number of Slice Flip Flops: 367 out of 3,840 9%
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Number of 4 input LUTs: 1,131 out of 3,840 29%
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Logic Distribution:
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Number of occupied Slices: 694 out of 1,920 36%
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Number of Slices containing only related logic: 694 out of 694 100%
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Number of Slices containing unrelated logic: 0 out of 694 0%
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*See NOTES below for an explanation of the effects of unrelated logic
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Total Number 4 input LUTs: 1,135 out of 3,840 29%
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Number used as logic: 1,131
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Number used as a route-thru: 4
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Number of bonded IOBs: 74 out of 173 42%
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IOB Flip Flops: 26
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Number of GCLKs: 2 out of 8 25%
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Number of DCMs: 1 out of 4 25%
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Total equivalent gate count for design: 17,815
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Additional JTAG gate count for IOBs: 3,552
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Peak Memory Usage: 113 MB
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NOTES:
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Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
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Map gives priority to combine logic that is related. Doing so results in
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the best timing performance.
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Unrelated logic shares no connectivity. Map will only begin packing
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unrelated logic into a slice once 99% of the slices are occupied through
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related logic packing.
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Note that once logic distribution reaches the 99% level through related
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logic packing, this does not mean the device is completely utilized.
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Unrelated logic packing will then begin, continuing until all usable LUTs
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and FFs are occupied. Depending on your timing budget, increased levels of
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unrelated logic packing may adversely affect the overall timing performance
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of your design.
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Mapping completed.
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See MAP report file "topbox_map.mrp" for details.
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Started process "Place & Route".
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Constraints file: topbox.pcf.
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Loading device for application Rf_Device from file '3s200.nph' in environment
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C:/Xilinx71.
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"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
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Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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Device speed data version: "PRODUCTION 1.35 2005-01-22".
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Device Utilization Summary:
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Number of BUFGMUXs 2 out of 8 25%
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Number of DCMs 1 out of 4 25%
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Number of External IOBs 74 out of 173 42%
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Number of LOCed IOBs 6 out of 74 8%
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Number of Slices 694 out of 1920 36%
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Number of SLICEMs 0 out of 960 0%
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Overall effort level (-ol): Standard (set by user)
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Placer effort level (-pl): Standard (set by user)
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Placer cost table entry (-t): 1
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Router effort level (-rl): Standard (set by user)
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Starting Placer
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Phase 1.1
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Phase 1.1 (Checksum:98af6c) REAL time: 1 secs
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Phase 2.31
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Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
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Phase 3.2
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.
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Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs
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Phase 4.3
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Phase 4.3 (Checksum:26259fc) REAL time: 1 secs
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Phase 5.5
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Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs
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Phase 6.8
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......................................
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Phase 6.8 (Checksum:a92ff3) REAL time: 1 secs
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Phase 7.5
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Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs
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Phase 8.18
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Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs
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Phase 9.5
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Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs
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Writing design to file topbox.ncd
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Total REAL time to Placer completion: 2 secs
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Total CPU time to Placer completion: 2 secs
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Starting Router
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Phase 1: 4717 unrouted; REAL time: 2 secs
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Phase 2: 4442 unrouted; REAL time: 2 secs
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Phase 3: 2150 unrouted; REAL time: 3 secs
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Phase 4: 0 unrouted; REAL time: 4 secs
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Total REAL time to Router completion: 4 secs
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Total CPU time to Router completion: 4 secs
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| clk | BUFGMUX0| No | 255 | 0.042 | 1.052 |
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+---------------------+--------------+------+------+------------+-------------+
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 4 secs
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Total CPU time to PAR completion: 4 secs
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Peak Memory Usage: 83 MB
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 1
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Writing design to file topbox.ncd
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PAR done!
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Started process "Generate Post-Place & Route Static Timing".
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Loading device for application Rf_Device from file '3s200.nph' in environment
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C:/Xilinx71.
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"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
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Analysis completed Sun Sep 24 10:26:34 2006
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--------------------------------------------------------------------------------
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Generating Report ...
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Number of warnings: 0
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Total time: 2 secs
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Started process "Generate Programming File".
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INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
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with the CLKFX and CLKFX180 outputs of the DCM comp
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CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
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Interactive Data Sheet.
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Project Navigator Auto-Make Log File
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-------------------------------------
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting " "
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ERROR: error deleting " ": no such file or directory
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deleting " "
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ERROR: error deleting " ": no such file or directory
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting " "
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ERROR: error deleting " ": no such file or directory
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deleting " "
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ERROR: error deleting " ": no such file or directory
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deleting " "
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ERROR: error deleting " ": no such file or directory
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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deleting "_impact.cmd"
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ERROR: error deleting "_impact.cmd": permission denied
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deleting "_impact.log"
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ERROR: error deleting "_impact.log": permission denied
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|
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deleting "_impact.cmd"
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| 362 |
|
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ERROR: error deleting "_impact.cmd": permission denied
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| 363 |
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|
| 364 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 365 |
|
|
deleting "_impact.cmd"
|
| 366 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 367 |
|
|
deleting "_impact.log"
|
| 368 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 369 |
|
|
deleting "_impact.cmd"
|
| 370 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 371 |
|
|
deleting "_impact.log"
|
| 372 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 373 |
|
|
deleting "_impact.cmd"
|
| 374 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 375 |
|
|
deleting "_impact.log"
|
| 376 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 377 |
|
|
deleting "_impact.cmd"
|
| 378 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 379 |
|
|
deleting "_impact.log"
|
| 380 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 381 |
|
|
deleting "_impact.cmd"
|
| 382 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 383 |
|
|
deleting "_impact.log"
|
| 384 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 385 |
|
|
deleting "_impact.cmd"
|
| 386 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 387 |
|
|
deleting "_impact.log"
|
| 388 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 389 |
|
|
deleting "_impact.cmd"
|
| 390 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 391 |
|
|
deleting "_impact.log"
|
| 392 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 393 |
|
|
deleting "_impact.cmd"
|
| 394 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 395 |
|
|
deleting "_impact.log"
|
| 396 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 397 |
|
|
deleting "_impact.cmd"
|
| 398 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 399 |
|
|
deleting "_impact.log"
|
| 400 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 401 |
|
|
deleting "_impact.cmd"
|
| 402 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 403 |
|
|
deleting "_impact.log"
|
| 404 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 405 |
|
|
deleting "_impact.cmd"
|
| 406 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 407 |
|
|
deleting "_impact.log"
|
| 408 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 409 |
|
|
deleting "_impact.cmd"
|
| 410 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 411 |
|
|
deleting "_impact.log"
|
| 412 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 413 |
|
|
deleting "_impact.cmd"
|
| 414 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 415 |
|
|
deleting "_impact.log"
|
| 416 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 417 |
|
|
deleting "_impact.cmd"
|
| 418 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 419 |
|
|
deleting "_impact.log"
|
| 420 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 421 |
|
|
deleting "_impact.cmd"
|
| 422 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 423 |
|
|
deleting "_impact.log"
|
| 424 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 425 |
|
|
deleting "_impact.cmd"
|
| 426 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 427 |
|
|
deleting "_impact.log"
|
| 428 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 429 |
|
|
deleting "_impact.cmd"
|
| 430 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 431 |
|
|
deleting "_impact.log"
|
| 432 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 433 |
|
|
deleting "_impact.cmd"
|
| 434 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 435 |
|
|
deleting "_impact.log"
|
| 436 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 437 |
|
|
deleting "_impact.cmd"
|
| 438 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 439 |
|
|
deleting "_impact.log"
|
| 440 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 441 |
|
|
deleting "_impact.cmd"
|
| 442 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 443 |
|
|
deleting "_impact.log"
|
| 444 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 445 |
|
|
deleting "_impact.cmd"
|
| 446 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 447 |
|
|
deleting "_impact.log"
|
| 448 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 449 |
|
|
deleting "_impact.cmd"
|
| 450 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 451 |
|
|
deleting "_impact.log"
|
| 452 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 453 |
|
|
deleting "_impact.cmd"
|
| 454 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 455 |
|
|
deleting "_impact.log"
|
| 456 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 457 |
|
|
deleting "_impact.cmd"
|
| 458 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 459 |
|
|
deleting "_impact.log"
|
| 460 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 461 |
|
|
deleting "_impact.cmd"
|
| 462 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 463 |
|
|
deleting "_impact.log"
|
| 464 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 465 |
|
|
deleting "_impact.cmd"
|
| 466 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 467 |
|
|
deleting "_impact.log"
|
| 468 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 469 |
|
|
deleting "_impact.cmd"
|
| 470 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 471 |
|
|
deleting "_impact.log"
|
| 472 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 473 |
|
|
deleting "_impact.cmd"
|
| 474 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 475 |
|
|
deleting "_impact.log"
|
| 476 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 477 |
|
|
deleting "_impact.cmd"
|
| 478 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 479 |
|
|
deleting "_impact.log"
|
| 480 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 481 |
|
|
deleting "_impact.cmd"
|
| 482 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 483 |
|
|
deleting "_impact.log"
|
| 484 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 485 |
|
|
deleting "_impact.cmd"
|
| 486 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 487 |
|
|
deleting "_impact.log"
|
| 488 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 489 |
|
|
deleting "_impact.cmd"
|
| 490 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 491 |
|
|
deleting "_impact.log"
|
| 492 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 493 |
|
|
deleting "_impact.cmd"
|
| 494 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 495 |
|
|
deleting "_impact.log"
|
| 496 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 497 |
|
|
deleting "_impact.cmd"
|
| 498 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 499 |
|
|
deleting "_impact.log"
|
| 500 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 501 |
|
|
deleting "_impact.cmd"
|
| 502 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 503 |
|
|
deleting "_impact.log"
|
| 504 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 505 |
|
|
deleting "_impact.cmd"
|
| 506 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 507 |
|
|
deleting "_impact.log"
|
| 508 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 509 |
|
|
deleting "_impact.cmd"
|
| 510 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 511 |
|
|
deleting "_impact.log"
|
| 512 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 513 |
|
|
deleting "_impact.cmd"
|
| 514 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 515 |
|
|
deleting "_impact.log"
|
| 516 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 517 |
|
|
deleting "_impact.cmd"
|
| 518 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 519 |
|
|
deleting "_impact.log"
|
| 520 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 521 |
|
|
deleting "_impact.cmd"
|
| 522 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 523 |
|
|
deleting "_impact.log"
|
| 524 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 525 |
|
|
deleting "_impact.cmd"
|
| 526 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 527 |
|
|
deleting "_impact.log"
|
| 528 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 529 |
|
|
deleting "_impact.cmd"
|
| 530 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 531 |
|
|
deleting "_impact.log"
|
| 532 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 533 |
|
|
deleting "_impact.cmd"
|
| 534 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 535 |
|
|
deleting "_impact.log"
|
| 536 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 537 |
|
|
deleting "_impact.cmd"
|
| 538 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 539 |
|
|
deleting "_impact.log"
|
| 540 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 541 |
|
|
deleting "_impact.cmd"
|
| 542 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 543 |
|
|
deleting "_impact.log"
|
| 544 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 545 |
|
|
deleting "_impact.cmd"
|
| 546 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 547 |
|
|
deleting "_impact.log"
|
| 548 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 549 |
|
|
deleting "_impact.cmd"
|
| 550 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 551 |
|
|
deleting "_impact.log"
|
| 552 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 553 |
|
|
deleting "_impact.cmd"
|
| 554 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 555 |
|
|
deleting "_impact.log"
|
| 556 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 557 |
|
|
deleting "_impact.cmd"
|
| 558 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 559 |
|
|
deleting "_impact.log"
|
| 560 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 561 |
|
|
deleting "_impact.cmd"
|
| 562 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 563 |
|
|
deleting "_impact.log"
|
| 564 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 565 |
|
|
deleting "_impact.cmd"
|
| 566 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 567 |
|
|
deleting "_impact.log"
|
| 568 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 569 |
|
|
deleting "_impact.cmd"
|
| 570 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 571 |
|
|
deleting "_impact.log"
|
| 572 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 573 |
|
|
deleting "_impact.cmd"
|
| 574 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 575 |
|
|
deleting "_impact.log"
|
| 576 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 577 |
|
|
deleting "_impact.cmd"
|
| 578 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 579 |
|
|
deleting "_impact.log"
|
| 580 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 581 |
|
|
deleting "_impact.cmd"
|
| 582 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 583 |
|
|
deleting "_impact.log"
|
| 584 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 585 |
|
|
deleting "_impact.cmd"
|
| 586 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 587 |
|
|
deleting "_impact.log"
|
| 588 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 589 |
|
|
deleting "_impact.cmd"
|
| 590 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 591 |
|
|
deleting "_impact.log"
|
| 592 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 593 |
|
|
deleting "_impact.cmd"
|
| 594 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 595 |
|
|
deleting "_impact.log"
|
| 596 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 597 |
|
|
deleting "_impact.cmd"
|
| 598 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 599 |
|
|
deleting "_impact.log"
|
| 600 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 601 |
|
|
deleting "_impact.cmd"
|
| 602 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 603 |
|
|
deleting "_impact.log"
|
| 604 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 605 |
|
|
deleting "_impact.log"
|
| 606 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 607 |
|
|
deleting "_impact.cmd"
|
| 608 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 609 |
|
|
deleting "_impact.cmd"
|
| 610 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 611 |
|
|
deleting "_impact.log"
|
| 612 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 613 |
|
|
deleting "_impact.cmd"
|
| 614 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 615 |
|
|
deleting "_impact.log"
|
| 616 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 617 |
|
|
deleting "_impact.cmd"
|
| 618 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 619 |
|
|
deleting "_impact.log"
|
| 620 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 621 |
|
|
deleting "_impact.cmd"
|
| 622 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 623 |
|
|
deleting "_impact.log"
|
| 624 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 625 |
|
|
deleting "_impact.cmd"
|
| 626 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 627 |
|
|
deleting "_impact.log"
|
| 628 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 629 |
|
|
deleting "_impact.cmd"
|
| 630 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 631 |
|
|
deleting "_impact.log"
|
| 632 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 633 |
|
|
deleting "_impact.cmd"
|
| 634 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 635 |
|
|
deleting "_impact.log"
|
| 636 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 637 |
|
|
deleting "_impact.cmd"
|
| 638 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 639 |
|
|
deleting "_impact.log"
|
| 640 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 641 |
|
|
deleting "_impact.cmd"
|
| 642 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 643 |
|
|
deleting "_impact.log"
|
| 644 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 645 |
|
|
deleting "_impact.cmd"
|
| 646 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 647 |
|
|
deleting "_impact.log"
|
| 648 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 649 |
|
|
deleting "_impact.cmd"
|
| 650 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 651 |
|
|
deleting "_impact.log"
|
| 652 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 653 |
|
|
deleting "_impact.cmd"
|
| 654 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 655 |
|
|
deleting "_impact.log"
|
| 656 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 657 |
|
|
deleting "_impact.cmd"
|
| 658 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 659 |
|
|
deleting "_impact.log"
|
| 660 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 661 |
|
|
deleting "_impact.cmd"
|
| 662 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 663 |
|
|
deleting "_impact.log"
|
| 664 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 665 |
|
|
deleting "_impact.cmd"
|
| 666 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 667 |
|
|
deleting "_impact.log"
|
| 668 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 669 |
|
|
deleting "_impact.cmd"
|
| 670 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 671 |
|
|
deleting "_impact.log"
|
| 672 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 673 |
|
|
deleting "_impact.cmd"
|
| 674 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 675 |
|
|
deleting "_impact.log"
|
| 676 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 677 |
|
|
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ERROR: error deleting "_impact.cmd": permission denied
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ERROR: error deleting "_impact.log": permission denied
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ERROR: error deleting "_impact.cmd": permission denied
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ERROR: error deleting "_impact.log": permission denied
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|
ERROR: error deleting "_impact.cmd": permission denied
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ERROR: error deleting "_impact.log": permission denied
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|
ERROR: error deleting "_impact.cmd": permission denied
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|
ERROR: error deleting "_impact.log": permission denied
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|
ERROR: error deleting "_impact.cmd": permission denied
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|
ERROR: error deleting "_impact.log": permission denied
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|
ERROR: error deleting "_impact.cmd": permission denied
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|
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| 700 |
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|
ERROR: error deleting "_impact.log": permission denied
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|
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|
ERROR: error deleting "_impact.cmd": permission denied
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| 703 |
|
|
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|
ERROR: error deleting "_impact.log": permission denied
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|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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|
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| 708 |
|
|
ERROR: error deleting "_impact.log": permission denied
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|
|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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|
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|
|
ERROR: error deleting "_impact.log": permission denied
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|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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|
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|
|
ERROR: error deleting "_impact.log": permission denied
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|
|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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|
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| 720 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 721 |
|
|
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| 722 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 723 |
|
|
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| 724 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 725 |
|
|
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| 726 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 727 |
|
|
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| 728 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 729 |
|
|
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| 730 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 731 |
|
|
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|
|
ERROR: error deleting "_impact.log": permission denied
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| 733 |
|
|
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| 734 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 735 |
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|
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| 736 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 737 |
|
|
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| 738 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 739 |
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|
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| 740 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 741 |
|
|
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| 742 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 743 |
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|
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| 744 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 745 |
|
|
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| 746 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 747 |
|
|
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| 748 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 749 |
|
|
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| 750 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 751 |
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|
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| 752 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 753 |
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|
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| 754 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 755 |
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|
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| 756 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 757 |
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|
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| 758 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 759 |
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|
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| 760 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 761 |
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|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 763 |
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|
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| 764 |
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|
ERROR: error deleting "_impact.log": permission denied
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| 765 |
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|
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|
ERROR: error deleting "_impact.cmd": permission denied
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| 767 |
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|
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| 768 |
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|
ERROR: error deleting "_impact.log": permission denied
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| 769 |
|
|
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| 770 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 771 |
|
|
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| 772 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 773 |
|
|
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| 774 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 775 |
|
|
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| 776 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 777 |
|
|
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| 778 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 779 |
|
|
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| 780 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 781 |
|
|
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| 782 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 783 |
|
|
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| 784 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 785 |
|
|
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| 786 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 787 |
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|
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| 788 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 789 |
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|
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| 790 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 791 |
|
|
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| 792 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 793 |
|
|
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| 794 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 795 |
|
|
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| 796 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 797 |
|
|
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| 798 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 799 |
|
|
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| 800 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 801 |
|
|
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| 802 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 803 |
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|
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| 804 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 805 |
|
|
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| 806 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 807 |
|
|
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| 808 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 809 |
|
|
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| 810 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 811 |
|
|
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| 812 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 813 |
|
|
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| 814 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 815 |
|
|
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| 816 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 817 |
|
|
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| 818 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 819 |
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|
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| 820 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 821 |
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|
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| 822 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 823 |
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|
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| 824 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 825 |
|
|
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|
| 826 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 827 |
|
|
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| 828 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 829 |
|
|
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|
| 830 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 831 |
|
|
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|
| 832 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 833 |
|
|
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| 834 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 835 |
|
|
deleting "_impact.log"
|
| 836 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 837 |
|
|
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|
| 838 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 839 |
|
|
deleting "_impact.log"
|
| 840 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 841 |
|
|
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|
| 842 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 843 |
|
|
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|
| 844 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 845 |
|
|
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|
| 846 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 847 |
|
|
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| 848 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 849 |
|
|
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| 850 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 851 |
|
|
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|
| 852 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 853 |
|
|
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|
| 854 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 855 |
|
|
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| 856 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 857 |
|
|
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|
| 858 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 859 |
|
|
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|
| 860 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 861 |
|
|
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| 862 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 863 |
|
|
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| 864 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 865 |
|
|
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|
| 866 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 867 |
|
|
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| 868 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 869 |
|
|
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| 870 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 871 |
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|
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| 872 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 873 |
|
|
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|
| 874 |
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|
ERROR: error deleting "_impact.cmd": permission denied
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| 875 |
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|
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| 876 |
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|
ERROR: error deleting "_impact.log": permission denied
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| 877 |
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|
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| 878 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 879 |
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|
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| 880 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 881 |
|
|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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|
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| 884 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 885 |
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|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 887 |
|
|
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| 888 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 889 |
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|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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|
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|
|
ERROR: error deleting "_impact.log": permission denied
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| 893 |
|
|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 895 |
|
|
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| 896 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 897 |
|
|
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| 898 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 899 |
|
|
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| 900 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 901 |
|
|
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|
| 902 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 903 |
|
|
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|
| 904 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 905 |
|
|
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|
| 906 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 907 |
|
|
deleting "_impact.log"
|
| 908 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 909 |
|
|
deleting "_impact.cmd"
|
| 910 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 911 |
|
|
deleting "_impact.log"
|
| 912 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 913 |
|
|
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|
| 914 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 915 |
|
|
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| 916 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 917 |
|
|
deleting "_impact.cmd"
|
| 918 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 919 |
|
|
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|
| 920 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 921 |
|
|
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|
| 922 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 923 |
|
|
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|
| 924 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 925 |
|
|
deleting "_impact.cmd"
|
| 926 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 927 |
|
|
deleting "_impact.log"
|
| 928 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 929 |
|
|
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|
| 930 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 931 |
|
|
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|
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|
|
ERROR: error deleting "_impact.log": permission denied
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|
|
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|
| 934 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 935 |
|
|
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| 936 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 937 |
|
|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 939 |
|
|
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| 940 |
|
|
ERROR: error deleting "_impact.log": permission denied
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| 941 |
|
|
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|
| 942 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 943 |
|
|
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| 944 |
|
|
ERROR: error deleting "_impact.log": permission denied
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|
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|
|
ERROR: error deleting "_impact.log": permission denied
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|
|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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|
|
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|
|
ERROR: error deleting "_impact.log": permission denied
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|
|
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|
ERROR: error deleting "_impact.cmd": permission denied
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|
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|
|
ERROR: error deleting "_impact.log": permission denied
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|
|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 957 |
|
|
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|
|
ERROR: error deleting "_impact.log": permission denied
|
| 959 |
|
|
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| 960 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 961 |
|
|
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|
|
ERROR: error deleting "_impact.cmd": permission denied
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| 963 |
|
|
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|
ERROR: error deleting "_impact.log": permission denied
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|
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|
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| 1967 |
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| 1968 |
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| 1970 |
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| 1971 |
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| 1972 |
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| 1973 |
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| 1974 |
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| 1975 |
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| 1978 |
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| 1979 |
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| 1980 |
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| 1981 |
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| 1982 |
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| 1983 |
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| 1984 |
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| 1985 |
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| 1986 |
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| 1987 |
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| 1988 |
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| 1989 |
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| 1990 |
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| 1991 |
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| 1992 |
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| 1993 |
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| 1994 |
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| 1995 |
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| 1996 |
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| 1998 |
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| 2000 |
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| 2001 |
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| 2002 |
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| 2003 |
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| 2004 |
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| 2005 |
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| 2006 |
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| 2007 |
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| 2008 |
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| 2009 |
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| 2010 |
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| 2011 |
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| 2012 |
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| 2013 |
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| 2014 |
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| 2015 |
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| 2016 |
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| 2017 |
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| 2018 |
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| 2019 |
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| 2020 |
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| 2021 |
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| 2022 |
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| 2023 |
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| 2024 |
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| 2025 |
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| 2026 |
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| 2027 |
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| 2028 |
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| 2029 |
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|
| 2030 |
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| 2031 |
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| 2032 |
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| 2033 |
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| 2034 |
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| 2035 |
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| 2036 |
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| 2037 |
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| 2038 |
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| 2039 |
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| 2040 |
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| 2041 |
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| 2047 |
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| 2048 |
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| 2049 |
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| 2050 |
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| 2051 |
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| 2053 |
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| 2054 |
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| 2055 |
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| 2056 |
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| 2057 |
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| 2058 |
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| 2059 |
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| 2060 |
|
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| 2061 |
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| 2062 |
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| 2063 |
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| 2064 |
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| 2065 |
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| 2066 |
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| 2067 |
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| 2068 |
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| 2069 |
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| 2070 |
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| 2071 |
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| 2072 |
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| 2073 |
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| 2074 |
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| 2075 |
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| 2076 |
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|
| 2077 |
|
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| 2078 |
|
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| 2079 |
|
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| 2080 |
|
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| 2081 |
|
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|
| 2082 |
|
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|
| 2083 |
|
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|
| 2084 |
|
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| 2085 |
|
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| 2086 |
|
|
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| 2087 |
|
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|
| 2088 |
|
|
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|
| 2089 |
|
|
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|
| 2090 |
|
|
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|
| 2091 |
|
|
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|
| 2092 |
|
|
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|
| 2093 |
|
|
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|
| 2094 |
|
|
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|
| 2095 |
|
|
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|
| 2096 |
|
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|
| 2097 |
|
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|
| 2098 |
|
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|
| 2099 |
|
|
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|
| 2100 |
|
|
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|
| 2101 |
|
|
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|
| 2102 |
|
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|
| 2103 |
|
|
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|
| 2104 |
|
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|
| 2105 |
|
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|
| 2106 |
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|
| 2107 |
|
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|
| 2108 |
|
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|
| 2109 |
|
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|
| 2110 |
|
|
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|
| 2111 |
|
|
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|
| 2112 |
|
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|
| 2113 |
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|
| 2114 |
|
|
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|
| 2115 |
|
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|
| 2116 |
|
|
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|
| 2117 |
|
|
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|
| 2118 |
|
|
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|
| 2119 |
|
|
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|
| 2120 |
|
|
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|
| 2121 |
|
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|
| 2122 |
|
|
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|
| 2123 |
|
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|
| 2124 |
|
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|
| 2125 |
|
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|
| 2126 |
|
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|
| 2127 |
|
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|
| 2128 |
|
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|
| 2129 |
|
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|
| 2130 |
|
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|
| 2131 |
|
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|
| 2132 |
|
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|
| 2133 |
|
|
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|
| 2134 |
|
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|
| 2135 |
|
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|
| 2136 |
|
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|
| 2137 |
|
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|
| 2138 |
|
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|
| 2139 |
|
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|
| 2140 |
|
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|
| 2141 |
|
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|
| 2142 |
|
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|
| 2143 |
|
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|
| 2144 |
|
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|
| 2145 |
|
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|
| 2146 |
|
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|
| 2147 |
|
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|
| 2148 |
|
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|
| 2149 |
|
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|
| 2150 |
|
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|
| 2151 |
|
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|
| 2152 |
|
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|
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deleting "topbox_ngdbuild.nav"
|
| 2733 |
|
|
deleting "topbox.bld"
|
| 2734 |
|
|
deleting "tobox.ucf.untf"
|
| 2735 |
|
|
deleting "topbox.cmd_log"
|
| 2736 |
|
|
deleting "topbox_summary.html"
|
| 2737 |
|
|
deleting "topbox_map.ncd"
|
| 2738 |
|
|
deleting "topbox.ngm"
|
| 2739 |
|
|
deleting "topbox.pcf"
|
| 2740 |
|
|
deleting "topbox.nc1"
|
| 2741 |
|
|
deleting "topbox.mrp"
|
| 2742 |
|
|
deleting "topbox_map.mrp"
|
| 2743 |
|
|
deleting "topbox.mdf"
|
| 2744 |
|
|
deleting "topbox.cmd_log"
|
| 2745 |
|
|
deleting "topbox_map.ngm"
|
| 2746 |
|
|
deleting "__projnav/ncdTOtwr_tcl.rsp"
|
| 2747 |
|
|
deleting "topbox.twr"
|
| 2748 |
|
|
deleting "topbox.twx"
|
| 2749 |
|
|
deleting "topbox.tsi"
|
| 2750 |
|
|
deleting "topbox.cmd_log"
|
| 2751 |
|
|
deleting "topbox_summary.html"
|
| 2752 |
|
|
deleting "__projnav/nc1TOncd_tcl.rsp"
|
| 2753 |
|
|
deleting "topbox.ncd"
|
| 2754 |
|
|
deleting "topbox.par"
|
| 2755 |
|
|
deleting "topbox.pad"
|
| 2756 |
|
|
deleting "topbox_pad.txt"
|
| 2757 |
|
|
deleting "topbox_pad.csv"
|
| 2758 |
|
|
deleting "topbox.pad_txt"
|
| 2759 |
|
|
deleting "topbox.dly"
|
| 2760 |
|
|
deleting "reportgen.log"
|
| 2761 |
|
|
deleting "topbox.xpi"
|
| 2762 |
|
|
deleting "topbox.grf"
|
| 2763 |
|
|
deleting "topbox.itr"
|
| 2764 |
|
|
deleting "topbox_last_par.ncd"
|
| 2765 |
|
|
deleting "topbox.placed_ncd_tracker"
|
| 2766 |
|
|
deleting "topbox.routed_ncd_tracker"
|
| 2767 |
|
|
deleting "topbox.cmd_log"
|
| 2768 |
|
|
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
|
| 2769 |
|
|
deleting "__projnav/bitgen.rsp"
|
| 2770 |
|
|
deleting "bitgen.ut"
|
| 2771 |
|
|
deleting "topbox.ut"
|
| 2772 |
|
|
deleting "topbox.bgn"
|
| 2773 |
|
|
deleting "topbox.rbt"
|
| 2774 |
|
|
deleting "topbox.ll"
|
| 2775 |
|
|
deleting "topbox.msk"
|
| 2776 |
|
|
deleting "topbox.drc"
|
| 2777 |
|
|
deleting "topbox.nky"
|
| 2778 |
|
|
deleting "topbox.bit"
|
| 2779 |
|
|
deleting "topbox.bin"
|
| 2780 |
|
|
deleting "topbox.isc"
|
| 2781 |
|
|
deleting "topbox.cmd_log"
|
| 2782 |
|
|
deleting "__projnav/ednTOngd_tcl.rsp"
|
| 2783 |
|
|
deleting ""c:\blue71/_ngo""
|
| 2784 |
|
|
deleting "topbox.ngd"
|
| 2785 |
|
|
deleting "topbox_ngdbuild.nav"
|
| 2786 |
|
|
deleting "topbox.bld"
|
| 2787 |
|
|
deleting "tobox.ucf.untf"
|
| 2788 |
|
|
deleting "topbox.cmd_log"
|
| 2789 |
|
|
deleting "__projnav/ednTOngd_tcl.rsp"
|
| 2790 |
|
|
deleting ""c:\blue71/_ngo""
|
| 2791 |
|
|
deleting "topbox.ngd"
|
| 2792 |
|
|
deleting "topbox_ngdbuild.nav"
|
| 2793 |
|
|
deleting "topbox.bld"
|
| 2794 |
|
|
deleting "tobox.ucf.untf"
|
| 2795 |
|
|
deleting "topbox.cmd_log"
|
| 2796 |
|
|
deleting "topbox_summary.html"
|
| 2797 |
|
|
deleting "topbox_map.ncd"
|
| 2798 |
|
|
deleting "topbox.ngm"
|
| 2799 |
|
|
deleting "topbox.pcf"
|
| 2800 |
|
|
deleting "topbox.nc1"
|
| 2801 |
|
|
deleting "topbox.mrp"
|
| 2802 |
|
|
deleting "topbox_map.mrp"
|
| 2803 |
|
|
deleting "topbox.mdf"
|
| 2804 |
|
|
deleting "topbox.cmd_log"
|
| 2805 |
|
|
deleting "topbox_map.ngm"
|
| 2806 |
|
|
deleting "__projnav/ncdTOtwr_tcl.rsp"
|
| 2807 |
|
|
deleting "topbox.twr"
|
| 2808 |
|
|
deleting "topbox.twx"
|
| 2809 |
|
|
deleting "topbox.tsi"
|
| 2810 |
|
|
deleting "topbox.cmd_log"
|
| 2811 |
|
|
deleting "topbox_summary.html"
|
| 2812 |
|
|
deleting "__projnav/nc1TOncd_tcl.rsp"
|
| 2813 |
|
|
deleting "topbox.ncd"
|
| 2814 |
|
|
deleting "topbox.par"
|
| 2815 |
|
|
deleting "topbox.pad"
|
| 2816 |
|
|
deleting "topbox_pad.txt"
|
| 2817 |
|
|
deleting "topbox_pad.csv"
|
| 2818 |
|
|
deleting "topbox.pad_txt"
|
| 2819 |
|
|
deleting "topbox.dly"
|
| 2820 |
|
|
deleting "reportgen.log"
|
| 2821 |
|
|
deleting "topbox.xpi"
|
| 2822 |
|
|
deleting "topbox.grf"
|
| 2823 |
|
|
deleting "topbox.itr"
|
| 2824 |
|
|
deleting "topbox_last_par.ncd"
|
| 2825 |
|
|
deleting "topbox.placed_ncd_tracker"
|
| 2826 |
|
|
deleting "topbox.routed_ncd_tracker"
|
| 2827 |
|
|
deleting "topbox.cmd_log"
|
| 2828 |
|
|
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
|
| 2829 |
|
|
deleting "__projnav/bitgen.rsp"
|
| 2830 |
|
|
deleting "bitgen.ut"
|
| 2831 |
|
|
deleting "topbox.ut"
|
| 2832 |
|
|
deleting "topbox.bgn"
|
| 2833 |
|
|
deleting "topbox.rbt"
|
| 2834 |
|
|
deleting "topbox.ll"
|
| 2835 |
|
|
deleting "topbox.msk"
|
| 2836 |
|
|
deleting "topbox.drc"
|
| 2837 |
|
|
deleting "topbox.nky"
|
| 2838 |
|
|
deleting "topbox.bit"
|
| 2839 |
|
|
deleting "topbox.bin"
|
| 2840 |
|
|
deleting "topbox.isc"
|
| 2841 |
|
|
deleting "topbox.cmd_log"
|
| 2842 |
|
|
deleting "__projnav/maindcm_jhdparse_tcl.rsp"
|
| 2843 |
|
|
deleting "maindcm.v"
|
| 2844 |
|
|
deleting "xaw2verilog.log"
|
| 2845 |
|
|
deleting "topbox.lso"
|
| 2846 |
|
|
deleting "topbox_summary.html"
|
| 2847 |
|
|
deleting "topbox.syr"
|
| 2848 |
|
|
deleting "topbox.prj"
|
| 2849 |
|
|
deleting "topbox.sprj"
|
| 2850 |
|
|
deleting "topbox.ana"
|
| 2851 |
|
|
deleting "topbox.stx"
|
| 2852 |
|
|
deleting "topbox.cmd_log"
|
| 2853 |
|
|
deleting "topbox.ngc"
|
| 2854 |
|
|
deleting "topbox.ngr"
|
| 2855 |
|
|
deleting "__projnav/ednTOngd_tcl.rsp"
|
| 2856 |
|
|
deleting ""c:\blue71/_ngo""
|
| 2857 |
|
|
deleting "topbox.ngd"
|
| 2858 |
|
|
deleting "topbox_ngdbuild.nav"
|
| 2859 |
|
|
deleting "topbox.bld"
|
| 2860 |
|
|
deleting "tobox.ucf.untf"
|
| 2861 |
|
|
deleting "topbox.cmd_log"
|
| 2862 |
|
|
deleting "topbox_summary.html"
|
| 2863 |
|
|
deleting "topbox_map.ncd"
|
| 2864 |
|
|
deleting "topbox.ngm"
|
| 2865 |
|
|
deleting "topbox.pcf"
|
| 2866 |
|
|
deleting "topbox.nc1"
|
| 2867 |
|
|
deleting "topbox.mrp"
|
| 2868 |
|
|
deleting "topbox_map.mrp"
|
| 2869 |
|
|
deleting "topbox.mdf"
|
| 2870 |
|
|
deleting "topbox.cmd_log"
|
| 2871 |
|
|
deleting "topbox_map.ngm"
|
| 2872 |
|
|
deleting "__projnav/ncdTOtwr_tcl.rsp"
|
| 2873 |
|
|
deleting "topbox.twr"
|
| 2874 |
|
|
deleting "topbox.twx"
|
| 2875 |
|
|
deleting "topbox.tsi"
|
| 2876 |
|
|
deleting "topbox.cmd_log"
|
| 2877 |
|
|
deleting "topbox_summary.html"
|
| 2878 |
|
|
deleting "__projnav/nc1TOncd_tcl.rsp"
|
| 2879 |
|
|
deleting "topbox.ncd"
|
| 2880 |
|
|
deleting "topbox.par"
|
| 2881 |
|
|
deleting "topbox.pad"
|
| 2882 |
|
|
deleting "topbox_pad.txt"
|
| 2883 |
|
|
deleting "topbox_pad.csv"
|
| 2884 |
|
|
deleting "topbox.pad_txt"
|
| 2885 |
|
|
deleting "topbox.dly"
|
| 2886 |
|
|
deleting "reportgen.log"
|
| 2887 |
|
|
deleting "topbox.xpi"
|
| 2888 |
|
|
deleting "topbox.grf"
|
| 2889 |
|
|
deleting "topbox.itr"
|
| 2890 |
|
|
deleting "topbox_last_par.ncd"
|
| 2891 |
|
|
deleting "topbox.placed_ncd_tracker"
|
| 2892 |
|
|
deleting "topbox.routed_ncd_tracker"
|
| 2893 |
|
|
deleting "topbox.cmd_log"
|
| 2894 |
|
|
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
|
| 2895 |
|
|
deleting "__projnav/bitgen.rsp"
|
| 2896 |
|
|
deleting "bitgen.ut"
|
| 2897 |
|
|
deleting "topbox.ut"
|
| 2898 |
|
|
deleting "topbox.bgn"
|
| 2899 |
|
|
deleting "topbox.rbt"
|
| 2900 |
|
|
deleting "topbox.ll"
|
| 2901 |
|
|
deleting "topbox.msk"
|
| 2902 |
|
|
deleting "topbox.drc"
|
| 2903 |
|
|
deleting "topbox.nky"
|
| 2904 |
|
|
deleting "topbox.bit"
|
| 2905 |
|
|
deleting "topbox.bin"
|
| 2906 |
|
|
deleting "topbox.isc"
|
| 2907 |
|
|
deleting "topbox.cmd_log"
|
| 2908 |
|
|
deleting "topbox.dly"
|
| 2909 |
|
|
deleting "reportgen.log"
|
| 2910 |
|
|
deleting "topbox_summary.html"
|
| 2911 |
|
|
deleting "if"
|
| 2912 |
|
|
deleting " $IsCopy "
|
| 2913 |
|
|
deleting ""
|
| 2914 |
|
|
deleting " Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File" "$HDLModule""
|
| 2915 |
|
|
deleting " "
|
| 2916 |
|
|
ERROR: error deleting " ": no such file or directory
|
| 2917 |
|
|
deleting "if"
|
| 2918 |
|
|
deleting " $IsCopy "
|
| 2919 |
|
|
deleting ""
|
| 2920 |
|
|
deleting " Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File" "$HDLModule""
|
| 2921 |
|
|
deleting " "
|
| 2922 |
|
|
ERROR: error deleting " ": no such file or directory
|
| 2923 |
|
|
deleting "__projnav/ednTOngd_tcl.rsp"
|
| 2924 |
|
|
deleting ""c:\blue71/_ngo""
|
| 2925 |
|
|
deleting "topbox.ngd"
|
| 2926 |
|
|
deleting "topbox_ngdbuild.nav"
|
| 2927 |
|
|
deleting "topbox.bld"
|
| 2928 |
|
|
deleting "tobox.ucf.untf"
|
| 2929 |
|
|
deleting "topbox.cmd_log"
|
| 2930 |
|
|
deleting "if"
|
| 2931 |
|
|
deleting " $IsCopy "
|
| 2932 |
|
|
deleting ""
|
| 2933 |
|
|
deleting " Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File" "$HDLModule""
|
| 2934 |
|
|
deleting " "
|
| 2935 |
|
|
ERROR: error deleting " ": no such file or directory
|
| 2936 |
|
|
deleting "__projnav/ednTOngd_tcl.rsp"
|
| 2937 |
|
|
deleting ""c:\blue71/_ngo""
|
| 2938 |
|
|
deleting "topbox.ngd"
|
| 2939 |
|
|
deleting "topbox_ngdbuild.nav"
|
| 2940 |
|
|
deleting "topbox.bld"
|
| 2941 |
|
|
deleting "tobox.ucf.untf"
|
| 2942 |
|
|
deleting "topbox.cmd_log"
|
| 2943 |
|
|
deleting "__projnav/maindcm_jhdparse_tcl.rsp"
|
| 2944 |
|
|
deleting "maindcm.v"
|
| 2945 |
|
|
deleting "xaw2verilog.log"
|
| 2946 |
|
|
deleting "topbox.lso"
|
| 2947 |
|
|
deleting "topbox_summary.html"
|
| 2948 |
|
|
deleting "topbox.syr"
|
| 2949 |
|
|
deleting "topbox.prj"
|
| 2950 |
|
|
deleting "topbox.sprj"
|
| 2951 |
|
|
deleting "topbox.ana"
|
| 2952 |
|
|
deleting "topbox.stx"
|
| 2953 |
|
|
deleting "topbox.cmd_log"
|
| 2954 |
|
|
deleting "topbox.ngc"
|
| 2955 |
|
|
deleting "topbox.ngr"
|
| 2956 |
|
|
deleting "__projnav/ednTOngd_tcl.rsp"
|
| 2957 |
|
|
deleting ""c:\blue71/_ngo""
|
| 2958 |
|
|
deleting "topbox.ngd"
|
| 2959 |
|
|
deleting "topbox_ngdbuild.nav"
|
| 2960 |
|
|
deleting "topbox.bld"
|
| 2961 |
|
|
deleting "tobox.ucf.untf"
|
| 2962 |
|
|
deleting "topbox.cmd_log"
|
| 2963 |
|
|
deleting "topbox_summary.html"
|
| 2964 |
|
|
deleting "topbox_map.ncd"
|
| 2965 |
|
|
deleting "topbox.ngm"
|
| 2966 |
|
|
deleting "topbox.pcf"
|
| 2967 |
|
|
deleting "topbox.nc1"
|
| 2968 |
|
|
deleting "topbox.mrp"
|
| 2969 |
|
|
deleting "topbox_map.mrp"
|
| 2970 |
|
|
deleting "topbox.mdf"
|
| 2971 |
|
|
deleting "topbox.cmd_log"
|
| 2972 |
|
|
deleting "topbox_map.ngm"
|
| 2973 |
|
|
deleting "__projnav/ncdTOtwr_tcl.rsp"
|
| 2974 |
|
|
deleting "topbox.twr"
|
| 2975 |
|
|
deleting "topbox.twx"
|
| 2976 |
|
|
deleting "topbox.tsi"
|
| 2977 |
|
|
deleting "topbox.cmd_log"
|
| 2978 |
|
|
deleting "topbox_summary.html"
|
| 2979 |
|
|
deleting "__projnav/nc1TOncd_tcl.rsp"
|
| 2980 |
|
|
deleting "topbox.ncd"
|
| 2981 |
|
|
deleting "topbox.par"
|
| 2982 |
|
|
deleting "topbox.pad"
|
| 2983 |
|
|
deleting "topbox_pad.txt"
|
| 2984 |
|
|
deleting "topbox_pad.csv"
|
| 2985 |
|
|
deleting "topbox.pad_txt"
|
| 2986 |
|
|
deleting "topbox.dly"
|
| 2987 |
|
|
deleting "reportgen.log"
|
| 2988 |
|
|
deleting "topbox.xpi"
|
| 2989 |
|
|
deleting "topbox.grf"
|
| 2990 |
|
|
deleting "topbox.itr"
|
| 2991 |
|
|
deleting "topbox_last_par.ncd"
|
| 2992 |
|
|
deleting "topbox.placed_ncd_tracker"
|
| 2993 |
|
|
deleting "topbox.routed_ncd_tracker"
|
| 2994 |
|
|
deleting "topbox.cmd_log"
|
| 2995 |
|
|
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
|
| 2996 |
|
|
deleting "__projnav/bitgen.rsp"
|
| 2997 |
|
|
deleting "bitgen.ut"
|
| 2998 |
|
|
deleting "topbox.ut"
|
| 2999 |
|
|
deleting "topbox.bgn"
|
| 3000 |
|
|
deleting "topbox.rbt"
|
| 3001 |
|
|
deleting "topbox.ll"
|
| 3002 |
|
|
deleting "topbox.msk"
|
| 3003 |
|
|
deleting "topbox.drc"
|
| 3004 |
|
|
deleting "topbox.nky"
|
| 3005 |
|
|
deleting "topbox.bit"
|
| 3006 |
|
|
deleting "topbox.bin"
|
| 3007 |
|
|
deleting "topbox.isc"
|
| 3008 |
|
|
deleting "topbox.cmd_log"
|
| 3009 |
|
|
deleting "topbox.prm"
|
| 3010 |
|
|
deleting "topbox.isc"
|
| 3011 |
|
|
deleting "topbox.svf"
|
| 3012 |
|
|
deleting "xilinx.sys"
|
| 3013 |
|
|
deleting "topbox.mcs"
|
| 3014 |
|
|
deleting "topbox.exo"
|
| 3015 |
|
|
deleting "topbox.hex"
|
| 3016 |
|
|
deleting "topbox.tek"
|
| 3017 |
|
|
deleting "topbox.dst"
|
| 3018 |
|
|
deleting "topbox.dst_compressed"
|
| 3019 |
|
|
deleting "topbox.mpm"
|
| 3020 |
|
|
deleting "_impact.cmd"
|
| 3021 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 3022 |
|
|
deleting "_impact.log"
|
| 3023 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 3024 |
|
|
deleting "__projnav/ednTOngd_tcl.rsp"
|
| 3025 |
|
|
deleting ""c:\blue71/_ngo""
|
| 3026 |
|
|
deleting "topbox.ngd"
|
| 3027 |
|
|
deleting "topbox_ngdbuild.nav"
|
| 3028 |
|
|
deleting "topbox.bld"
|
| 3029 |
|
|
deleting "tobox.ucf.untf"
|
| 3030 |
|
|
deleting "topbox.cmd_log"
|
| 3031 |
|
|
deleting "topbox_summary.html"
|
| 3032 |
|
|
deleting "topbox_map.ncd"
|
| 3033 |
|
|
deleting "topbox.ngm"
|
| 3034 |
|
|
deleting "topbox.pcf"
|
| 3035 |
|
|
deleting "topbox.nc1"
|
| 3036 |
|
|
deleting "topbox.mrp"
|
| 3037 |
|
|
deleting "topbox_map.mrp"
|
| 3038 |
|
|
deleting "topbox.mdf"
|
| 3039 |
|
|
deleting "topbox.cmd_log"
|
| 3040 |
|
|
deleting "topbox_map.ngm"
|
| 3041 |
|
|
deleting "__projnav/ncdTOtwr_tcl.rsp"
|
| 3042 |
|
|
deleting "topbox.twr"
|
| 3043 |
|
|
deleting "topbox.twx"
|
| 3044 |
|
|
deleting "topbox.tsi"
|
| 3045 |
|
|
deleting "topbox.cmd_log"
|
| 3046 |
|
|
deleting "topbox_summary.html"
|
| 3047 |
|
|
deleting "__projnav/nc1TOncd_tcl.rsp"
|
| 3048 |
|
|
deleting "topbox.ncd"
|
| 3049 |
|
|
deleting "topbox.par"
|
| 3050 |
|
|
deleting "topbox.pad"
|
| 3051 |
|
|
deleting "topbox_pad.txt"
|
| 3052 |
|
|
deleting "topbox_pad.csv"
|
| 3053 |
|
|
deleting "topbox.pad_txt"
|
| 3054 |
|
|
deleting "topbox.dly"
|
| 3055 |
|
|
deleting "reportgen.log"
|
| 3056 |
|
|
deleting "topbox.xpi"
|
| 3057 |
|
|
deleting "topbox.grf"
|
| 3058 |
|
|
deleting "topbox.itr"
|
| 3059 |
|
|
deleting "topbox_last_par.ncd"
|
| 3060 |
|
|
deleting "topbox.placed_ncd_tracker"
|
| 3061 |
|
|
deleting "topbox.routed_ncd_tracker"
|
| 3062 |
|
|
deleting "topbox.cmd_log"
|
| 3063 |
|
|
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
|
| 3064 |
|
|
deleting "__projnav/bitgen.rsp"
|
| 3065 |
|
|
deleting "bitgen.ut"
|
| 3066 |
|
|
deleting "topbox.ut"
|
| 3067 |
|
|
deleting "topbox.bgn"
|
| 3068 |
|
|
deleting "topbox.rbt"
|
| 3069 |
|
|
deleting "topbox.ll"
|
| 3070 |
|
|
deleting "topbox.msk"
|
| 3071 |
|
|
deleting "topbox.drc"
|
| 3072 |
|
|
deleting "topbox.nky"
|
| 3073 |
|
|
deleting "topbox.bit"
|
| 3074 |
|
|
deleting "topbox.bin"
|
| 3075 |
|
|
deleting "topbox.isc"
|
| 3076 |
|
|
deleting "topbox.cmd_log"
|
| 3077 |
|
|
deleting "topbox.prm"
|
| 3078 |
|
|
deleting "topbox.isc"
|
| 3079 |
|
|
deleting "topbox.svf"
|
| 3080 |
|
|
deleting "xilinx.sys"
|
| 3081 |
|
|
deleting "topbox.mcs"
|
| 3082 |
|
|
deleting "topbox.exo"
|
| 3083 |
|
|
deleting "topbox.hex"
|
| 3084 |
|
|
deleting "topbox.tek"
|
| 3085 |
|
|
deleting "topbox.dst"
|
| 3086 |
|
|
deleting "topbox.dst_compressed"
|
| 3087 |
|
|
deleting "topbox.mpm"
|
| 3088 |
|
|
deleting "_impact.cmd"
|
| 3089 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 3090 |
|
|
deleting "_impact.log"
|
| 3091 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 3092 |
|
|
deleting "__projnav/maindcm_jhdparse_tcl.rsp"
|
| 3093 |
|
|
deleting "maindcm.v"
|
| 3094 |
|
|
deleting "xaw2verilog.log"
|
| 3095 |
|
|
deleting "topbox.lso"
|
| 3096 |
|
|
deleting "topbox_summary.html"
|
| 3097 |
|
|
deleting "topbox.syr"
|
| 3098 |
|
|
deleting "topbox.prj"
|
| 3099 |
|
|
deleting "topbox.sprj"
|
| 3100 |
|
|
deleting "topbox.ana"
|
| 3101 |
|
|
deleting "topbox.stx"
|
| 3102 |
|
|
deleting "topbox.cmd_log"
|
| 3103 |
|
|
deleting "topbox.ngc"
|
| 3104 |
|
|
deleting "topbox.ngr"
|
| 3105 |
|
|
deleting "__projnav/ednTOngd_tcl.rsp"
|
| 3106 |
|
|
deleting ""c:\blue71/_ngo""
|
| 3107 |
|
|
deleting "topbox.ngd"
|
| 3108 |
|
|
deleting "topbox_ngdbuild.nav"
|
| 3109 |
|
|
deleting "topbox.bld"
|
| 3110 |
|
|
deleting "tobox.ucf.untf"
|
| 3111 |
|
|
deleting "topbox.cmd_log"
|
| 3112 |
|
|
deleting "topbox_summary.html"
|
| 3113 |
|
|
deleting "topbox_map.ncd"
|
| 3114 |
|
|
deleting "topbox.ngm"
|
| 3115 |
|
|
deleting "topbox.pcf"
|
| 3116 |
|
|
deleting "topbox.nc1"
|
| 3117 |
|
|
deleting "topbox.mrp"
|
| 3118 |
|
|
deleting "topbox_map.mrp"
|
| 3119 |
|
|
deleting "topbox.mdf"
|
| 3120 |
|
|
deleting "topbox.cmd_log"
|
| 3121 |
|
|
deleting "topbox_map.ngm"
|
| 3122 |
|
|
deleting "__projnav/ncdTOtwr_tcl.rsp"
|
| 3123 |
|
|
deleting "topbox.twr"
|
| 3124 |
|
|
deleting "topbox.twx"
|
| 3125 |
|
|
deleting "topbox.tsi"
|
| 3126 |
|
|
deleting "topbox.cmd_log"
|
| 3127 |
|
|
deleting "topbox_summary.html"
|
| 3128 |
|
|
deleting "__projnav/nc1TOncd_tcl.rsp"
|
| 3129 |
|
|
deleting "topbox.ncd"
|
| 3130 |
|
|
deleting "topbox.par"
|
| 3131 |
|
|
deleting "topbox.pad"
|
| 3132 |
|
|
deleting "topbox_pad.txt"
|
| 3133 |
|
|
deleting "topbox_pad.csv"
|
| 3134 |
|
|
deleting "topbox.pad_txt"
|
| 3135 |
|
|
deleting "topbox.dly"
|
| 3136 |
|
|
deleting "reportgen.log"
|
| 3137 |
|
|
deleting "topbox.xpi"
|
| 3138 |
|
|
deleting "topbox.grf"
|
| 3139 |
|
|
deleting "topbox.itr"
|
| 3140 |
|
|
deleting "topbox_last_par.ncd"
|
| 3141 |
|
|
deleting "topbox.placed_ncd_tracker"
|
| 3142 |
|
|
deleting "topbox.routed_ncd_tracker"
|
| 3143 |
|
|
deleting "topbox.cmd_log"
|
| 3144 |
|
|
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
|
| 3145 |
|
|
deleting "__projnav/bitgen.rsp"
|
| 3146 |
|
|
deleting "bitgen.ut"
|
| 3147 |
|
|
deleting "topbox.ut"
|
| 3148 |
|
|
deleting "topbox.bgn"
|
| 3149 |
|
|
deleting "topbox.rbt"
|
| 3150 |
|
|
deleting "topbox.ll"
|
| 3151 |
|
|
deleting "topbox.msk"
|
| 3152 |
|
|
deleting "topbox.drc"
|
| 3153 |
|
|
deleting "topbox.nky"
|
| 3154 |
|
|
deleting "topbox.bit"
|
| 3155 |
|
|
deleting "topbox.bin"
|
| 3156 |
|
|
deleting "topbox.isc"
|
| 3157 |
|
|
deleting "topbox.cmd_log"
|
| 3158 |
|
|
deleting "topbox.prm"
|
| 3159 |
|
|
deleting "topbox.isc"
|
| 3160 |
|
|
deleting "topbox.svf"
|
| 3161 |
|
|
deleting "xilinx.sys"
|
| 3162 |
|
|
deleting "topbox.mcs"
|
| 3163 |
|
|
deleting "topbox.exo"
|
| 3164 |
|
|
deleting "topbox.hex"
|
| 3165 |
|
|
deleting "topbox.tek"
|
| 3166 |
|
|
deleting "topbox.dst"
|
| 3167 |
|
|
deleting "topbox.dst_compressed"
|
| 3168 |
|
|
deleting "topbox.mpm"
|
| 3169 |
|
|
deleting "_impact.cmd"
|
| 3170 |
|
|
ERROR: error deleting "_impact.cmd": permission denied
|
| 3171 |
|
|
deleting "_impact.log"
|
| 3172 |
|
|
ERROR: error deleting "_impact.log": permission denied
|
| 3173 |
|
|
deleting "__projnav/ednTOngd_tcl.rsp"
|
| 3174 |
|
|
deleting ""c:\blue71/_ngo""
|
| 3175 |
|
|
deleting "topbox.ngd"
|
| 3176 |
|
|
deleting "topbox_ngdbuild.nav"
|
| 3177 |
|
|
deleting "topbox.bld"
|
| 3178 |
|
|
deleting "tobox.ucf.untf"
|
| 3179 |
|
|
deleting "topbox.cmd_log"
|
| 3180 |
|
|
deleting "topbox_summary.html"
|
| 3181 |
|
|
deleting "topbox_map.ncd"
|
| 3182 |
|
|
deleting "topbox.ngm"
|
| 3183 |
|
|
deleting "topbox.pcf"
|
| 3184 |
|
|
deleting "topbox.nc1"
|
| 3185 |
|
|
deleting "topbox.mrp"
|
| 3186 |
|
|
deleting "topbox_map.mrp"
|
| 3187 |
|
|
deleting "topbox.mdf"
|
| 3188 |
|
|
deleting "topbox.cmd_log"
|
| 3189 |
|
|
deleting "topbox_map.ngm"
|
| 3190 |
|
|
deleting "__projnav/ncdTOtwr_tcl.rsp"
|
| 3191 |
|
|
deleting "topbox.twr"
|
| 3192 |
|
|
deleting "topbox.twx"
|
| 3193 |
|
|
deleting "topbox.tsi"
|
| 3194 |
|
|
deleting "topbox.cmd_log"
|
| 3195 |
|
|
deleting "topbox_summary.html"
|
| 3196 |
|
|
deleting "__projnav/nc1TOncd_tcl.rsp"
|
| 3197 |
|
|
deleting "topbox.ncd"
|
| 3198 |
|
|
deleting "topbox.par"
|
| 3199 |
|
|
deleting "topbox.pad"
|
| 3200 |
|
|
deleting "topbox_pad.txt"
|
| 3201 |
|
|
deleting "topbox_pad.csv"
|
| 3202 |
|
|
deleting "topbox.pad_txt"
|
| 3203 |
|
|
deleting "topbox.dly"
|
| 3204 |
|
|
deleting "reportgen.log"
|
| 3205 |
|
|
deleting "topbox.xpi"
|
| 3206 |
|
|
deleting "topbox.grf"
|
| 3207 |
|
|
deleting "topbox.itr"
|
| 3208 |
|
|
deleting "topbox_last_par.ncd"
|
| 3209 |
|
|
deleting "topbox.placed_ncd_tracker"
|
| 3210 |
|
|
deleting "topbox.routed_ncd_tracker"
|
| 3211 |
|
|
deleting "topbox.cmd_log"
|
| 3212 |
|
|
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
|
| 3213 |
|
|
deleting "__projnav/bitgen.rsp"
|
| 3214 |
|
|
deleting "bitgen.ut"
|
| 3215 |
|
|
deleting "topbox.ut"
|
| 3216 |
|
|
deleting "topbox.bgn"
|
| 3217 |
|
|
deleting "topbox.rbt"
|
| 3218 |
|
|
deleting "topbox.ll"
|
| 3219 |
|
|
deleting "topbox.msk"
|
| 3220 |
|
|
deleting "topbox.drc"
|
| 3221 |
|
|
deleting "topbox.nky"
|
| 3222 |
|
|
deleting "topbox.bit"
|
| 3223 |
|
|
deleting "topbox.bin"
|
| 3224 |
|
|
deleting "topbox.isc"
|
| 3225 |
|
|
deleting "topbox.cmd_log"
|
| 3226 |
|
|
deleting "topbox_summary.html"
|
| 3227 |
|
|
deleting "topbox_map.ncd"
|
| 3228 |
|
|
deleting "topbox.ngm"
|
| 3229 |
|
|
deleting "topbox.pcf"
|
| 3230 |
|
|
deleting "topbox.nc1"
|
| 3231 |
|
|
deleting "topbox.mrp"
|
| 3232 |
|
|
deleting "topbox_map.mrp"
|
| 3233 |
|
|
deleting "topbox.mdf"
|
| 3234 |
|
|
deleting "topbox.cmd_log"
|
| 3235 |
|
|
deleting "topbox_map.ngm"
|
| 3236 |
|
|
deleting "__projnav/ncdTOtwr_tcl.rsp"
|
| 3237 |
|
|
deleting "topbox.twr"
|
| 3238 |
|
|
deleting "topbox.twx"
|
| 3239 |
|
|
deleting "topbox.tsi"
|
| 3240 |
|
|
deleting "topbox.cmd_log"
|
| 3241 |
|
|
deleting "topbox_summary.html"
|
| 3242 |
|
|
deleting "__projnav/nc1TOncd_tcl.rsp"
|
| 3243 |
|
|
deleting "topbox.ncd"
|
| 3244 |
|
|
deleting "topbox.par"
|
| 3245 |
|
|
deleting "topbox.pad"
|
| 3246 |
|
|
deleting "topbox_pad.txt"
|
| 3247 |
|
|
deleting "topbox_pad.csv"
|
| 3248 |
|
|
deleting "topbox.pad_txt"
|
| 3249 |
|
|
deleting "topbox.dly"
|
| 3250 |
|
|
deleting "reportgen.log"
|
| 3251 |
|
|
deleting "topbox.xpi"
|
| 3252 |
|
|
deleting "topbox.grf"
|
| 3253 |
|
|
deleting "topbox.itr"
|
| 3254 |
|
|
deleting "topbox_last_par.ncd"
|
| 3255 |
|
|
deleting "topbox.placed_ncd_tracker"
|
| 3256 |
|
|
deleting "topbox.routed_ncd_tracker"
|
| 3257 |
|
|
deleting "topbox.cmd_log"
|
| 3258 |
|
|
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
|
| 3259 |
|
|
deleting "__projnav/bitgen.rsp"
|
| 3260 |
|
|
deleting "bitgen.ut"
|
| 3261 |
|
|
deleting "topbox.ut"
|
| 3262 |
|
|
deleting "topbox.bgn"
|
| 3263 |
|
|
deleting "topbox.rbt"
|
| 3264 |
|
|
deleting "topbox.ll"
|
| 3265 |
|
|
deleting "topbox.msk"
|
| 3266 |
|
|
deleting "topbox.drc"
|
| 3267 |
|
|
deleting "topbox.nky"
|
| 3268 |
|
|
deleting "topbox.bit"
|
| 3269 |
|
|
deleting "topbox.bin"
|
| 3270 |
|
|
deleting "topbox.isc"
|
| 3271 |
|
|
deleting "topbox.cmd_log"
|
| 3272 |
|
|
deleting "topbox_summary.html"
|
| 3273 |
|
|
deleting "topbox_map.ncd"
|
| 3274 |
|
|
deleting "topbox.ngm"
|
| 3275 |
|
|
deleting "topbox.pcf"
|
| 3276 |
|
|
deleting "topbox.nc1"
|
| 3277 |
|
|
deleting "topbox.mrp"
|
| 3278 |
|
|
deleting "topbox_map.mrp"
|
| 3279 |
|
|
deleting "topbox.mdf"
|
| 3280 |
|
|
deleting "topbox.cmd_log"
|
| 3281 |
|
|
deleting "topbox_map.ngm"
|
| 3282 |
|
|
deleting "__projnav/ncdTOtwr_tcl.rsp"
|
| 3283 |
|
|
deleting "topbox.twr"
|
| 3284 |
|
|
deleting "topbox.twx"
|
| 3285 |
|
|
deleting "topbox.tsi"
|
| 3286 |
|
|
deleting "topbox.cmd_log"
|
| 3287 |
|
|
deleting "topbox_summary.html"
|
| 3288 |
|
|
deleting "__projnav/nc1TOncd_tcl.rsp"
|
| 3289 |
|
|
deleting "topbox.ncd"
|
| 3290 |
|
|
deleting "topbox.par"
|
| 3291 |
|
|
deleting "topbox.pad"
|
| 3292 |
|
|
deleting "topbox_pad.txt"
|
| 3293 |
|
|
deleting "topbox_pad.csv"
|
| 3294 |
|
|
deleting "topbox.pad_txt"
|
| 3295 |
|
|
deleting "topbox.dly"
|
| 3296 |
|
|
deleting "reportgen.log"
|
| 3297 |
|
|
deleting "topbox.xpi"
|
| 3298 |
|
|
deleting "topbox.grf"
|
| 3299 |
|
|
deleting "topbox.itr"
|
| 3300 |
|
|
deleting "topbox_last_par.ncd"
|
| 3301 |
|
|
deleting "topbox.placed_ncd_tracker"
|
| 3302 |
|
|
deleting "topbox.routed_ncd_tracker"
|
| 3303 |
|
|
deleting "topbox.cmd_log"
|
| 3304 |
|
|
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
|
| 3305 |
|
|
deleting "__projnav/bitgen.rsp"
|
| 3306 |
|
|
deleting "bitgen.ut"
|
| 3307 |
|
|
deleting "topbox.ut"
|
| 3308 |
|
|
deleting "topbox.bgn"
|
| 3309 |
|
|
deleting "topbox.rbt"
|
| 3310 |
|
|
deleting "topbox.ll"
|
| 3311 |
|
|
deleting "topbox.msk"
|
| 3312 |
|
|
deleting "topbox.drc"
|
| 3313 |
|
|
deleting "topbox.nky"
|
| 3314 |
|
|
deleting "topbox.bit"
|
| 3315 |
|
|
deleting "topbox.bin"
|
| 3316 |
|
|
deleting "topbox.isc"
|
| 3317 |
|
|
deleting "topbox.cmd_log"
|
| 3318 |
|
|
deleting "topbox.prj"
|
| 3319 |
|
|
deleting "topbox.prj"
|
| 3320 |
|
|
deleting "__projnav/topbox.xst"
|
| 3321 |
|
|
deleting "./xst"
|
| 3322 |
|
|
deleting "topbox.prj"
|
| 3323 |
|
|
deleting "topbox.prj"
|
| 3324 |
|
|
deleting "__projnav/topbox.xst"
|
| 3325 |
|
|
deleting "./xst"
|
| 3326 |
|
|
deleting "topbox.prj"
|
| 3327 |
|
|
deleting "topbox.prj"
|
| 3328 |
|
|
deleting "__projnav/topbox.xst"
|
| 3329 |
|
|
deleting "./xst"
|
| 3330 |
|
|
deleting "topbox.prj"
|
| 3331 |
|
|
deleting "topbox.prj"
|
| 3332 |
|
|
deleting "__projnav/topbox.xst"
|
| 3333 |
|
|
deleting "./xst"
|
| 3334 |
|
|
deleting "topbox.prj"
|
| 3335 |
|
|
deleting "topbox.prj"
|
| 3336 |
|
|
deleting "__projnav/topbox.xst"
|
| 3337 |
|
|
deleting "./xst"
|
| 3338 |
|
|
deleting "topbox.prj"
|
| 3339 |
|
|
deleting "topbox.prj"
|
| 3340 |
|
|
deleting "__projnav/topbox.xst"
|
| 3341 |
|
|
deleting "./xst"
|
| 3342 |
|
|
deleting "topbox.prj"
|
| 3343 |
|
|
deleting "topbox.prj"
|
| 3344 |
|
|
deleting "__projnav/topbox.xst"
|
| 3345 |
|
|
deleting "./xst"
|
| 3346 |
|
|
deleting "topbox.prj"
|
| 3347 |
|
|
deleting "topbox.prj"
|
| 3348 |
|
|
deleting "__projnav/topbox.xst"
|
| 3349 |
|
|
deleting "./xst"
|
| 3350 |
|
|
deleting "topbox.prj"
|
| 3351 |
|
|
deleting "topbox.prj"
|
| 3352 |
|
|
deleting "__projnav/topbox.xst"
|
| 3353 |
|
|
deleting "./xst"
|
| 3354 |
|
|
deleting "topbox.prj"
|
| 3355 |
|
|
deleting "topbox.prj"
|
| 3356 |
|
|
deleting "__projnav/topbox.xst"
|
| 3357 |
|
|
deleting "./xst"
|
| 3358 |
|
|
deleting "topbox.prj"
|
| 3359 |
|
|
deleting "topbox.prj"
|
| 3360 |
|
|
deleting "__projnav/topbox.xst"
|
| 3361 |
|
|
deleting "./xst"
|
| 3362 |
|
|
deleting "topbox.prj"
|
| 3363 |
|
|
deleting "topbox.prj"
|
| 3364 |
|
|
deleting "__projnav/topbox.xst"
|
| 3365 |
|
|
deleting "./xst"
|
| 3366 |
|
|
deleting "topbox.prj"
|
| 3367 |
|
|
deleting "topbox.prj"
|
| 3368 |
|
|
deleting "__projnav/topbox.xst"
|
| 3369 |
|
|
deleting "./xst"
|
| 3370 |
|
|
deleting "topbox.prj"
|
| 3371 |
|
|
deleting "topbox.prj"
|
| 3372 |
|
|
deleting "__projnav/topbox.xst"
|
| 3373 |
|
|
deleting "./xst"
|
| 3374 |
|
|
deleting "topbox.prj"
|
| 3375 |
|
|
deleting "topbox.prj"
|
| 3376 |
|
|
deleting "__projnav/topbox.xst"
|
| 3377 |
|
|
deleting "./xst"
|
| 3378 |
|
|
deleting "topbox.prj"
|
| 3379 |
|
|
deleting "topbox.prj"
|
| 3380 |
|
|
deleting "__projnav/topbox.xst"
|
| 3381 |
|
|
deleting "./xst"
|
| 3382 |
|
|
deleting "topbox.prj"
|
| 3383 |
|
|
deleting "topbox.prj"
|
| 3384 |
|
|
deleting "__projnav/topbox.xst"
|
| 3385 |
|
|
deleting "./xst"
|
| 3386 |
|
|
deleting "topbox.prj"
|
| 3387 |
|
|
deleting "topbox.prj"
|
| 3388 |
|
|
deleting "__projnav/topbox.xst"
|
| 3389 |
|
|
deleting "./xst"
|
| 3390 |
|
|
deleting "topbox.prj"
|
| 3391 |
|
|
deleting "topbox.prj"
|
| 3392 |
|
|
deleting "__projnav/topbox.xst"
|
| 3393 |
|
|
deleting "./xst"
|
| 3394 |
|
|
deleting "topbox.prj"
|
| 3395 |
|
|
deleting "topbox.prj"
|
| 3396 |
|
|
deleting "__projnav/topbox.xst"
|
| 3397 |
|
|
deleting "./xst"
|
| 3398 |
|
|
deleting "topbox.prj"
|
| 3399 |
|
|
deleting "topbox.prj"
|
| 3400 |
|
|
deleting "__projnav/topbox.xst"
|
| 3401 |
|
|
deleting "./xst"
|
| 3402 |
|
|
deleting "topbox.prj"
|
| 3403 |
|
|
deleting "topbox.prj"
|
| 3404 |
|
|
deleting "__projnav/topbox.xst"
|
| 3405 |
|
|
deleting "./xst"
|
| 3406 |
|
|
deleting "topbox.prj"
|
| 3407 |
|
|
deleting "topbox.prj"
|
| 3408 |
|
|
deleting "__projnav/topbox.xst"
|
| 3409 |
|
|
deleting "./xst"
|
| 3410 |
|
|
deleting "topbox.prj"
|
| 3411 |
|
|
deleting "topbox.prj"
|
| 3412 |
|
|
deleting "__projnav/topbox.xst"
|
| 3413 |
|
|
deleting "./xst"
|
| 3414 |
|
|
deleting "topbox.prj"
|
| 3415 |
|
|
deleting "topbox.prj"
|
| 3416 |
|
|
deleting "__projnav/topbox.xst"
|
| 3417 |
|
|
deleting "./xst"
|
| 3418 |
|
|
deleting "topbox.prj"
|
| 3419 |
|
|
deleting "topbox.prj"
|
| 3420 |
|
|
deleting "__projnav/topbox.xst"
|
| 3421 |
|
|
deleting "./xst"
|
| 3422 |
|
|
deleting "topbox.prj"
|
| 3423 |
|
|
deleting "topbox.prj"
|
| 3424 |
|
|
deleting "__projnav/topbox.xst"
|
| 3425 |
|
|
deleting "./xst"
|
| 3426 |
|
|
deleting "topbox.prj"
|
| 3427 |
|
|
deleting "topbox.prj"
|
| 3428 |
|
|
deleting "__projnav/topbox.xst"
|
| 3429 |
|
|
deleting "./xst"
|
| 3430 |
|
|
deleting "topbox.prj"
|
| 3431 |
|
|
deleting "topbox.prj"
|
| 3432 |
|
|
deleting "__projnav/topbox.xst"
|
| 3433 |
|
|
deleting "./xst"
|
| 3434 |
|
|
deleting "topbox.prj"
|
| 3435 |
|
|
deleting "topbox.prj"
|
| 3436 |
|
|
deleting "__projnav/topbox.xst"
|
| 3437 |
|
|
deleting "./xst"
|
| 3438 |
|
|
deleting "topbox.prj"
|
| 3439 |
|
|
deleting "__projnav/topbox.xst"
|
| 3440 |
|
|
deleting "./xst"
|
| 3441 |
|
|
deleting "topbox.prj"
|
| 3442 |
|
|
deleting "topbox.prj"
|
| 3443 |
|
|
deleting "__projnav/topbox.xst"
|
| 3444 |
|
|
deleting "./xst"
|
| 3445 |
|
|
deleting "topbox.prj"
|
| 3446 |
|
|
deleting "topbox.prj"
|
| 3447 |
|
|
deleting "__projnav/topbox.xst"
|
| 3448 |
|
|
deleting "./xst"
|
| 3449 |
|
|
deleting "topbox.prj"
|
| 3450 |
|
|
deleting "topbox.prj"
|
| 3451 |
|
|
deleting "__projnav/topbox.xst"
|
| 3452 |
|
|
deleting "./xst"
|
| 3453 |
|
|
deleting "topbox.prj"
|
| 3454 |
|
|
deleting "topbox.prj"
|
| 3455 |
|
|
deleting "__projnav/topbox.xst"
|
| 3456 |
|
|
deleting "./xst"
|
| 3457 |
|
|
deleting "topbox.prj"
|
| 3458 |
|
|
deleting "topbox.prj"
|
| 3459 |
|
|
deleting "__projnav/topbox.xst"
|
| 3460 |
|
|
deleting "./xst"
|
| 3461 |
|
|
deleting "topbox.prj"
|
| 3462 |
|
|
deleting "topbox.prj"
|
| 3463 |
|
|
deleting "__projnav/topbox.xst"
|
| 3464 |
|
|
deleting "./xst"
|
| 3465 |
|
|
deleting "topbox.prj"
|
| 3466 |
|
|
deleting "topbox.prj"
|
| 3467 |
|
|
deleting "__projnav/topbox.xst"
|
| 3468 |
|
|
deleting "./xst"
|
| 3469 |
|
|
deleting "topbox.prj"
|
| 3470 |
|
|
deleting "topbox.prj"
|
| 3471 |
|
|
deleting "__projnav/topbox.xst"
|
| 3472 |
|
|
deleting "./xst"
|
| 3473 |
|
|
deleting "topbox.prj"
|
| 3474 |
|
|
deleting "topbox.prj"
|
| 3475 |
|
|
deleting "__projnav/topbox.xst"
|
| 3476 |
|
|
deleting "./xst"
|
| 3477 |
|
|
deleting "topbox.prj"
|
| 3478 |
|
|
deleting "topbox.prj"
|
| 3479 |
|
|
deleting "__projnav/topbox.xst"
|
| 3480 |
|
|
deleting "./xst"
|
| 3481 |
|
|
deleting "topbox.prj"
|
| 3482 |
|
|
deleting "topbox.prj"
|
| 3483 |
|
|
deleting "__projnav/topbox.xst"
|
| 3484 |
|
|
deleting "./xst"
|
| 3485 |
|
|
deleting "topbox.prj"
|
| 3486 |
|
|
deleting "topbox.prj"
|
| 3487 |
|
|
deleting "__projnav/topbox.xst"
|
| 3488 |
|
|
deleting "./xst"
|
| 3489 |
|
|
deleting "__projnav/xblue.gfl"
|
| 3490 |
|
|
deleting "__projnav/xblue_flowplus.gfl"
|
| 3491 |
|
|
deleting xblue.dhp
|
| 3492 |
|
|
Finished cleaning up project
|
| 3493 |
|
|
|
| 3494 |
|
|
|
| 3495 |
|
|
Project Navigator Auto-Make Log File
|
| 3496 |
|
|
-------------------------------------
|
| 3497 |
|
|
|
| 3498 |
|
|
|
| 3499 |
|
|
|
| 3500 |
|
|
|
| 3501 |
|
|
Started process "View HDL Source".
|
| 3502 |
|
|
|
| 3503 |
|
|
xaw2verilog: Completed successfully
|
| 3504 |
|
|
|
| 3505 |
|
|
|
| 3506 |
|
|
|
| 3507 |
|
|
|
| 3508 |
|
|
|
| 3509 |
|
|
|
| 3510 |
|
|
|
| 3511 |
|
|
|
| 3512 |
|
|
|
| 3513 |
|
|
|
| 3514 |
|
|
Started process "Synthesize".
|
| 3515 |
|
|
|
| 3516 |
|
|
|
| 3517 |
|
|
=========================================================================
|
| 3518 |
|
|
* HDL Compilation *
|
| 3519 |
|
|
=========================================================================
|
| 3520 |
|
|
Compiling verilog file "io.v"
|
| 3521 |
|
|
Module compiled
|
| 3522 |
|
|
Module compiled
|
| 3523 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 3524 |
|
|
Module compiled
|
| 3525 |
|
|
Compiling verilog file "misc.v"
|
| 3526 |
|
|
Module compiled
|
| 3527 |
|
|
Module compiled
|
| 3528 |
|
|
Module compiled
|
| 3529 |
|
|
Module compiled
|
| 3530 |
|
|
Module compiled
|
| 3531 |
|
|
Module compiled
|
| 3532 |
|
|
Compiling verilog file "alu.v"
|
| 3533 |
|
|
Module compiled
|
| 3534 |
|
|
Compiling verilog file "switchsync.v"
|
| 3535 |
|
|
Module compiled
|
| 3536 |
|
|
Compiling verilog file "jkff.v"
|
| 3537 |
|
|
Module compiled
|
| 3538 |
|
|
Compiling verilog file "control.v"
|
| 3539 |
|
|
Module compiled
|
| 3540 |
|
|
Module compiled
|
| 3541 |
|
|
Compiling verilog file "maindcm.v"
|
| 3542 |
|
|
Module compiled
|
| 3543 |
|
|
Compiling verilog file "idecode.v"
|
| 3544 |
|
|
Module compiled
|
| 3545 |
|
|
Compiling verilog file "top.v"
|
| 3546 |
|
|
Module compiled
|
| 3547 |
|
|
Compiling verilog file "rcvr.v"
|
| 3548 |
|
|
Module compiled
|
| 3549 |
|
|
Compiling verilog file "txmit.v"
|
| 3550 |
|
|
Module compiled
|
| 3551 |
|
|
Compiling verilog file "uart.v"
|
| 3552 |
|
|
Module compiled
|
| 3553 |
|
|
Compiling verilog file "topbox.v"
|
| 3554 |
|
|
Module compiled
|
| 3555 |
|
|
No errors in compilation
|
| 3556 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 3557 |
|
|
|
| 3558 |
|
|
|
| 3559 |
|
|
=========================================================================
|
| 3560 |
|
|
* HDL Analysis *
|
| 3561 |
|
|
=========================================================================
|
| 3562 |
|
|
Analyzing top module .
|
| 3563 |
|
|
Module is correct for synthesis.
|
| 3564 |
|
|
|
| 3565 |
|
|
Analyzing module .
|
| 3566 |
|
|
Module is correct for synthesis.
|
| 3567 |
|
|
|
| 3568 |
|
|
Analyzing module .
|
| 3569 |
|
|
pClockFrequency = 50
|
| 3570 |
|
|
pRefreshFrequency = 100
|
| 3571 |
|
|
pUpperLimit = 125000
|
| 3572 |
|
|
pDividerCounterBits = 24
|
| 3573 |
|
|
Module is correct for synthesis.
|
| 3574 |
|
|
|
| 3575 |
|
|
Analyzing module .
|
| 3576 |
|
|
pInitialValue = 0
|
| 3577 |
|
|
pTimerWidth = 19
|
| 3578 |
|
|
pInitialTimerValue = 500000
|
| 3579 |
|
|
Module is correct for synthesis.
|
| 3580 |
|
|
|
| 3581 |
|
|
Analyzing module .
|
| 3582 |
|
|
Module is correct for synthesis.
|
| 3583 |
|
|
|
| 3584 |
|
|
Analyzing module .
|
| 3585 |
|
|
SIZE = 16
|
| 3586 |
|
|
Module is correct for synthesis.
|
| 3587 |
|
|
|
| 3588 |
|
|
Analyzing module .
|
| 3589 |
|
|
Module is correct for synthesis.
|
| 3590 |
|
|
|
| 3591 |
|
|
Analyzing module .
|
| 3592 |
|
|
SIZE = 12
|
| 3593 |
|
|
Module is correct for synthesis.
|
| 3594 |
|
|
|
| 3595 |
|
|
Analyzing module .
|
| 3596 |
|
|
Module is correct for synthesis.
|
| 3597 |
|
|
|
| 3598 |
|
|
Analyzing module .
|
| 3599 |
|
|
VALUE = 0000000000000001
|
| 3600 |
|
|
Module is correct for synthesis.
|
| 3601 |
|
|
|
| 3602 |
|
|
Analyzing module .
|
| 3603 |
|
|
Module is correct for synthesis.
|
| 3604 |
|
|
|
| 3605 |
|
|
Analyzing module .
|
| 3606 |
|
|
VALUE = 1111111111111111
|
| 3607 |
|
|
Module is correct for synthesis.
|
| 3608 |
|
|
|
| 3609 |
|
|
Analyzing module .
|
| 3610 |
|
|
Module is correct for synthesis.
|
| 3611 |
|
|
|
| 3612 |
|
|
Analyzing module .
|
| 3613 |
|
|
VALUE = 0000000000000000
|
| 3614 |
|
|
Module is correct for synthesis.
|
| 3615 |
|
|
|
| 3616 |
|
|
Analyzing module .
|
| 3617 |
|
|
Module is correct for synthesis.
|
| 3618 |
|
|
|
| 3619 |
|
|
Analyzing module .
|
| 3620 |
|
|
Module is correct for synthesis.
|
| 3621 |
|
|
|
| 3622 |
|
|
Analyzing module .
|
| 3623 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 3624 |
|
|
Module is correct for synthesis.
|
| 3625 |
|
|
|
| 3626 |
|
|
Analyzing module .
|
| 3627 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 3628 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 3629 |
|
|
Module is correct for synthesis.
|
| 3630 |
|
|
|
| 3631 |
|
|
Analyzing module .
|
| 3632 |
|
|
Module is correct for synthesis.
|
| 3633 |
|
|
|
| 3634 |
|
|
Analyzing module .
|
| 3635 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3636 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3637 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3638 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3639 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3640 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3641 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3642 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3643 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3644 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3645 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3646 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3647 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3648 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 3649 |
|
|
Module is correct for synthesis.
|
| 3650 |
|
|
|
| 3651 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 3652 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 3653 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 3654 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 3655 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 3656 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 3657 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 3658 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 3659 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 3660 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 3661 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 3662 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 3663 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 3664 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 3665 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 3666 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 3667 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 3668 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 3669 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 3670 |
|
|
Analyzing module .
|
| 3671 |
|
|
Module is correct for synthesis.
|
| 3672 |
|
|
|
| 3673 |
|
|
Analyzing module .
|
| 3674 |
|
|
XTAL_CLK = 35000000
|
| 3675 |
|
|
BAUD = 9600
|
| 3676 |
|
|
CLK_DIV = 113
|
| 3677 |
|
|
CW = 8
|
| 3678 |
|
|
Module is correct for synthesis.
|
| 3679 |
|
|
|
| 3680 |
|
|
Analyzing module .
|
| 3681 |
|
|
Module is correct for synthesis.
|
| 3682 |
|
|
|
| 3683 |
|
|
Analyzing module .
|
| 3684 |
|
|
Module is correct for synthesis.
|
| 3685 |
|
|
|
| 3686 |
|
|
|
| 3687 |
|
|
=========================================================================
|
| 3688 |
|
|
* HDL Synthesis *
|
| 3689 |
|
|
=========================================================================
|
| 3690 |
|
|
|
| 3691 |
|
|
Synthesizing Unit .
|
| 3692 |
|
|
Related source file is "txmit.v".
|
| 3693 |
|
|
Found 1-bit register for signal .
|
| 3694 |
|
|
Found 1-bit register for signal .
|
| 3695 |
|
|
Found 1-bit register for signal .
|
| 3696 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 3697 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 3698 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 3699 |
|
|
Found 1-bit register for signal .
|
| 3700 |
|
|
Found 1-bit register for signal .
|
| 3701 |
|
|
Found 4-bit up counter for signal .
|
| 3702 |
|
|
Found 4-bit up counter for signal .
|
| 3703 |
|
|
Found 8-bit register for signal .
|
| 3704 |
|
|
Found 8-bit register for signal .
|
| 3705 |
|
|
Summary:
|
| 3706 |
|
|
inferred 2 Counter(s).
|
| 3707 |
|
|
inferred 21 D-type flip-flop(s).
|
| 3708 |
|
|
inferred 2 Comparator(s).
|
| 3709 |
|
|
inferred 1 Multiplexer(s).
|
| 3710 |
|
|
Unit synthesized.
|
| 3711 |
|
|
|
| 3712 |
|
|
|
| 3713 |
|
|
Synthesizing Unit .
|
| 3714 |
|
|
Related source file is "rcvr.v".
|
| 3715 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 3716 |
|
|
Found 1-bit register for signal .
|
| 3717 |
|
|
Found 1-bit register for signal .
|
| 3718 |
|
|
Found 1-bit register for signal .
|
| 3719 |
|
|
Found 8-bit tristate buffer for signal .
|
| 3720 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 3721 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 3722 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 3723 |
|
|
Found 1-bit register for signal .
|
| 3724 |
|
|
Found 1-bit register for signal .
|
| 3725 |
|
|
Found 4-bit register for signal .
|
| 3726 |
|
|
Found 4-bit up counter for signal .
|
| 3727 |
|
|
Found 8-bit register for signal .
|
| 3728 |
|
|
Found 7-bit register for signal >.
|
| 3729 |
|
|
Found 1-bit register for signal .
|
| 3730 |
|
|
Found 1-bit register for signal .
|
| 3731 |
|
|
Summary:
|
| 3732 |
|
|
inferred 1 Counter(s).
|
| 3733 |
|
|
inferred 26 D-type flip-flop(s).
|
| 3734 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 3735 |
|
|
inferred 1 Comparator(s).
|
| 3736 |
|
|
inferred 1 Multiplexer(s).
|
| 3737 |
|
|
inferred 8 Tristate(s).
|
| 3738 |
|
|
Unit synthesized.
|
| 3739 |
|
|
|
| 3740 |
|
|
|
| 3741 |
|
|
Synthesizing Unit .
|
| 3742 |
|
|
Related source file is "jkff.v".
|
| 3743 |
|
|
Found 1-bit register for signal .
|
| 3744 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 3745 |
|
|
Summary:
|
| 3746 |
|
|
inferred 1 D-type flip-flop(s).
|
| 3747 |
|
|
inferred 1 Multiplexer(s).
|
| 3748 |
|
|
Unit synthesized.
|
| 3749 |
|
|
|
| 3750 |
|
|
|
| 3751 |
|
|
Synthesizing Unit .
|
| 3752 |
|
|
Related source file is "switchsync.v".
|
| 3753 |
|
|
Found 1-bit register for signal .
|
| 3754 |
|
|
Found 1-bit register for signal .
|
| 3755 |
|
|
Summary:
|
| 3756 |
|
|
inferred 2 D-type flip-flop(s).
|
| 3757 |
|
|
Unit synthesized.
|
| 3758 |
|
|
|
| 3759 |
|
|
|
| 3760 |
|
|
Synthesizing Unit .
|
| 3761 |
|
|
Related source file is "maindcm.v".
|
| 3762 |
|
|
Unit synthesized.
|
| 3763 |
|
|
|
| 3764 |
|
|
|
| 3765 |
|
|
Synthesizing Unit .
|
| 3766 |
|
|
Related source file is "control.v".
|
| 3767 |
|
|
Found 1-bit register for signal .
|
| 3768 |
|
|
Found 1-bit register for signal .
|
| 3769 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 3770 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 3771 |
|
|
Found 3-bit up counter for signal .
|
| 3772 |
|
|
Summary:
|
| 3773 |
|
|
inferred 1 Counter(s).
|
| 3774 |
|
|
inferred 2 D-type flip-flop(s).
|
| 3775 |
|
|
inferred 2 Multiplexer(s).
|
| 3776 |
|
|
Unit synthesized.
|
| 3777 |
|
|
|
| 3778 |
|
|
|
| 3779 |
|
|
Synthesizing Unit .
|
| 3780 |
|
|
Related source file is "misc.v".
|
| 3781 |
|
|
Found 16-bit tristate buffer for signal .
|
| 3782 |
|
|
Summary:
|
| 3783 |
|
|
inferred 16 Tristate(s).
|
| 3784 |
|
|
Unit synthesized.
|
| 3785 |
|
|
|
| 3786 |
|
|
|
| 3787 |
|
|
Synthesizing Unit .
|
| 3788 |
|
|
Related source file is "misc.v".
|
| 3789 |
|
|
Found 16-bit tristate buffer for signal .
|
| 3790 |
|
|
Summary:
|
| 3791 |
|
|
inferred 16 Tristate(s).
|
| 3792 |
|
|
Unit synthesized.
|
| 3793 |
|
|
|
| 3794 |
|
|
|
| 3795 |
|
|
Synthesizing Unit .
|
| 3796 |
|
|
Related source file is "misc.v".
|
| 3797 |
|
|
Found 16-bit tristate buffer for signal .
|
| 3798 |
|
|
Summary:
|
| 3799 |
|
|
inferred 16 Tristate(s).
|
| 3800 |
|
|
Unit synthesized.
|
| 3801 |
|
|
|
| 3802 |
|
|
|
| 3803 |
|
|
Synthesizing Unit .
|
| 3804 |
|
|
Related source file is "misc.v".
|
| 3805 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 3806 |
|
|
Found 16-bit tristate buffer for signal .
|
| 3807 |
|
|
Found 12-bit register for signal .
|
| 3808 |
|
|
Summary:
|
| 3809 |
|
|
inferred 12 D-type flip-flop(s).
|
| 3810 |
|
|
inferred 16 Tristate(s).
|
| 3811 |
|
|
Unit synthesized.
|
| 3812 |
|
|
|
| 3813 |
|
|
|
| 3814 |
|
|
Synthesizing Unit .
|
| 3815 |
|
|
Related source file is "idecode.v".
|
| 3816 |
|
|
Unit synthesized.
|
| 3817 |
|
|
|
| 3818 |
|
|
|
| 3819 |
|
|
Synthesizing Unit .
|
| 3820 |
|
|
Related source file is "control.v".
|
| 3821 |
|
|
Unit synthesized.
|
| 3822 |
|
|
|
| 3823 |
|
|
|
| 3824 |
|
|
Synthesizing Unit .
|
| 3825 |
|
|
Related source file is "alu.v".
|
| 3826 |
|
|
Found 16-bit tristate buffer for signal .
|
| 3827 |
|
|
Found 17-bit subtractor for signal <$AUX_108>.
|
| 3828 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 3829 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 3830 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 3831 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 3832 |
|
|
Summary:
|
| 3833 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 3834 |
|
|
inferred 16 Tristate(s).
|
| 3835 |
|
|
Unit synthesized.
|
| 3836 |
|
|
|
| 3837 |
|
|
|
| 3838 |
|
|
Synthesizing Unit .
|
| 3839 |
|
|
Related source file is "misc.v".
|
| 3840 |
|
|
Unit synthesized.
|
| 3841 |
|
|
|
| 3842 |
|
|
|
| 3843 |
|
|
Synthesizing Unit .
|
| 3844 |
|
|
Related source file is "misc.v".
|
| 3845 |
|
|
Unit synthesized.
|
| 3846 |
|
|
|
| 3847 |
|
|
|
| 3848 |
|
|
Synthesizing Unit .
|
| 3849 |
|
|
Related source file is "misc.v".
|
| 3850 |
|
|
Unit synthesized.
|
| 3851 |
|
|
|
| 3852 |
|
|
|
| 3853 |
|
|
Synthesizing Unit .
|
| 3854 |
|
|
Related source file is "misc.v".
|
| 3855 |
|
|
Unit synthesized.
|
| 3856 |
|
|
|
| 3857 |
|
|
|
| 3858 |
|
|
Synthesizing Unit .
|
| 3859 |
|
|
Related source file is "misc.v".
|
| 3860 |
|
|
Found 16-bit tristate buffer for signal .
|
| 3861 |
|
|
Found 16-bit register for signal .
|
| 3862 |
|
|
Summary:
|
| 3863 |
|
|
inferred 16 D-type flip-flop(s).
|
| 3864 |
|
|
inferred 16 Tristate(s).
|
| 3865 |
|
|
Unit synthesized.
|
| 3866 |
|
|
|
| 3867 |
|
|
|
| 3868 |
|
|
Synthesizing Unit .
|
| 3869 |
|
|
Related source file is "io.v".
|
| 3870 |
|
|
Found 1-bit register for signal .
|
| 3871 |
|
|
Found 1-bit register for signal .
|
| 3872 |
|
|
Found 1-bit register for signal .
|
| 3873 |
|
|
Found 1-bit register for signal .
|
| 3874 |
|
|
Found 1-bit register for signal .
|
| 3875 |
|
|
Found 1-bit register for signal .
|
| 3876 |
|
|
Found 19-bit down counter for signal .
|
| 3877 |
|
|
Found 1-bit register for signal .
|
| 3878 |
|
|
Found 1-bit xor2 for signal .
|
| 3879 |
|
|
Summary:
|
| 3880 |
|
|
inferred 1 Counter(s).
|
| 3881 |
|
|
inferred 7 D-type flip-flop(s).
|
| 3882 |
|
|
Unit synthesized.
|
| 3883 |
|
|
|
| 3884 |
|
|
|
| 3885 |
|
|
Synthesizing Unit .
|
| 3886 |
|
|
Related source file is "io.v".
|
| 3887 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 3888 |
|
|
Found 1-bit register for signal .
|
| 3889 |
|
|
Found 1-bit register for signal .
|
| 3890 |
|
|
Found 1-bit register for signal .
|
| 3891 |
|
|
Found 1-bit register for signal .
|
| 3892 |
|
|
Found 1-bit register for signal .
|
| 3893 |
|
|
Found 1-bit register for signal .
|
| 3894 |
|
|
Found 1-bit register for signal .
|
| 3895 |
|
|
Found 1-bit register for signal .
|
| 3896 |
|
|
Found 1-bit register for signal .
|
| 3897 |
|
|
Found 1-bit register for signal .
|
| 3898 |
|
|
Found 1-bit register for signal .
|
| 3899 |
|
|
Found 1-bit register for signal .
|
| 3900 |
|
|
Found 24-bit up counter for signal .
|
| 3901 |
|
|
Found 1-of-4 decoder for signal .
|
| 3902 |
|
|
Found 2-bit down counter for signal .
|
| 3903 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 3904 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 3905 |
|
|
Summary:
|
| 3906 |
|
|
inferred 1 ROM(s).
|
| 3907 |
|
|
inferred 2 Counter(s).
|
| 3908 |
|
|
inferred 12 D-type flip-flop(s).
|
| 3909 |
|
|
inferred 9 Multiplexer(s).
|
| 3910 |
|
|
inferred 1 Decoder(s).
|
| 3911 |
|
|
Unit synthesized.
|
| 3912 |
|
|
|
| 3913 |
|
|
|
| 3914 |
|
|
Synthesizing Unit .
|
| 3915 |
|
|
Related source file is "uart.v".
|
| 3916 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 3917 |
|
|
Found 1-bit register for signal .
|
| 3918 |
|
|
Found 8-bit up counter for signal .
|
| 3919 |
|
|
Found 1-bit register for signal .
|
| 3920 |
|
|
Summary:
|
| 3921 |
|
|
inferred 1 Counter(s).
|
| 3922 |
|
|
inferred 2 D-type flip-flop(s).
|
| 3923 |
|
|
inferred 1 Multiplexer(s).
|
| 3924 |
|
|
Unit synthesized.
|
| 3925 |
|
|
|
| 3926 |
|
|
|
| 3927 |
|
|
Synthesizing Unit .
|
| 3928 |
|
|
Related source file is "top.v".
|
| 3929 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 3930 |
|
|
Found 16-bit tristate buffer for signal .
|
| 3931 |
|
|
Found 1-bit register for signal .
|
| 3932 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 3933 |
|
|
Found 16-bit tristate buffer for signal .
|
| 3934 |
|
|
Found 1-bit register for signal .
|
| 3935 |
|
|
Found 1-bit register for signal .
|
| 3936 |
|
|
Found 1-bit register for signal .
|
| 3937 |
|
|
Summary:
|
| 3938 |
|
|
inferred 4 D-type flip-flop(s).
|
| 3939 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 3940 |
|
|
inferred 96 Tristate(s).
|
| 3941 |
|
|
Unit synthesized.
|
| 3942 |
|
|
|
| 3943 |
|
|
|
| 3944 |
|
|
Synthesizing Unit .
|
| 3945 |
|
|
Related source file is "FrontPanel.v".
|
| 3946 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 3947 |
|
|
Found finite state machine for signal .
|
| 3948 |
|
|
-----------------------------------------------------------------------
|
| 3949 |
|
|
| States | 6 |
|
| 3950 |
|
|
| Transitions | 6 |
|
| 3951 |
|
|
| Inputs | 0 |
|
| 3952 |
|
|
| Outputs | 12 |
|
| 3953 |
|
|
| Clock | clockin (rising_edge) |
|
| 3954 |
|
|
| Clock enable | select (positive) |
|
| 3955 |
|
|
| Reset | clear (positive) |
|
| 3956 |
|
|
| Reset type | synchronous |
|
| 3957 |
|
|
| Reset State | 000001 |
|
| 3958 |
|
|
| Encoding | automatic |
|
| 3959 |
|
|
| Implementation | LUT |
|
| 3960 |
|
|
-----------------------------------------------------------------------
|
| 3961 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 3962 |
|
|
Found 4-bit register for signal .
|
| 3963 |
|
|
Found 16-bit register for signal .
|
| 3964 |
|
|
Summary:
|
| 3965 |
|
|
inferred 1 Finite State Machine(s).
|
| 3966 |
|
|
inferred 16 D-type flip-flop(s).
|
| 3967 |
|
|
inferred 16 Multiplexer(s).
|
| 3968 |
|
|
Unit synthesized.
|
| 3969 |
|
|
|
| 3970 |
|
|
|
| 3971 |
|
|
Synthesizing Unit .
|
| 3972 |
|
|
Related source file is "topbox.v".
|
| 3973 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 3974 |
|
|
Found 16-bit tristate buffer for signal .
|
| 3975 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 3976 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 3977 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 3978 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 3979 |
|
|
Found 4-bit register for signal .
|
| 3980 |
|
|
Found 1-bit register for signal .
|
| 3981 |
|
|
Found 1-bit register for signal .
|
| 3982 |
|
|
Found 16-bit register for signal .
|
| 3983 |
|
|
Summary:
|
| 3984 |
|
|
inferred 22 D-type flip-flop(s).
|
| 3985 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 3986 |
|
|
inferred 6 Multiplexer(s).
|
| 3987 |
|
|
inferred 48 Tristate(s).
|
| 3988 |
|
|
Unit synthesized.
|
| 3989 |
|
|
|
| 3990 |
|
|
|
| 3991 |
|
|
=========================================================================
|
| 3992 |
|
|
* Advanced HDL Synthesis *
|
| 3993 |
|
|
=========================================================================
|
| 3994 |
|
|
|
| 3995 |
|
|
Advanced RAM inference ...
|
| 3996 |
|
|
Advanced multiplier inference ...
|
| 3997 |
|
|
Advanced Registered AddSub inference ...
|
| 3998 |
|
|
Analyzing FSM for best encoding.
|
| 3999 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 4000 |
|
|
--------------------
|
| 4001 |
|
|
State | Encoding
|
| 4002 |
|
|
--------------------
|
| 4003 |
|
|
000001 | 100000
|
| 4004 |
|
|
000010 | 010000
|
| 4005 |
|
|
000100 | 001000
|
| 4006 |
|
|
001000 | 000100
|
| 4007 |
|
|
010000 | 000010
|
| 4008 |
|
|
100000 | 000001
|
| 4009 |
|
|
--------------------
|
| 4010 |
|
|
Dynamic shift register inference ...
|
| 4011 |
|
|
|
| 4012 |
|
|
=========================================================================
|
| 4013 |
|
|
HDL Synthesis Report
|
| 4014 |
|
|
|
| 4015 |
|
|
Macro Statistics
|
| 4016 |
|
|
# FSMs : 1
|
| 4017 |
|
|
# ROMs : 1
|
| 4018 |
|
|
16x7-bit ROM : 1
|
| 4019 |
|
|
# Adders/Subtractors : 5
|
| 4020 |
|
|
12-bit adder carry out : 1
|
| 4021 |
|
|
16-bit adder carry out : 1
|
| 4022 |
|
|
17-bit subtractor : 1
|
| 4023 |
|
|
4-bit adder : 2
|
| 4024 |
|
|
# Counters : 10
|
| 4025 |
|
|
19-bit down counter : 3
|
| 4026 |
|
|
2-bit down counter : 1
|
| 4027 |
|
|
24-bit up counter : 1
|
| 4028 |
|
|
3-bit up counter : 1
|
| 4029 |
|
|
4-bit up counter : 3
|
| 4030 |
|
|
8-bit up counter : 1
|
| 4031 |
|
|
# Registers : 138
|
| 4032 |
|
|
1-bit register : 125
|
| 4033 |
|
|
12-bit register : 4
|
| 4034 |
|
|
16-bit register : 4
|
| 4035 |
|
|
4-bit register : 3
|
| 4036 |
|
|
8-bit register : 2
|
| 4037 |
|
|
# Comparators : 3
|
| 4038 |
|
|
4-bit comparator greater : 2
|
| 4039 |
|
|
4-bit comparator less : 1
|
| 4040 |
|
|
# Multiplexers : 15
|
| 4041 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 4042 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 4043 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 4044 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 4045 |
|
|
# Decoders : 1
|
| 4046 |
|
|
1-of-4 decoder : 1
|
| 4047 |
|
|
# Tristates : 97
|
| 4048 |
|
|
1-bit tristate buffer : 80
|
| 4049 |
|
|
16-bit tristate buffer : 16
|
| 4050 |
|
|
8-bit tristate buffer : 1
|
| 4051 |
|
|
# Xors : 6
|
| 4052 |
|
|
1-bit xor2 : 5
|
| 4053 |
|
|
16-bit xor2 : 1
|
| 4054 |
|
|
|
| 4055 |
|
|
=========================================================================
|
| 4056 |
|
|
|
| 4057 |
|
|
=========================================================================
|
| 4058 |
|
|
* Low Level Synthesis *
|
| 4059 |
|
|
=========================================================================
|
| 4060 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4061 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4062 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4063 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 4064 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 4065 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 4066 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 4067 |
|
|
|
| 4068 |
|
|
Optimizing unit ...
|
| 4069 |
|
|
|
| 4070 |
|
|
Optimizing unit ...
|
| 4071 |
|
|
|
| 4072 |
|
|
Optimizing unit ...
|
| 4073 |
|
|
|
| 4074 |
|
|
Optimizing unit ...
|
| 4075 |
|
|
|
| 4076 |
|
|
Optimizing unit ...
|
| 4077 |
|
|
|
| 4078 |
|
|
Optimizing unit ...
|
| 4079 |
|
|
|
| 4080 |
|
|
Optimizing unit ...
|
| 4081 |
|
|
|
| 4082 |
|
|
Optimizing unit ...
|
| 4083 |
|
|
|
| 4084 |
|
|
Optimizing unit ...
|
| 4085 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 4086 |
|
|
|
| 4087 |
|
|
Mapping all equations...
|
| 4088 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4089 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4090 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4091 |
|
|
Building and optimizing final netlist ...
|
| 4092 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
|
| 4093 |
|
|
FlipFlop CPU/IR/regvalue_0 has been replicated 3 time(s)
|
| 4094 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
|
| 4095 |
|
|
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
|
| 4096 |
|
|
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
|
| 4097 |
|
|
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
|
| 4098 |
|
|
FlipFlop CPU/IR/regvalue_15 has been replicated 1 time(s)
|
| 4099 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
|
| 4100 |
|
|
FlipFlop CPU/IR/regvalue_4 has been replicated 1 time(s)
|
| 4101 |
|
|
FlipFlop CPU/IR/regvalue_6 has been replicated 1 time(s)
|
| 4102 |
|
|
FlipFlop CPU/ctl/sim/counter_0 has been replicated 4 time(s)
|
| 4103 |
|
|
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
|
| 4104 |
|
|
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
|
| 4105 |
|
|
FlipFlop loadnow has been replicated 2 time(s)
|
| 4106 |
|
|
|
| 4107 |
|
|
=========================================================================
|
| 4108 |
|
|
* Final Report *
|
| 4109 |
|
|
=========================================================================
|
| 4110 |
|
|
|
| 4111 |
|
|
Device utilization summary:
|
| 4112 |
|
|
---------------------------
|
| 4113 |
|
|
|
| 4114 |
|
|
Selected Device : 3s200ft256-4
|
| 4115 |
|
|
|
| 4116 |
|
|
Number of Slices: 611 out of 1920 31%
|
| 4117 |
|
|
Number of Slice Flip Flops: 393 out of 3840 10%
|
| 4118 |
|
|
Number of 4 input LUTs: 1081 out of 3840 28%
|
| 4119 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 4120 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 4121 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 4122 |
|
|
|
| 4123 |
|
|
|
| 4124 |
|
|
=========================================================================
|
| 4125 |
|
|
TIMING REPORT
|
| 4126 |
|
|
|
| 4127 |
|
|
|
| 4128 |
|
|
Clock Information:
|
| 4129 |
|
|
------------------
|
| 4130 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 4131 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 4132 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 4133 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 393 |
|
| 4134 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 4135 |
|
|
|
| 4136 |
|
|
Timing Summary:
|
| 4137 |
|
|
---------------
|
| 4138 |
|
|
Speed Grade: -4
|
| 4139 |
|
|
|
| 4140 |
|
|
Minimum period: 14.217ns (Maximum Frequency: 70.338MHz)
|
| 4141 |
|
|
Minimum input arrival time before clock: 10.576ns
|
| 4142 |
|
|
Maximum output required time after clock: 24.383ns
|
| 4143 |
|
|
Maximum combinational path delay: 14.555ns
|
| 4144 |
|
|
|
| 4145 |
|
|
=========================================================================
|
| 4146 |
|
|
|
| 4147 |
|
|
|
| 4148 |
|
|
|
| 4149 |
|
|
|
| 4150 |
|
|
Started process "Translate".
|
| 4151 |
|
|
|
| 4152 |
|
|
|
| 4153 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -aul -p
|
| 4154 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 4155 |
|
|
|
| 4156 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 4157 |
|
|
|
| 4158 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 4159 |
|
|
|
| 4160 |
|
|
Checking timing specifications ...
|
| 4161 |
|
|
Checking expanded design ...
|
| 4162 |
|
|
|
| 4163 |
|
|
NGDBUILD Design Results Summary:
|
| 4164 |
|
|
Number of errors: 0
|
| 4165 |
|
|
Number of warnings: 0
|
| 4166 |
|
|
|
| 4167 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 4168 |
|
|
|
| 4169 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 4170 |
|
|
|
| 4171 |
|
|
NGDBUILD done.
|
| 4172 |
|
|
|
| 4173 |
|
|
|
| 4174 |
|
|
|
| 4175 |
|
|
|
| 4176 |
|
|
Started process "Map".
|
| 4177 |
|
|
|
| 4178 |
|
|
Using target part "3s200ft256-4".
|
| 4179 |
|
|
Mapping design into LUTs...
|
| 4180 |
|
|
Running directed packing...
|
| 4181 |
|
|
Running delay-based LUT packing...
|
| 4182 |
|
|
Running related packing...
|
| 4183 |
|
|
|
| 4184 |
|
|
Design Summary:
|
| 4185 |
|
|
Number of errors: 0
|
| 4186 |
|
|
Number of warnings: 5
|
| 4187 |
|
|
Logic Utilization:
|
| 4188 |
|
|
Number of Slice Flip Flops: 367 out of 3,840 9%
|
| 4189 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 4190 |
|
|
Logic Distribution:
|
| 4191 |
|
|
Number of occupied Slices: 694 out of 1,920 36%
|
| 4192 |
|
|
Number of Slices containing only related logic: 694 out of 694 100%
|
| 4193 |
|
|
Number of Slices containing unrelated logic: 0 out of 694 0%
|
| 4194 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 4195 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 4196 |
|
|
Number used as logic: 1,131
|
| 4197 |
|
|
Number used as a route-thru: 4
|
| 4198 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 4199 |
|
|
IOB Flip Flops: 26
|
| 4200 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 4201 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 4202 |
|
|
|
| 4203 |
|
|
Total equivalent gate count for design: 17,815
|
| 4204 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 4205 |
|
|
Peak Memory Usage: 113 MB
|
| 4206 |
|
|
|
| 4207 |
|
|
NOTES:
|
| 4208 |
|
|
|
| 4209 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 4210 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 4211 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 4212 |
|
|
the best timing performance.
|
| 4213 |
|
|
|
| 4214 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 4215 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 4216 |
|
|
related logic packing.
|
| 4217 |
|
|
|
| 4218 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 4219 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 4220 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 4221 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 4222 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 4223 |
|
|
of your design.
|
| 4224 |
|
|
|
| 4225 |
|
|
Mapping completed.
|
| 4226 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 4227 |
|
|
|
| 4228 |
|
|
|
| 4229 |
|
|
|
| 4230 |
|
|
|
| 4231 |
|
|
Started process "Place & Route".
|
| 4232 |
|
|
|
| 4233 |
|
|
|
| 4234 |
|
|
|
| 4235 |
|
|
|
| 4236 |
|
|
Constraints file: topbox.pcf.
|
| 4237 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 4238 |
|
|
C:/Xilinx71.
|
| 4239 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 4240 |
|
|
|
| 4241 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 4242 |
|
|
Celsius)
|
| 4243 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 4244 |
|
|
|
| 4245 |
|
|
|
| 4246 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 4247 |
|
|
|
| 4248 |
|
|
|
| 4249 |
|
|
Device Utilization Summary:
|
| 4250 |
|
|
|
| 4251 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 4252 |
|
|
Number of DCMs 1 out of 4 25%
|
| 4253 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 4254 |
|
|
Number of LOCed IOBs 6 out of 74 8%
|
| 4255 |
|
|
|
| 4256 |
|
|
Number of Slices 694 out of 1920 36%
|
| 4257 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 4258 |
|
|
|
| 4259 |
|
|
|
| 4260 |
|
|
|
| 4261 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 4262 |
|
|
Placer effort level (-pl): Standard (set by user)
|
| 4263 |
|
|
Placer cost table entry (-t): 1
|
| 4264 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 4265 |
|
|
|
| 4266 |
|
|
|
| 4267 |
|
|
Starting Placer
|
| 4268 |
|
|
|
| 4269 |
|
|
Phase 1.1
|
| 4270 |
|
|
Phase 1.1 (Checksum:98af6c) REAL time: 1 secs
|
| 4271 |
|
|
|
| 4272 |
|
|
Phase 2.31
|
| 4273 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
|
| 4274 |
|
|
|
| 4275 |
|
|
Phase 3.2
|
| 4276 |
|
|
.
|
| 4277 |
|
|
|
| 4278 |
|
|
|
| 4279 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs
|
| 4280 |
|
|
|
| 4281 |
|
|
Phase 4.3
|
| 4282 |
|
|
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs
|
| 4283 |
|
|
|
| 4284 |
|
|
Phase 5.5
|
| 4285 |
|
|
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs
|
| 4286 |
|
|
|
| 4287 |
|
|
Phase 6.8
|
| 4288 |
|
|
......................................
|
| 4289 |
|
|
Phase 6.8 (Checksum:a92ff3) REAL time: 1 secs
|
| 4290 |
|
|
|
| 4291 |
|
|
Phase 7.5
|
| 4292 |
|
|
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs
|
| 4293 |
|
|
|
| 4294 |
|
|
Phase 8.18
|
| 4295 |
|
|
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs
|
| 4296 |
|
|
|
| 4297 |
|
|
Phase 9.5
|
| 4298 |
|
|
Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs
|
| 4299 |
|
|
|
| 4300 |
|
|
Writing design to file topbox.ncd
|
| 4301 |
|
|
|
| 4302 |
|
|
|
| 4303 |
|
|
Total REAL time to Placer completion: 2 secs
|
| 4304 |
|
|
Total CPU time to Placer completion: 2 secs
|
| 4305 |
|
|
|
| 4306 |
|
|
Starting Router
|
| 4307 |
|
|
|
| 4308 |
|
|
Phase 1: 4717 unrouted; REAL time: 2 secs
|
| 4309 |
|
|
|
| 4310 |
|
|
Phase 2: 4442 unrouted; REAL time: 2 secs
|
| 4311 |
|
|
|
| 4312 |
|
|
Phase 3: 2150 unrouted; REAL time: 3 secs
|
| 4313 |
|
|
|
| 4314 |
|
|
Phase 4: 0 unrouted; REAL time: 4 secs
|
| 4315 |
|
|
|
| 4316 |
|
|
|
| 4317 |
|
|
Total REAL time to Router completion: 4 secs
|
| 4318 |
|
|
Total CPU time to Router completion: 4 secs
|
| 4319 |
|
|
|
| 4320 |
|
|
Generating "PAR" statistics.
|
| 4321 |
|
|
|
| 4322 |
|
|
**************************
|
| 4323 |
|
|
Generating Clock Report
|
| 4324 |
|
|
**************************
|
| 4325 |
|
|
|
| 4326 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 4327 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 4328 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 4329 |
|
|
| clk | BUFGMUX0| No | 255 | 0.042 | 1.052 |
|
| 4330 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 4331 |
|
|
|
| 4332 |
|
|
Generating Pad Report.
|
| 4333 |
|
|
|
| 4334 |
|
|
All signals are completely routed.
|
| 4335 |
|
|
|
| 4336 |
|
|
Total REAL time to PAR completion: 4 secs
|
| 4337 |
|
|
Total CPU time to PAR completion: 4 secs
|
| 4338 |
|
|
|
| 4339 |
|
|
Peak Memory Usage: 83 MB
|
| 4340 |
|
|
|
| 4341 |
|
|
Placement: Completed - No errors found.
|
| 4342 |
|
|
Routing: Completed - No errors found.
|
| 4343 |
|
|
|
| 4344 |
|
|
Number of error messages: 0
|
| 4345 |
|
|
Number of warning messages: 0
|
| 4346 |
|
|
Number of info messages: 1
|
| 4347 |
|
|
|
| 4348 |
|
|
Writing design to file topbox.ncd
|
| 4349 |
|
|
|
| 4350 |
|
|
|
| 4351 |
|
|
|
| 4352 |
|
|
PAR done!
|
| 4353 |
|
|
|
| 4354 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 4355 |
|
|
|
| 4356 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 4357 |
|
|
C:/Xilinx71.
|
| 4358 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 4359 |
|
|
|
| 4360 |
|
|
Analysis completed Sun Sep 24 10:28:03 2006
|
| 4361 |
|
|
--------------------------------------------------------------------------------
|
| 4362 |
|
|
|
| 4363 |
|
|
Generating Report ...
|
| 4364 |
|
|
|
| 4365 |
|
|
Number of warnings: 0
|
| 4366 |
|
|
Total time: 2 secs
|
| 4367 |
|
|
|
| 4368 |
|
|
|
| 4369 |
|
|
|
| 4370 |
|
|
|
| 4371 |
|
|
|
| 4372 |
|
|
|
| 4373 |
|
|
|
| 4374 |
|
|
Started process "Generate Programming File".
|
| 4375 |
|
|
|
| 4376 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 4377 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 4378 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 4379 |
|
|
Interactive Data Sheet.
|
| 4380 |
|
|
|
| 4381 |
|
|
|
| 4382 |
|
|
Project Navigator Auto-Make Log File
|
| 4383 |
|
|
-------------------------------------
|
| 4384 |
|
|
|
| 4385 |
|
|
|
| 4386 |
|
|
|
| 4387 |
|
|
|
| 4388 |
|
|
Started process "Synthesize".
|
| 4389 |
|
|
|
| 4390 |
|
|
|
| 4391 |
|
|
=========================================================================
|
| 4392 |
|
|
* HDL Compilation *
|
| 4393 |
|
|
=========================================================================
|
| 4394 |
|
|
Compiling verilog file "io.v"
|
| 4395 |
|
|
Module compiled
|
| 4396 |
|
|
Module compiled
|
| 4397 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 4398 |
|
|
Module compiled
|
| 4399 |
|
|
Compiling verilog file "misc.v"
|
| 4400 |
|
|
Module compiled
|
| 4401 |
|
|
Module compiled
|
| 4402 |
|
|
Module compiled
|
| 4403 |
|
|
Module compiled
|
| 4404 |
|
|
Module compiled
|
| 4405 |
|
|
Module compiled
|
| 4406 |
|
|
Compiling verilog file "alu.v"
|
| 4407 |
|
|
Module compiled
|
| 4408 |
|
|
Compiling verilog file "switchsync.v"
|
| 4409 |
|
|
Module compiled
|
| 4410 |
|
|
Compiling verilog file "jkff.v"
|
| 4411 |
|
|
Module compiled
|
| 4412 |
|
|
Compiling verilog file "control.v"
|
| 4413 |
|
|
Module compiled
|
| 4414 |
|
|
Module compiled
|
| 4415 |
|
|
Compiling verilog file "maindcm.v"
|
| 4416 |
|
|
Module compiled
|
| 4417 |
|
|
Compiling verilog file "idecode.v"
|
| 4418 |
|
|
Module compiled
|
| 4419 |
|
|
Compiling verilog file "top.v"
|
| 4420 |
|
|
Module compiled
|
| 4421 |
|
|
Compiling verilog file "rcvr.v"
|
| 4422 |
|
|
Module compiled
|
| 4423 |
|
|
Compiling verilog file "txmit.v"
|
| 4424 |
|
|
Module compiled
|
| 4425 |
|
|
Compiling verilog file "uart.v"
|
| 4426 |
|
|
Module compiled
|
| 4427 |
|
|
Compiling verilog file "topbox.v"
|
| 4428 |
|
|
Module compiled
|
| 4429 |
|
|
No errors in compilation
|
| 4430 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 4431 |
|
|
|
| 4432 |
|
|
|
| 4433 |
|
|
=========================================================================
|
| 4434 |
|
|
* HDL Analysis *
|
| 4435 |
|
|
=========================================================================
|
| 4436 |
|
|
Analyzing top module .
|
| 4437 |
|
|
Module is correct for synthesis.
|
| 4438 |
|
|
|
| 4439 |
|
|
Analyzing module .
|
| 4440 |
|
|
Module is correct for synthesis.
|
| 4441 |
|
|
|
| 4442 |
|
|
Analyzing module .
|
| 4443 |
|
|
pClockFrequency = 50
|
| 4444 |
|
|
pRefreshFrequency = 100
|
| 4445 |
|
|
pUpperLimit = 125000
|
| 4446 |
|
|
pDividerCounterBits = 24
|
| 4447 |
|
|
Module is correct for synthesis.
|
| 4448 |
|
|
|
| 4449 |
|
|
Analyzing module .
|
| 4450 |
|
|
pInitialValue = 0
|
| 4451 |
|
|
pTimerWidth = 19
|
| 4452 |
|
|
pInitialTimerValue = 500000
|
| 4453 |
|
|
Module is correct for synthesis.
|
| 4454 |
|
|
|
| 4455 |
|
|
Analyzing module .
|
| 4456 |
|
|
Module is correct for synthesis.
|
| 4457 |
|
|
|
| 4458 |
|
|
Analyzing module .
|
| 4459 |
|
|
SIZE = 16
|
| 4460 |
|
|
Module is correct for synthesis.
|
| 4461 |
|
|
|
| 4462 |
|
|
Analyzing module .
|
| 4463 |
|
|
Module is correct for synthesis.
|
| 4464 |
|
|
|
| 4465 |
|
|
Analyzing module .
|
| 4466 |
|
|
SIZE = 12
|
| 4467 |
|
|
Module is correct for synthesis.
|
| 4468 |
|
|
|
| 4469 |
|
|
Analyzing module .
|
| 4470 |
|
|
Module is correct for synthesis.
|
| 4471 |
|
|
|
| 4472 |
|
|
Analyzing module .
|
| 4473 |
|
|
VALUE = 0000000000000001
|
| 4474 |
|
|
Module is correct for synthesis.
|
| 4475 |
|
|
|
| 4476 |
|
|
Analyzing module .
|
| 4477 |
|
|
Module is correct for synthesis.
|
| 4478 |
|
|
|
| 4479 |
|
|
Analyzing module .
|
| 4480 |
|
|
VALUE = 1111111111111111
|
| 4481 |
|
|
Module is correct for synthesis.
|
| 4482 |
|
|
|
| 4483 |
|
|
Analyzing module .
|
| 4484 |
|
|
Module is correct for synthesis.
|
| 4485 |
|
|
|
| 4486 |
|
|
Analyzing module .
|
| 4487 |
|
|
VALUE = 0000000000000000
|
| 4488 |
|
|
Module is correct for synthesis.
|
| 4489 |
|
|
|
| 4490 |
|
|
Analyzing module .
|
| 4491 |
|
|
Module is correct for synthesis.
|
| 4492 |
|
|
|
| 4493 |
|
|
Analyzing module .
|
| 4494 |
|
|
Module is correct for synthesis.
|
| 4495 |
|
|
|
| 4496 |
|
|
Analyzing module .
|
| 4497 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 4498 |
|
|
Module is correct for synthesis.
|
| 4499 |
|
|
|
| 4500 |
|
|
Analyzing module .
|
| 4501 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 4502 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 4503 |
|
|
Module is correct for synthesis.
|
| 4504 |
|
|
|
| 4505 |
|
|
Analyzing module .
|
| 4506 |
|
|
Module is correct for synthesis.
|
| 4507 |
|
|
|
| 4508 |
|
|
Analyzing module .
|
| 4509 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4510 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4511 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4512 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4513 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4514 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4515 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4516 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4517 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4518 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4519 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4520 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4521 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4522 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 4523 |
|
|
Module is correct for synthesis.
|
| 4524 |
|
|
|
| 4525 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 4526 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 4527 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 4528 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 4529 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 4530 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 4531 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 4532 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 4533 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 4534 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 4535 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 4536 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 4537 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 4538 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 4539 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 4540 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 4541 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 4542 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 4543 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 4544 |
|
|
Analyzing module .
|
| 4545 |
|
|
Module is correct for synthesis.
|
| 4546 |
|
|
|
| 4547 |
|
|
Analyzing module .
|
| 4548 |
|
|
XTAL_CLK = 35000000
|
| 4549 |
|
|
BAUD = 9600
|
| 4550 |
|
|
CLK_DIV = 113
|
| 4551 |
|
|
CW = 8
|
| 4552 |
|
|
Module is correct for synthesis.
|
| 4553 |
|
|
|
| 4554 |
|
|
Analyzing module .
|
| 4555 |
|
|
Module is correct for synthesis.
|
| 4556 |
|
|
|
| 4557 |
|
|
Analyzing module .
|
| 4558 |
|
|
Module is correct for synthesis.
|
| 4559 |
|
|
|
| 4560 |
|
|
|
| 4561 |
|
|
=========================================================================
|
| 4562 |
|
|
* HDL Synthesis *
|
| 4563 |
|
|
=========================================================================
|
| 4564 |
|
|
|
| 4565 |
|
|
Synthesizing Unit .
|
| 4566 |
|
|
Related source file is "txmit.v".
|
| 4567 |
|
|
Found 1-bit register for signal .
|
| 4568 |
|
|
Found 1-bit register for signal .
|
| 4569 |
|
|
Found 1-bit register for signal .
|
| 4570 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 4571 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 4572 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 4573 |
|
|
Found 1-bit register for signal .
|
| 4574 |
|
|
Found 1-bit register for signal .
|
| 4575 |
|
|
Found 4-bit up counter for signal .
|
| 4576 |
|
|
Found 4-bit up counter for signal .
|
| 4577 |
|
|
Found 8-bit register for signal .
|
| 4578 |
|
|
Found 8-bit register for signal .
|
| 4579 |
|
|
Summary:
|
| 4580 |
|
|
inferred 2 Counter(s).
|
| 4581 |
|
|
inferred 21 D-type flip-flop(s).
|
| 4582 |
|
|
inferred 2 Comparator(s).
|
| 4583 |
|
|
inferred 1 Multiplexer(s).
|
| 4584 |
|
|
Unit synthesized.
|
| 4585 |
|
|
|
| 4586 |
|
|
|
| 4587 |
|
|
Synthesizing Unit .
|
| 4588 |
|
|
Related source file is "rcvr.v".
|
| 4589 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 4590 |
|
|
Found 1-bit register for signal .
|
| 4591 |
|
|
Found 1-bit register for signal .
|
| 4592 |
|
|
Found 1-bit register for signal .
|
| 4593 |
|
|
Found 8-bit tristate buffer for signal .
|
| 4594 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 4595 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 4596 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 4597 |
|
|
Found 1-bit register for signal .
|
| 4598 |
|
|
Found 1-bit register for signal .
|
| 4599 |
|
|
Found 4-bit register for signal .
|
| 4600 |
|
|
Found 4-bit up counter for signal .
|
| 4601 |
|
|
Found 8-bit register for signal .
|
| 4602 |
|
|
Found 7-bit register for signal >.
|
| 4603 |
|
|
Found 1-bit register for signal .
|
| 4604 |
|
|
Found 1-bit register for signal .
|
| 4605 |
|
|
Summary:
|
| 4606 |
|
|
inferred 1 Counter(s).
|
| 4607 |
|
|
inferred 26 D-type flip-flop(s).
|
| 4608 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 4609 |
|
|
inferred 1 Comparator(s).
|
| 4610 |
|
|
inferred 1 Multiplexer(s).
|
| 4611 |
|
|
inferred 8 Tristate(s).
|
| 4612 |
|
|
Unit synthesized.
|
| 4613 |
|
|
|
| 4614 |
|
|
|
| 4615 |
|
|
Synthesizing Unit .
|
| 4616 |
|
|
Related source file is "jkff.v".
|
| 4617 |
|
|
Found 1-bit register for signal .
|
| 4618 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 4619 |
|
|
Summary:
|
| 4620 |
|
|
inferred 1 D-type flip-flop(s).
|
| 4621 |
|
|
inferred 1 Multiplexer(s).
|
| 4622 |
|
|
Unit synthesized.
|
| 4623 |
|
|
|
| 4624 |
|
|
|
| 4625 |
|
|
Synthesizing Unit .
|
| 4626 |
|
|
Related source file is "switchsync.v".
|
| 4627 |
|
|
Found 1-bit register for signal .
|
| 4628 |
|
|
Found 1-bit register for signal .
|
| 4629 |
|
|
Summary:
|
| 4630 |
|
|
inferred 2 D-type flip-flop(s).
|
| 4631 |
|
|
Unit synthesized.
|
| 4632 |
|
|
|
| 4633 |
|
|
|
| 4634 |
|
|
Synthesizing Unit .
|
| 4635 |
|
|
Related source file is "maindcm.v".
|
| 4636 |
|
|
Unit synthesized.
|
| 4637 |
|
|
|
| 4638 |
|
|
|
| 4639 |
|
|
Synthesizing Unit .
|
| 4640 |
|
|
Related source file is "control.v".
|
| 4641 |
|
|
Found 1-bit register for signal .
|
| 4642 |
|
|
Found 1-bit register for signal .
|
| 4643 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 4644 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 4645 |
|
|
Found 3-bit up counter for signal .
|
| 4646 |
|
|
Summary:
|
| 4647 |
|
|
inferred 1 Counter(s).
|
| 4648 |
|
|
inferred 2 D-type flip-flop(s).
|
| 4649 |
|
|
inferred 2 Multiplexer(s).
|
| 4650 |
|
|
Unit synthesized.
|
| 4651 |
|
|
|
| 4652 |
|
|
|
| 4653 |
|
|
Synthesizing Unit .
|
| 4654 |
|
|
Related source file is "misc.v".
|
| 4655 |
|
|
Found 16-bit tristate buffer for signal .
|
| 4656 |
|
|
Summary:
|
| 4657 |
|
|
inferred 16 Tristate(s).
|
| 4658 |
|
|
Unit synthesized.
|
| 4659 |
|
|
|
| 4660 |
|
|
|
| 4661 |
|
|
Synthesizing Unit .
|
| 4662 |
|
|
Related source file is "misc.v".
|
| 4663 |
|
|
Found 16-bit tristate buffer for signal .
|
| 4664 |
|
|
Summary:
|
| 4665 |
|
|
inferred 16 Tristate(s).
|
| 4666 |
|
|
Unit synthesized.
|
| 4667 |
|
|
|
| 4668 |
|
|
|
| 4669 |
|
|
Synthesizing Unit .
|
| 4670 |
|
|
Related source file is "misc.v".
|
| 4671 |
|
|
Found 16-bit tristate buffer for signal .
|
| 4672 |
|
|
Summary:
|
| 4673 |
|
|
inferred 16 Tristate(s).
|
| 4674 |
|
|
Unit synthesized.
|
| 4675 |
|
|
|
| 4676 |
|
|
|
| 4677 |
|
|
Synthesizing Unit .
|
| 4678 |
|
|
Related source file is "misc.v".
|
| 4679 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 4680 |
|
|
Found 16-bit tristate buffer for signal .
|
| 4681 |
|
|
Found 12-bit register for signal .
|
| 4682 |
|
|
Summary:
|
| 4683 |
|
|
inferred 12 D-type flip-flop(s).
|
| 4684 |
|
|
inferred 16 Tristate(s).
|
| 4685 |
|
|
Unit synthesized.
|
| 4686 |
|
|
|
| 4687 |
|
|
|
| 4688 |
|
|
Synthesizing Unit .
|
| 4689 |
|
|
Related source file is "idecode.v".
|
| 4690 |
|
|
Unit synthesized.
|
| 4691 |
|
|
|
| 4692 |
|
|
|
| 4693 |
|
|
Synthesizing Unit .
|
| 4694 |
|
|
Related source file is "control.v".
|
| 4695 |
|
|
Unit synthesized.
|
| 4696 |
|
|
|
| 4697 |
|
|
|
| 4698 |
|
|
Synthesizing Unit .
|
| 4699 |
|
|
Related source file is "alu.v".
|
| 4700 |
|
|
Found 16-bit tristate buffer for signal .
|
| 4701 |
|
|
Found 17-bit subtractor for signal <$AUX_108>.
|
| 4702 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 4703 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 4704 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 4705 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 4706 |
|
|
Summary:
|
| 4707 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 4708 |
|
|
inferred 16 Tristate(s).
|
| 4709 |
|
|
Unit synthesized.
|
| 4710 |
|
|
|
| 4711 |
|
|
|
| 4712 |
|
|
Synthesizing Unit .
|
| 4713 |
|
|
Related source file is "misc.v".
|
| 4714 |
|
|
Unit synthesized.
|
| 4715 |
|
|
|
| 4716 |
|
|
|
| 4717 |
|
|
Synthesizing Unit .
|
| 4718 |
|
|
Related source file is "misc.v".
|
| 4719 |
|
|
Unit synthesized.
|
| 4720 |
|
|
|
| 4721 |
|
|
|
| 4722 |
|
|
Synthesizing Unit .
|
| 4723 |
|
|
Related source file is "misc.v".
|
| 4724 |
|
|
Unit synthesized.
|
| 4725 |
|
|
|
| 4726 |
|
|
|
| 4727 |
|
|
Synthesizing Unit .
|
| 4728 |
|
|
Related source file is "misc.v".
|
| 4729 |
|
|
Unit synthesized.
|
| 4730 |
|
|
|
| 4731 |
|
|
|
| 4732 |
|
|
Synthesizing Unit .
|
| 4733 |
|
|
Related source file is "misc.v".
|
| 4734 |
|
|
Found 16-bit tristate buffer for signal .
|
| 4735 |
|
|
Found 16-bit register for signal .
|
| 4736 |
|
|
Summary:
|
| 4737 |
|
|
inferred 16 D-type flip-flop(s).
|
| 4738 |
|
|
inferred 16 Tristate(s).
|
| 4739 |
|
|
Unit synthesized.
|
| 4740 |
|
|
|
| 4741 |
|
|
|
| 4742 |
|
|
Synthesizing Unit .
|
| 4743 |
|
|
Related source file is "io.v".
|
| 4744 |
|
|
Found 1-bit register for signal .
|
| 4745 |
|
|
Found 1-bit register for signal .
|
| 4746 |
|
|
Found 1-bit register for signal .
|
| 4747 |
|
|
Found 1-bit register for signal .
|
| 4748 |
|
|
Found 1-bit register for signal .
|
| 4749 |
|
|
Found 1-bit register for signal .
|
| 4750 |
|
|
Found 19-bit down counter for signal .
|
| 4751 |
|
|
Found 1-bit register for signal .
|
| 4752 |
|
|
Found 1-bit xor2 for signal .
|
| 4753 |
|
|
Summary:
|
| 4754 |
|
|
inferred 1 Counter(s).
|
| 4755 |
|
|
inferred 7 D-type flip-flop(s).
|
| 4756 |
|
|
Unit synthesized.
|
| 4757 |
|
|
|
| 4758 |
|
|
|
| 4759 |
|
|
Synthesizing Unit .
|
| 4760 |
|
|
Related source file is "io.v".
|
| 4761 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 4762 |
|
|
Found 1-bit register for signal .
|
| 4763 |
|
|
Found 1-bit register for signal .
|
| 4764 |
|
|
Found 1-bit register for signal .
|
| 4765 |
|
|
Found 1-bit register for signal .
|
| 4766 |
|
|
Found 1-bit register for signal .
|
| 4767 |
|
|
Found 1-bit register for signal .
|
| 4768 |
|
|
Found 1-bit register for signal .
|
| 4769 |
|
|
Found 1-bit register for signal .
|
| 4770 |
|
|
Found 1-bit register for signal .
|
| 4771 |
|
|
Found 1-bit register for signal .
|
| 4772 |
|
|
Found 1-bit register for signal .
|
| 4773 |
|
|
Found 1-bit register for signal .
|
| 4774 |
|
|
Found 24-bit up counter for signal .
|
| 4775 |
|
|
Found 1-of-4 decoder for signal .
|
| 4776 |
|
|
Found 2-bit down counter for signal .
|
| 4777 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 4778 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 4779 |
|
|
Summary:
|
| 4780 |
|
|
inferred 1 ROM(s).
|
| 4781 |
|
|
inferred 2 Counter(s).
|
| 4782 |
|
|
inferred 12 D-type flip-flop(s).
|
| 4783 |
|
|
inferred 9 Multiplexer(s).
|
| 4784 |
|
|
inferred 1 Decoder(s).
|
| 4785 |
|
|
Unit synthesized.
|
| 4786 |
|
|
|
| 4787 |
|
|
|
| 4788 |
|
|
Synthesizing Unit .
|
| 4789 |
|
|
Related source file is "uart.v".
|
| 4790 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 4791 |
|
|
Found 1-bit register for signal .
|
| 4792 |
|
|
Found 8-bit up counter for signal .
|
| 4793 |
|
|
Found 1-bit register for signal .
|
| 4794 |
|
|
Summary:
|
| 4795 |
|
|
inferred 1 Counter(s).
|
| 4796 |
|
|
inferred 2 D-type flip-flop(s).
|
| 4797 |
|
|
inferred 1 Multiplexer(s).
|
| 4798 |
|
|
Unit synthesized.
|
| 4799 |
|
|
|
| 4800 |
|
|
|
| 4801 |
|
|
Synthesizing Unit .
|
| 4802 |
|
|
Related source file is "top.v".
|
| 4803 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 4804 |
|
|
Found 16-bit tristate buffer for signal .
|
| 4805 |
|
|
Found 1-bit register for signal .
|
| 4806 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 4807 |
|
|
Found 16-bit tristate buffer for signal .
|
| 4808 |
|
|
Found 1-bit register for signal .
|
| 4809 |
|
|
Found 1-bit register for signal .
|
| 4810 |
|
|
Found 1-bit register for signal .
|
| 4811 |
|
|
Summary:
|
| 4812 |
|
|
inferred 4 D-type flip-flop(s).
|
| 4813 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 4814 |
|
|
inferred 96 Tristate(s).
|
| 4815 |
|
|
Unit synthesized.
|
| 4816 |
|
|
|
| 4817 |
|
|
|
| 4818 |
|
|
Synthesizing Unit .
|
| 4819 |
|
|
Related source file is "FrontPanel.v".
|
| 4820 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 4821 |
|
|
Found finite state machine for signal .
|
| 4822 |
|
|
-----------------------------------------------------------------------
|
| 4823 |
|
|
| States | 6 |
|
| 4824 |
|
|
| Transitions | 6 |
|
| 4825 |
|
|
| Inputs | 0 |
|
| 4826 |
|
|
| Outputs | 12 |
|
| 4827 |
|
|
| Clock | clockin (rising_edge) |
|
| 4828 |
|
|
| Clock enable | select (positive) |
|
| 4829 |
|
|
| Reset | clear (positive) |
|
| 4830 |
|
|
| Reset type | synchronous |
|
| 4831 |
|
|
| Reset State | 000001 |
|
| 4832 |
|
|
| Encoding | automatic |
|
| 4833 |
|
|
| Implementation | LUT |
|
| 4834 |
|
|
-----------------------------------------------------------------------
|
| 4835 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 4836 |
|
|
Found 4-bit register for signal .
|
| 4837 |
|
|
Found 16-bit register for signal .
|
| 4838 |
|
|
Summary:
|
| 4839 |
|
|
inferred 1 Finite State Machine(s).
|
| 4840 |
|
|
inferred 16 D-type flip-flop(s).
|
| 4841 |
|
|
inferred 16 Multiplexer(s).
|
| 4842 |
|
|
Unit synthesized.
|
| 4843 |
|
|
|
| 4844 |
|
|
|
| 4845 |
|
|
Synthesizing Unit .
|
| 4846 |
|
|
Related source file is "topbox.v".
|
| 4847 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 4848 |
|
|
Found 16-bit tristate buffer for signal .
|
| 4849 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 4850 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 4851 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 4852 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 4853 |
|
|
Found 4-bit register for signal .
|
| 4854 |
|
|
Found 1-bit register for signal .
|
| 4855 |
|
|
Found 1-bit register for signal .
|
| 4856 |
|
|
Found 16-bit register for signal .
|
| 4857 |
|
|
Summary:
|
| 4858 |
|
|
inferred 22 D-type flip-flop(s).
|
| 4859 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 4860 |
|
|
inferred 6 Multiplexer(s).
|
| 4861 |
|
|
inferred 48 Tristate(s).
|
| 4862 |
|
|
Unit synthesized.
|
| 4863 |
|
|
|
| 4864 |
|
|
|
| 4865 |
|
|
=========================================================================
|
| 4866 |
|
|
* Advanced HDL Synthesis *
|
| 4867 |
|
|
=========================================================================
|
| 4868 |
|
|
|
| 4869 |
|
|
Advanced RAM inference ...
|
| 4870 |
|
|
Advanced multiplier inference ...
|
| 4871 |
|
|
Advanced Registered AddSub inference ...
|
| 4872 |
|
|
Analyzing FSM for best encoding.
|
| 4873 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 4874 |
|
|
--------------------
|
| 4875 |
|
|
State | Encoding
|
| 4876 |
|
|
--------------------
|
| 4877 |
|
|
000001 | 100000
|
| 4878 |
|
|
000010 | 010000
|
| 4879 |
|
|
000100 | 001000
|
| 4880 |
|
|
001000 | 000100
|
| 4881 |
|
|
010000 | 000010
|
| 4882 |
|
|
100000 | 000001
|
| 4883 |
|
|
--------------------
|
| 4884 |
|
|
Dynamic shift register inference ...
|
| 4885 |
|
|
|
| 4886 |
|
|
=========================================================================
|
| 4887 |
|
|
HDL Synthesis Report
|
| 4888 |
|
|
|
| 4889 |
|
|
Macro Statistics
|
| 4890 |
|
|
# FSMs : 1
|
| 4891 |
|
|
# ROMs : 1
|
| 4892 |
|
|
16x7-bit ROM : 1
|
| 4893 |
|
|
# Adders/Subtractors : 5
|
| 4894 |
|
|
12-bit adder carry out : 1
|
| 4895 |
|
|
16-bit adder carry out : 1
|
| 4896 |
|
|
17-bit subtractor : 1
|
| 4897 |
|
|
4-bit adder : 2
|
| 4898 |
|
|
# Counters : 10
|
| 4899 |
|
|
19-bit down counter : 3
|
| 4900 |
|
|
2-bit down counter : 1
|
| 4901 |
|
|
24-bit up counter : 1
|
| 4902 |
|
|
3-bit up counter : 1
|
| 4903 |
|
|
4-bit up counter : 3
|
| 4904 |
|
|
8-bit up counter : 1
|
| 4905 |
|
|
# Registers : 138
|
| 4906 |
|
|
1-bit register : 125
|
| 4907 |
|
|
12-bit register : 4
|
| 4908 |
|
|
16-bit register : 4
|
| 4909 |
|
|
4-bit register : 3
|
| 4910 |
|
|
8-bit register : 2
|
| 4911 |
|
|
# Comparators : 3
|
| 4912 |
|
|
4-bit comparator greater : 2
|
| 4913 |
|
|
4-bit comparator less : 1
|
| 4914 |
|
|
# Multiplexers : 15
|
| 4915 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 4916 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 4917 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 4918 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 4919 |
|
|
# Decoders : 1
|
| 4920 |
|
|
1-of-4 decoder : 1
|
| 4921 |
|
|
# Tristates : 97
|
| 4922 |
|
|
1-bit tristate buffer : 80
|
| 4923 |
|
|
16-bit tristate buffer : 16
|
| 4924 |
|
|
8-bit tristate buffer : 1
|
| 4925 |
|
|
# Xors : 6
|
| 4926 |
|
|
1-bit xor2 : 5
|
| 4927 |
|
|
16-bit xor2 : 1
|
| 4928 |
|
|
|
| 4929 |
|
|
=========================================================================
|
| 4930 |
|
|
|
| 4931 |
|
|
=========================================================================
|
| 4932 |
|
|
* Low Level Synthesis *
|
| 4933 |
|
|
=========================================================================
|
| 4934 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4935 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4936 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4937 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 4938 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 4939 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 4940 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 4941 |
|
|
|
| 4942 |
|
|
Optimizing unit ...
|
| 4943 |
|
|
|
| 4944 |
|
|
Optimizing unit ...
|
| 4945 |
|
|
|
| 4946 |
|
|
Optimizing unit ...
|
| 4947 |
|
|
|
| 4948 |
|
|
Optimizing unit ...
|
| 4949 |
|
|
|
| 4950 |
|
|
Optimizing unit ...
|
| 4951 |
|
|
|
| 4952 |
|
|
Optimizing unit ...
|
| 4953 |
|
|
|
| 4954 |
|
|
Optimizing unit ...
|
| 4955 |
|
|
|
| 4956 |
|
|
Optimizing unit ...
|
| 4957 |
|
|
|
| 4958 |
|
|
Optimizing unit ...
|
| 4959 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 4960 |
|
|
|
| 4961 |
|
|
Mapping all equations...
|
| 4962 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4963 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4964 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 4965 |
|
|
Building and optimizing final netlist ...
|
| 4966 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
|
| 4967 |
|
|
FlipFlop CPU/IR/regvalue_0 has been replicated 1 time(s)
|
| 4968 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 3 time(s)
|
| 4969 |
|
|
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
|
| 4970 |
|
|
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
|
| 4971 |
|
|
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
|
| 4972 |
|
|
FlipFlop CPU/IR/regvalue_15 has been replicated 2 time(s)
|
| 4973 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
|
| 4974 |
|
|
FlipFlop CPU/IR/regvalue_5 has been replicated 1 time(s)
|
| 4975 |
|
|
FlipFlop CPU/ctl/sim/counter_0 has been replicated 1 time(s)
|
| 4976 |
|
|
FlipFlop CPU/ctl/sim/counter_1 has been replicated 2 time(s)
|
| 4977 |
|
|
FlipFlop CPU/ctl/sim/counter_2 has been replicated 1 time(s)
|
| 4978 |
|
|
|
| 4979 |
|
|
=========================================================================
|
| 4980 |
|
|
* Final Report *
|
| 4981 |
|
|
=========================================================================
|
| 4982 |
|
|
|
| 4983 |
|
|
Device utilization summary:
|
| 4984 |
|
|
---------------------------
|
| 4985 |
|
|
|
| 4986 |
|
|
Selected Device : 3s200ft256-4
|
| 4987 |
|
|
|
| 4988 |
|
|
Number of Slices: 648 out of 1920 33%
|
| 4989 |
|
|
Number of Slice Flip Flops: 385 out of 3840 10%
|
| 4990 |
|
|
Number of 4 input LUTs: 1154 out of 3840 30%
|
| 4991 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 4992 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 4993 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 4994 |
|
|
|
| 4995 |
|
|
|
| 4996 |
|
|
=========================================================================
|
| 4997 |
|
|
TIMING REPORT
|
| 4998 |
|
|
|
| 4999 |
|
|
|
| 5000 |
|
|
Clock Information:
|
| 5001 |
|
|
------------------
|
| 5002 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 5003 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 5004 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 5005 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 385 |
|
| 5006 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 5007 |
|
|
|
| 5008 |
|
|
Timing Summary:
|
| 5009 |
|
|
---------------
|
| 5010 |
|
|
Speed Grade: -4
|
| 5011 |
|
|
|
| 5012 |
|
|
Minimum period: 14.928ns (Maximum Frequency: 66.987MHz)
|
| 5013 |
|
|
Minimum input arrival time before clock: 10.934ns
|
| 5014 |
|
|
Maximum output required time after clock: 25.303ns
|
| 5015 |
|
|
Maximum combinational path delay: 14.935ns
|
| 5016 |
|
|
|
| 5017 |
|
|
=========================================================================
|
| 5018 |
|
|
|
| 5019 |
|
|
|
| 5020 |
|
|
|
| 5021 |
|
|
|
| 5022 |
|
|
Started process "Translate".
|
| 5023 |
|
|
|
| 5024 |
|
|
|
| 5025 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 5026 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 5027 |
|
|
|
| 5028 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 5029 |
|
|
|
| 5030 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 5031 |
|
|
ERROR:NgdBuild:756 - Line 213 in 'tobox.ucf': Could not find net(s) 'CPU/cp<4>'
|
| 5032 |
|
|
in the design. To suppress this error specify the correct net name or remove
|
| 5033 |
|
|
the constraint.
|
| 5034 |
|
|
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
|
| 5035 |
|
|
ERROR:NgdBuild:19 - Errors found while parsing constraint file "tobox.ucf".
|
| 5036 |
|
|
|
| 5037 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 5038 |
|
|
ERROR: NGDBUILD failed
|
| 5039 |
|
|
Process "Translate" did not complete.
|
| 5040 |
|
|
|
| 5041 |
|
|
|
| 5042 |
|
|
Project Navigator Auto-Make Log File
|
| 5043 |
|
|
-------------------------------------
|
| 5044 |
|
|
|
| 5045 |
|
|
|
| 5046 |
|
|
|
| 5047 |
|
|
|
| 5048 |
|
|
Started process "Synthesize".
|
| 5049 |
|
|
|
| 5050 |
|
|
|
| 5051 |
|
|
=========================================================================
|
| 5052 |
|
|
* HDL Compilation *
|
| 5053 |
|
|
=========================================================================
|
| 5054 |
|
|
Compiling verilog file "io.v"
|
| 5055 |
|
|
Module compiled
|
| 5056 |
|
|
Module compiled
|
| 5057 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 5058 |
|
|
Module compiled
|
| 5059 |
|
|
Compiling verilog file "misc.v"
|
| 5060 |
|
|
Module compiled
|
| 5061 |
|
|
Module compiled
|
| 5062 |
|
|
Module compiled
|
| 5063 |
|
|
Module compiled
|
| 5064 |
|
|
Module compiled
|
| 5065 |
|
|
Module compiled
|
| 5066 |
|
|
Compiling verilog file "alu.v"
|
| 5067 |
|
|
Module compiled
|
| 5068 |
|
|
Compiling verilog file "switchsync.v"
|
| 5069 |
|
|
Module compiled
|
| 5070 |
|
|
Compiling verilog file "jkff.v"
|
| 5071 |
|
|
Module compiled
|
| 5072 |
|
|
Compiling verilog file "control.v"
|
| 5073 |
|
|
Module compiled
|
| 5074 |
|
|
Module compiled
|
| 5075 |
|
|
Compiling verilog file "maindcm.v"
|
| 5076 |
|
|
Module compiled
|
| 5077 |
|
|
Compiling verilog file "idecode.v"
|
| 5078 |
|
|
Module compiled
|
| 5079 |
|
|
Compiling verilog file "top.v"
|
| 5080 |
|
|
Module compiled
|
| 5081 |
|
|
Compiling verilog file "rcvr.v"
|
| 5082 |
|
|
Module compiled
|
| 5083 |
|
|
Compiling verilog file "txmit.v"
|
| 5084 |
|
|
Module compiled
|
| 5085 |
|
|
Compiling verilog file "uart.v"
|
| 5086 |
|
|
Module compiled
|
| 5087 |
|
|
Compiling verilog file "topbox.v"
|
| 5088 |
|
|
Module compiled
|
| 5089 |
|
|
No errors in compilation
|
| 5090 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 5091 |
|
|
|
| 5092 |
|
|
|
| 5093 |
|
|
=========================================================================
|
| 5094 |
|
|
* HDL Analysis *
|
| 5095 |
|
|
=========================================================================
|
| 5096 |
|
|
Analyzing top module .
|
| 5097 |
|
|
Module is correct for synthesis.
|
| 5098 |
|
|
|
| 5099 |
|
|
Analyzing module .
|
| 5100 |
|
|
Module is correct for synthesis.
|
| 5101 |
|
|
|
| 5102 |
|
|
Analyzing module .
|
| 5103 |
|
|
pClockFrequency = 50
|
| 5104 |
|
|
pRefreshFrequency = 100
|
| 5105 |
|
|
pUpperLimit = 125000
|
| 5106 |
|
|
pDividerCounterBits = 24
|
| 5107 |
|
|
Module is correct for synthesis.
|
| 5108 |
|
|
|
| 5109 |
|
|
Analyzing module .
|
| 5110 |
|
|
pInitialValue = 0
|
| 5111 |
|
|
pTimerWidth = 19
|
| 5112 |
|
|
pInitialTimerValue = 500000
|
| 5113 |
|
|
Module is correct for synthesis.
|
| 5114 |
|
|
|
| 5115 |
|
|
Analyzing module .
|
| 5116 |
|
|
Module is correct for synthesis.
|
| 5117 |
|
|
|
| 5118 |
|
|
Analyzing module .
|
| 5119 |
|
|
SIZE = 16
|
| 5120 |
|
|
Module is correct for synthesis.
|
| 5121 |
|
|
|
| 5122 |
|
|
Analyzing module .
|
| 5123 |
|
|
Module is correct for synthesis.
|
| 5124 |
|
|
|
| 5125 |
|
|
Analyzing module .
|
| 5126 |
|
|
SIZE = 12
|
| 5127 |
|
|
Module is correct for synthesis.
|
| 5128 |
|
|
|
| 5129 |
|
|
Analyzing module .
|
| 5130 |
|
|
Module is correct for synthesis.
|
| 5131 |
|
|
|
| 5132 |
|
|
Analyzing module .
|
| 5133 |
|
|
VALUE = 0000000000000001
|
| 5134 |
|
|
Module is correct for synthesis.
|
| 5135 |
|
|
|
| 5136 |
|
|
Analyzing module .
|
| 5137 |
|
|
Module is correct for synthesis.
|
| 5138 |
|
|
|
| 5139 |
|
|
Analyzing module .
|
| 5140 |
|
|
VALUE = 1111111111111111
|
| 5141 |
|
|
Module is correct for synthesis.
|
| 5142 |
|
|
|
| 5143 |
|
|
Analyzing module .
|
| 5144 |
|
|
Module is correct for synthesis.
|
| 5145 |
|
|
|
| 5146 |
|
|
Analyzing module .
|
| 5147 |
|
|
VALUE = 0000000000000000
|
| 5148 |
|
|
Module is correct for synthesis.
|
| 5149 |
|
|
|
| 5150 |
|
|
Analyzing module .
|
| 5151 |
|
|
Module is correct for synthesis.
|
| 5152 |
|
|
|
| 5153 |
|
|
Analyzing module .
|
| 5154 |
|
|
Module is correct for synthesis.
|
| 5155 |
|
|
|
| 5156 |
|
|
Analyzing module .
|
| 5157 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 5158 |
|
|
Module is correct for synthesis.
|
| 5159 |
|
|
|
| 5160 |
|
|
Analyzing module .
|
| 5161 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 5162 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 5163 |
|
|
Module is correct for synthesis.
|
| 5164 |
|
|
|
| 5165 |
|
|
Analyzing module .
|
| 5166 |
|
|
Module is correct for synthesis.
|
| 5167 |
|
|
|
| 5168 |
|
|
Analyzing module .
|
| 5169 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5170 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5171 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5172 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5173 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5174 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5175 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5176 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5177 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5178 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5179 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5180 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5181 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5182 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 5183 |
|
|
Module is correct for synthesis.
|
| 5184 |
|
|
|
| 5185 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 5186 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 5187 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 5188 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 5189 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 5190 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 5191 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 5192 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 5193 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 5194 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 5195 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 5196 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 5197 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 5198 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 5199 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 5200 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 5201 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 5202 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 5203 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 5204 |
|
|
Analyzing module .
|
| 5205 |
|
|
Module is correct for synthesis.
|
| 5206 |
|
|
|
| 5207 |
|
|
Analyzing module .
|
| 5208 |
|
|
XTAL_CLK = 35000000
|
| 5209 |
|
|
BAUD = 9600
|
| 5210 |
|
|
CLK_DIV = 113
|
| 5211 |
|
|
CW = 8
|
| 5212 |
|
|
Module is correct for synthesis.
|
| 5213 |
|
|
|
| 5214 |
|
|
Analyzing module .
|
| 5215 |
|
|
Module is correct for synthesis.
|
| 5216 |
|
|
|
| 5217 |
|
|
Analyzing module .
|
| 5218 |
|
|
Module is correct for synthesis.
|
| 5219 |
|
|
|
| 5220 |
|
|
|
| 5221 |
|
|
=========================================================================
|
| 5222 |
|
|
* HDL Synthesis *
|
| 5223 |
|
|
=========================================================================
|
| 5224 |
|
|
|
| 5225 |
|
|
Synthesizing Unit .
|
| 5226 |
|
|
Related source file is "txmit.v".
|
| 5227 |
|
|
Found 1-bit register for signal .
|
| 5228 |
|
|
Found 1-bit register for signal .
|
| 5229 |
|
|
Found 1-bit register for signal .
|
| 5230 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 5231 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 5232 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 5233 |
|
|
Found 1-bit register for signal .
|
| 5234 |
|
|
Found 1-bit register for signal .
|
| 5235 |
|
|
Found 4-bit up counter for signal .
|
| 5236 |
|
|
Found 4-bit up counter for signal .
|
| 5237 |
|
|
Found 8-bit register for signal .
|
| 5238 |
|
|
Found 8-bit register for signal .
|
| 5239 |
|
|
Summary:
|
| 5240 |
|
|
inferred 2 Counter(s).
|
| 5241 |
|
|
inferred 21 D-type flip-flop(s).
|
| 5242 |
|
|
inferred 2 Comparator(s).
|
| 5243 |
|
|
inferred 1 Multiplexer(s).
|
| 5244 |
|
|
Unit synthesized.
|
| 5245 |
|
|
|
| 5246 |
|
|
|
| 5247 |
|
|
Synthesizing Unit .
|
| 5248 |
|
|
Related source file is "rcvr.v".
|
| 5249 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 5250 |
|
|
Found 1-bit register for signal .
|
| 5251 |
|
|
Found 1-bit register for signal .
|
| 5252 |
|
|
Found 1-bit register for signal .
|
| 5253 |
|
|
Found 8-bit tristate buffer for signal .
|
| 5254 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 5255 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 5256 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 5257 |
|
|
Found 1-bit register for signal .
|
| 5258 |
|
|
Found 1-bit register for signal .
|
| 5259 |
|
|
Found 4-bit register for signal .
|
| 5260 |
|
|
Found 4-bit up counter for signal .
|
| 5261 |
|
|
Found 8-bit register for signal .
|
| 5262 |
|
|
Found 7-bit register for signal >.
|
| 5263 |
|
|
Found 1-bit register for signal .
|
| 5264 |
|
|
Found 1-bit register for signal .
|
| 5265 |
|
|
Summary:
|
| 5266 |
|
|
inferred 1 Counter(s).
|
| 5267 |
|
|
inferred 26 D-type flip-flop(s).
|
| 5268 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 5269 |
|
|
inferred 1 Comparator(s).
|
| 5270 |
|
|
inferred 1 Multiplexer(s).
|
| 5271 |
|
|
inferred 8 Tristate(s).
|
| 5272 |
|
|
Unit synthesized.
|
| 5273 |
|
|
|
| 5274 |
|
|
|
| 5275 |
|
|
Synthesizing Unit .
|
| 5276 |
|
|
Related source file is "jkff.v".
|
| 5277 |
|
|
Found 1-bit register for signal .
|
| 5278 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 5279 |
|
|
Summary:
|
| 5280 |
|
|
inferred 1 D-type flip-flop(s).
|
| 5281 |
|
|
inferred 1 Multiplexer(s).
|
| 5282 |
|
|
Unit synthesized.
|
| 5283 |
|
|
|
| 5284 |
|
|
|
| 5285 |
|
|
Synthesizing Unit .
|
| 5286 |
|
|
Related source file is "switchsync.v".
|
| 5287 |
|
|
Found 1-bit register for signal .
|
| 5288 |
|
|
Found 1-bit register for signal .
|
| 5289 |
|
|
Summary:
|
| 5290 |
|
|
inferred 2 D-type flip-flop(s).
|
| 5291 |
|
|
Unit synthesized.
|
| 5292 |
|
|
|
| 5293 |
|
|
|
| 5294 |
|
|
Synthesizing Unit .
|
| 5295 |
|
|
Related source file is "maindcm.v".
|
| 5296 |
|
|
Unit synthesized.
|
| 5297 |
|
|
|
| 5298 |
|
|
|
| 5299 |
|
|
Synthesizing Unit .
|
| 5300 |
|
|
Related source file is "control.v".
|
| 5301 |
|
|
Found 1-bit register for signal .
|
| 5302 |
|
|
Found 1-bit register for signal .
|
| 5303 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 5304 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 5305 |
|
|
Found 3-bit up counter for signal .
|
| 5306 |
|
|
Summary:
|
| 5307 |
|
|
inferred 1 Counter(s).
|
| 5308 |
|
|
inferred 2 D-type flip-flop(s).
|
| 5309 |
|
|
inferred 2 Multiplexer(s).
|
| 5310 |
|
|
Unit synthesized.
|
| 5311 |
|
|
|
| 5312 |
|
|
|
| 5313 |
|
|
Synthesizing Unit .
|
| 5314 |
|
|
Related source file is "misc.v".
|
| 5315 |
|
|
Found 16-bit tristate buffer for signal .
|
| 5316 |
|
|
Summary:
|
| 5317 |
|
|
inferred 16 Tristate(s).
|
| 5318 |
|
|
Unit synthesized.
|
| 5319 |
|
|
|
| 5320 |
|
|
|
| 5321 |
|
|
Synthesizing Unit .
|
| 5322 |
|
|
Related source file is "misc.v".
|
| 5323 |
|
|
Found 16-bit tristate buffer for signal .
|
| 5324 |
|
|
Summary:
|
| 5325 |
|
|
inferred 16 Tristate(s).
|
| 5326 |
|
|
Unit synthesized.
|
| 5327 |
|
|
|
| 5328 |
|
|
|
| 5329 |
|
|
Synthesizing Unit .
|
| 5330 |
|
|
Related source file is "misc.v".
|
| 5331 |
|
|
Found 16-bit tristate buffer for signal .
|
| 5332 |
|
|
Summary:
|
| 5333 |
|
|
inferred 16 Tristate(s).
|
| 5334 |
|
|
Unit synthesized.
|
| 5335 |
|
|
|
| 5336 |
|
|
|
| 5337 |
|
|
Synthesizing Unit .
|
| 5338 |
|
|
Related source file is "misc.v".
|
| 5339 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 5340 |
|
|
Found 16-bit tristate buffer for signal .
|
| 5341 |
|
|
Found 12-bit register for signal .
|
| 5342 |
|
|
Summary:
|
| 5343 |
|
|
inferred 12 D-type flip-flop(s).
|
| 5344 |
|
|
inferred 16 Tristate(s).
|
| 5345 |
|
|
Unit synthesized.
|
| 5346 |
|
|
|
| 5347 |
|
|
|
| 5348 |
|
|
Synthesizing Unit .
|
| 5349 |
|
|
Related source file is "idecode.v".
|
| 5350 |
|
|
Unit synthesized.
|
| 5351 |
|
|
|
| 5352 |
|
|
|
| 5353 |
|
|
Synthesizing Unit .
|
| 5354 |
|
|
Related source file is "control.v".
|
| 5355 |
|
|
Unit synthesized.
|
| 5356 |
|
|
|
| 5357 |
|
|
|
| 5358 |
|
|
Synthesizing Unit .
|
| 5359 |
|
|
Related source file is "alu.v".
|
| 5360 |
|
|
Found 16-bit tristate buffer for signal .
|
| 5361 |
|
|
Found 17-bit subtractor for signal <$AUX_108>.
|
| 5362 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 5363 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 5364 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 5365 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 5366 |
|
|
Summary:
|
| 5367 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 5368 |
|
|
inferred 16 Tristate(s).
|
| 5369 |
|
|
Unit synthesized.
|
| 5370 |
|
|
|
| 5371 |
|
|
|
| 5372 |
|
|
Synthesizing Unit .
|
| 5373 |
|
|
Related source file is "misc.v".
|
| 5374 |
|
|
Unit synthesized.
|
| 5375 |
|
|
|
| 5376 |
|
|
|
| 5377 |
|
|
Synthesizing Unit .
|
| 5378 |
|
|
Related source file is "misc.v".
|
| 5379 |
|
|
Unit synthesized.
|
| 5380 |
|
|
|
| 5381 |
|
|
|
| 5382 |
|
|
Synthesizing Unit .
|
| 5383 |
|
|
Related source file is "misc.v".
|
| 5384 |
|
|
Unit synthesized.
|
| 5385 |
|
|
|
| 5386 |
|
|
|
| 5387 |
|
|
Synthesizing Unit .
|
| 5388 |
|
|
Related source file is "misc.v".
|
| 5389 |
|
|
Unit synthesized.
|
| 5390 |
|
|
|
| 5391 |
|
|
|
| 5392 |
|
|
Synthesizing Unit .
|
| 5393 |
|
|
Related source file is "misc.v".
|
| 5394 |
|
|
Found 16-bit tristate buffer for signal .
|
| 5395 |
|
|
Found 16-bit register for signal .
|
| 5396 |
|
|
Summary:
|
| 5397 |
|
|
inferred 16 D-type flip-flop(s).
|
| 5398 |
|
|
inferred 16 Tristate(s).
|
| 5399 |
|
|
Unit synthesized.
|
| 5400 |
|
|
|
| 5401 |
|
|
|
| 5402 |
|
|
Synthesizing Unit .
|
| 5403 |
|
|
Related source file is "io.v".
|
| 5404 |
|
|
Found 1-bit register for signal .
|
| 5405 |
|
|
Found 1-bit register for signal .
|
| 5406 |
|
|
Found 1-bit register for signal .
|
| 5407 |
|
|
Found 1-bit register for signal .
|
| 5408 |
|
|
Found 1-bit register for signal .
|
| 5409 |
|
|
Found 1-bit register for signal .
|
| 5410 |
|
|
Found 19-bit down counter for signal .
|
| 5411 |
|
|
Found 1-bit register for signal .
|
| 5412 |
|
|
Found 1-bit xor2 for signal .
|
| 5413 |
|
|
Summary:
|
| 5414 |
|
|
inferred 1 Counter(s).
|
| 5415 |
|
|
inferred 7 D-type flip-flop(s).
|
| 5416 |
|
|
Unit synthesized.
|
| 5417 |
|
|
|
| 5418 |
|
|
|
| 5419 |
|
|
Synthesizing Unit .
|
| 5420 |
|
|
Related source file is "io.v".
|
| 5421 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 5422 |
|
|
Found 1-bit register for signal .
|
| 5423 |
|
|
Found 1-bit register for signal .
|
| 5424 |
|
|
Found 1-bit register for signal .
|
| 5425 |
|
|
Found 1-bit register for signal .
|
| 5426 |
|
|
Found 1-bit register for signal .
|
| 5427 |
|
|
Found 1-bit register for signal .
|
| 5428 |
|
|
Found 1-bit register for signal .
|
| 5429 |
|
|
Found 1-bit register for signal .
|
| 5430 |
|
|
Found 1-bit register for signal .
|
| 5431 |
|
|
Found 1-bit register for signal .
|
| 5432 |
|
|
Found 1-bit register for signal .
|
| 5433 |
|
|
Found 1-bit register for signal .
|
| 5434 |
|
|
Found 24-bit up counter for signal .
|
| 5435 |
|
|
Found 1-of-4 decoder for signal .
|
| 5436 |
|
|
Found 2-bit down counter for signal .
|
| 5437 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 5438 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 5439 |
|
|
Summary:
|
| 5440 |
|
|
inferred 1 ROM(s).
|
| 5441 |
|
|
inferred 2 Counter(s).
|
| 5442 |
|
|
inferred 12 D-type flip-flop(s).
|
| 5443 |
|
|
inferred 9 Multiplexer(s).
|
| 5444 |
|
|
inferred 1 Decoder(s).
|
| 5445 |
|
|
Unit synthesized.
|
| 5446 |
|
|
|
| 5447 |
|
|
|
| 5448 |
|
|
Synthesizing Unit .
|
| 5449 |
|
|
Related source file is "uart.v".
|
| 5450 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 5451 |
|
|
Found 1-bit register for signal .
|
| 5452 |
|
|
Found 8-bit up counter for signal .
|
| 5453 |
|
|
Found 1-bit register for signal .
|
| 5454 |
|
|
Summary:
|
| 5455 |
|
|
inferred 1 Counter(s).
|
| 5456 |
|
|
inferred 2 D-type flip-flop(s).
|
| 5457 |
|
|
inferred 1 Multiplexer(s).
|
| 5458 |
|
|
Unit synthesized.
|
| 5459 |
|
|
|
| 5460 |
|
|
|
| 5461 |
|
|
Synthesizing Unit .
|
| 5462 |
|
|
Related source file is "top.v".
|
| 5463 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 5464 |
|
|
Found 16-bit tristate buffer for signal .
|
| 5465 |
|
|
Found 1-bit register for signal .
|
| 5466 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 5467 |
|
|
Found 16-bit tristate buffer for signal .
|
| 5468 |
|
|
Found 1-bit register for signal .
|
| 5469 |
|
|
Found 1-bit register for signal .
|
| 5470 |
|
|
Found 1-bit register for signal .
|
| 5471 |
|
|
Summary:
|
| 5472 |
|
|
inferred 4 D-type flip-flop(s).
|
| 5473 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 5474 |
|
|
inferred 96 Tristate(s).
|
| 5475 |
|
|
Unit synthesized.
|
| 5476 |
|
|
|
| 5477 |
|
|
|
| 5478 |
|
|
Synthesizing Unit .
|
| 5479 |
|
|
Related source file is "FrontPanel.v".
|
| 5480 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 5481 |
|
|
Found finite state machine for signal .
|
| 5482 |
|
|
-----------------------------------------------------------------------
|
| 5483 |
|
|
| States | 6 |
|
| 5484 |
|
|
| Transitions | 6 |
|
| 5485 |
|
|
| Inputs | 0 |
|
| 5486 |
|
|
| Outputs | 12 |
|
| 5487 |
|
|
| Clock | clockin (rising_edge) |
|
| 5488 |
|
|
| Clock enable | select (positive) |
|
| 5489 |
|
|
| Reset | clear (positive) |
|
| 5490 |
|
|
| Reset type | synchronous |
|
| 5491 |
|
|
| Reset State | 000001 |
|
| 5492 |
|
|
| Encoding | automatic |
|
| 5493 |
|
|
| Implementation | LUT |
|
| 5494 |
|
|
-----------------------------------------------------------------------
|
| 5495 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 5496 |
|
|
Found 4-bit register for signal .
|
| 5497 |
|
|
Found 16-bit register for signal .
|
| 5498 |
|
|
Summary:
|
| 5499 |
|
|
inferred 1 Finite State Machine(s).
|
| 5500 |
|
|
inferred 16 D-type flip-flop(s).
|
| 5501 |
|
|
inferred 16 Multiplexer(s).
|
| 5502 |
|
|
Unit synthesized.
|
| 5503 |
|
|
|
| 5504 |
|
|
|
| 5505 |
|
|
Synthesizing Unit .
|
| 5506 |
|
|
Related source file is "topbox.v".
|
| 5507 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 5508 |
|
|
Found 16-bit tristate buffer for signal .
|
| 5509 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 5510 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 5511 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 5512 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 5513 |
|
|
Found 4-bit register for signal .
|
| 5514 |
|
|
Found 1-bit register for signal .
|
| 5515 |
|
|
Found 1-bit register for signal .
|
| 5516 |
|
|
Found 16-bit register for signal .
|
| 5517 |
|
|
Summary:
|
| 5518 |
|
|
inferred 22 D-type flip-flop(s).
|
| 5519 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 5520 |
|
|
inferred 6 Multiplexer(s).
|
| 5521 |
|
|
inferred 48 Tristate(s).
|
| 5522 |
|
|
Unit synthesized.
|
| 5523 |
|
|
|
| 5524 |
|
|
|
| 5525 |
|
|
=========================================================================
|
| 5526 |
|
|
* Advanced HDL Synthesis *
|
| 5527 |
|
|
=========================================================================
|
| 5528 |
|
|
|
| 5529 |
|
|
Advanced RAM inference ...
|
| 5530 |
|
|
Advanced multiplier inference ...
|
| 5531 |
|
|
Advanced Registered AddSub inference ...
|
| 5532 |
|
|
Analyzing FSM for best encoding.
|
| 5533 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 5534 |
|
|
--------------------
|
| 5535 |
|
|
State | Encoding
|
| 5536 |
|
|
--------------------
|
| 5537 |
|
|
000001 | 100000
|
| 5538 |
|
|
000010 | 010000
|
| 5539 |
|
|
000100 | 001000
|
| 5540 |
|
|
001000 | 000100
|
| 5541 |
|
|
010000 | 000010
|
| 5542 |
|
|
100000 | 000001
|
| 5543 |
|
|
--------------------
|
| 5544 |
|
|
Dynamic shift register inference ...
|
| 5545 |
|
|
|
| 5546 |
|
|
=========================================================================
|
| 5547 |
|
|
HDL Synthesis Report
|
| 5548 |
|
|
|
| 5549 |
|
|
Macro Statistics
|
| 5550 |
|
|
# FSMs : 1
|
| 5551 |
|
|
# ROMs : 1
|
| 5552 |
|
|
16x7-bit ROM : 1
|
| 5553 |
|
|
# Adders/Subtractors : 5
|
| 5554 |
|
|
12-bit adder carry out : 1
|
| 5555 |
|
|
16-bit adder carry out : 1
|
| 5556 |
|
|
17-bit subtractor : 1
|
| 5557 |
|
|
4-bit adder : 2
|
| 5558 |
|
|
# Counters : 10
|
| 5559 |
|
|
19-bit down counter : 3
|
| 5560 |
|
|
2-bit down counter : 1
|
| 5561 |
|
|
24-bit up counter : 1
|
| 5562 |
|
|
3-bit up counter : 1
|
| 5563 |
|
|
4-bit up counter : 3
|
| 5564 |
|
|
8-bit up counter : 1
|
| 5565 |
|
|
# Registers : 138
|
| 5566 |
|
|
1-bit register : 125
|
| 5567 |
|
|
12-bit register : 4
|
| 5568 |
|
|
16-bit register : 4
|
| 5569 |
|
|
4-bit register : 3
|
| 5570 |
|
|
8-bit register : 2
|
| 5571 |
|
|
# Comparators : 3
|
| 5572 |
|
|
4-bit comparator greater : 2
|
| 5573 |
|
|
4-bit comparator less : 1
|
| 5574 |
|
|
# Multiplexers : 15
|
| 5575 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 5576 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 5577 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 5578 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 5579 |
|
|
# Decoders : 1
|
| 5580 |
|
|
1-of-4 decoder : 1
|
| 5581 |
|
|
# Tristates : 97
|
| 5582 |
|
|
1-bit tristate buffer : 80
|
| 5583 |
|
|
16-bit tristate buffer : 16
|
| 5584 |
|
|
8-bit tristate buffer : 1
|
| 5585 |
|
|
# Xors : 6
|
| 5586 |
|
|
1-bit xor2 : 5
|
| 5587 |
|
|
16-bit xor2 : 1
|
| 5588 |
|
|
|
| 5589 |
|
|
=========================================================================
|
| 5590 |
|
|
|
| 5591 |
|
|
=========================================================================
|
| 5592 |
|
|
* Low Level Synthesis *
|
| 5593 |
|
|
=========================================================================
|
| 5594 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 5595 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 5596 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 5597 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 5598 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 5599 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 5600 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 5601 |
|
|
|
| 5602 |
|
|
Optimizing unit ...
|
| 5603 |
|
|
|
| 5604 |
|
|
Optimizing unit ...
|
| 5605 |
|
|
|
| 5606 |
|
|
Optimizing unit ...
|
| 5607 |
|
|
|
| 5608 |
|
|
Optimizing unit ...
|
| 5609 |
|
|
|
| 5610 |
|
|
Optimizing unit ...
|
| 5611 |
|
|
|
| 5612 |
|
|
Optimizing unit ...
|
| 5613 |
|
|
|
| 5614 |
|
|
Optimizing unit ...
|
| 5615 |
|
|
|
| 5616 |
|
|
Optimizing unit ...
|
| 5617 |
|
|
|
| 5618 |
|
|
Optimizing unit ...
|
| 5619 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 5620 |
|
|
|
| 5621 |
|
|
Mapping all equations...
|
| 5622 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 5623 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 5624 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 5625 |
|
|
Building and optimizing final netlist ...
|
| 5626 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
|
| 5627 |
|
|
FlipFlop CPU/IR/regvalue_0 has been replicated 1 time(s)
|
| 5628 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 3 time(s)
|
| 5629 |
|
|
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
|
| 5630 |
|
|
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
|
| 5631 |
|
|
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
|
| 5632 |
|
|
FlipFlop CPU/IR/regvalue_15 has been replicated 2 time(s)
|
| 5633 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
|
| 5634 |
|
|
FlipFlop CPU/IR/regvalue_5 has been replicated 1 time(s)
|
| 5635 |
|
|
FlipFlop CPU/ctl/sim/counter_0 has been replicated 1 time(s)
|
| 5636 |
|
|
FlipFlop CPU/ctl/sim/counter_1 has been replicated 2 time(s)
|
| 5637 |
|
|
FlipFlop CPU/ctl/sim/counter_2 has been replicated 1 time(s)
|
| 5638 |
|
|
|
| 5639 |
|
|
=========================================================================
|
| 5640 |
|
|
* Final Report *
|
| 5641 |
|
|
=========================================================================
|
| 5642 |
|
|
|
| 5643 |
|
|
Device utilization summary:
|
| 5644 |
|
|
---------------------------
|
| 5645 |
|
|
|
| 5646 |
|
|
Selected Device : 3s200ft256-4
|
| 5647 |
|
|
|
| 5648 |
|
|
Number of Slices: 648 out of 1920 33%
|
| 5649 |
|
|
Number of Slice Flip Flops: 385 out of 3840 10%
|
| 5650 |
|
|
Number of 4 input LUTs: 1154 out of 3840 30%
|
| 5651 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 5652 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 5653 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 5654 |
|
|
|
| 5655 |
|
|
|
| 5656 |
|
|
=========================================================================
|
| 5657 |
|
|
TIMING REPORT
|
| 5658 |
|
|
|
| 5659 |
|
|
|
| 5660 |
|
|
Clock Information:
|
| 5661 |
|
|
------------------
|
| 5662 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 5663 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 5664 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 5665 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 385 |
|
| 5666 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 5667 |
|
|
|
| 5668 |
|
|
Timing Summary:
|
| 5669 |
|
|
---------------
|
| 5670 |
|
|
Speed Grade: -4
|
| 5671 |
|
|
|
| 5672 |
|
|
Minimum period: 14.928ns (Maximum Frequency: 66.987MHz)
|
| 5673 |
|
|
Minimum input arrival time before clock: 10.934ns
|
| 5674 |
|
|
Maximum output required time after clock: 25.303ns
|
| 5675 |
|
|
Maximum combinational path delay: 14.935ns
|
| 5676 |
|
|
|
| 5677 |
|
|
=========================================================================
|
| 5678 |
|
|
|
| 5679 |
|
|
|
| 5680 |
|
|
|
| 5681 |
|
|
|
| 5682 |
|
|
Started process "Translate".
|
| 5683 |
|
|
|
| 5684 |
|
|
|
| 5685 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 5686 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 5687 |
|
|
|
| 5688 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 5689 |
|
|
|
| 5690 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 5691 |
|
|
ERROR:NgdBuild:756 - Line 213 in 'tobox.ucf': Could not find net(s) 'CPU/cp<4>'
|
| 5692 |
|
|
in the design. To suppress this error specify the correct net name or remove
|
| 5693 |
|
|
the constraint.
|
| 5694 |
|
|
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
|
| 5695 |
|
|
ERROR:NgdBuild:19 - Errors found while parsing constraint file "tobox.ucf".
|
| 5696 |
|
|
|
| 5697 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 5698 |
|
|
ERROR: NGDBUILD failed
|
| 5699 |
|
|
Process "Translate" did not complete.
|
| 5700 |
|
|
|
| 5701 |
|
|
|
| 5702 |
|
|
Project Navigator Auto-Make Log File
|
| 5703 |
|
|
-------------------------------------
|
| 5704 |
|
|
|
| 5705 |
|
|
|
| 5706 |
|
|
|
| 5707 |
|
|
|
| 5708 |
|
|
Started process "Translate".
|
| 5709 |
|
|
|
| 5710 |
|
|
|
| 5711 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 5712 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 5713 |
|
|
|
| 5714 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 5715 |
|
|
|
| 5716 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 5717 |
|
|
|
| 5718 |
|
|
Checking timing specifications ...
|
| 5719 |
|
|
Checking expanded design ...
|
| 5720 |
|
|
|
| 5721 |
|
|
NGDBUILD Design Results Summary:
|
| 5722 |
|
|
Number of errors: 0
|
| 5723 |
|
|
Number of warnings: 0
|
| 5724 |
|
|
|
| 5725 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 5726 |
|
|
|
| 5727 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 5728 |
|
|
|
| 5729 |
|
|
NGDBUILD done.
|
| 5730 |
|
|
|
| 5731 |
|
|
|
| 5732 |
|
|
|
| 5733 |
|
|
|
| 5734 |
|
|
Started process "Map".
|
| 5735 |
|
|
|
| 5736 |
|
|
Using target part "3s200ft256-4".
|
| 5737 |
|
|
Mapping design into LUTs...
|
| 5738 |
|
|
Running directed packing...
|
| 5739 |
|
|
Running delay-based LUT packing...
|
| 5740 |
|
|
Running related packing...
|
| 5741 |
|
|
|
| 5742 |
|
|
Design Summary:
|
| 5743 |
|
|
Number of errors: 0
|
| 5744 |
|
|
Number of warnings: 2
|
| 5745 |
|
|
Logic Utilization:
|
| 5746 |
|
|
Number of Slice Flip Flops: 359 out of 3,840 9%
|
| 5747 |
|
|
Number of 4 input LUTs: 1,203 out of 3,840 31%
|
| 5748 |
|
|
Logic Distribution:
|
| 5749 |
|
|
Number of occupied Slices: 714 out of 1,920 37%
|
| 5750 |
|
|
Number of Slices containing only related logic: 714 out of 714 100%
|
| 5751 |
|
|
Number of Slices containing unrelated logic: 0 out of 714 0%
|
| 5752 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 5753 |
|
|
Total Number 4 input LUTs: 1,207 out of 3,840 31%
|
| 5754 |
|
|
Number used as logic: 1,203
|
| 5755 |
|
|
Number used as a route-thru: 4
|
| 5756 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 5757 |
|
|
IOB Flip Flops: 26
|
| 5758 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 5759 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 5760 |
|
|
|
| 5761 |
|
|
Total equivalent gate count for design: 18,177
|
| 5762 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 5763 |
|
|
Peak Memory Usage: 113 MB
|
| 5764 |
|
|
|
| 5765 |
|
|
NOTES:
|
| 5766 |
|
|
|
| 5767 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 5768 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 5769 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 5770 |
|
|
the best timing performance.
|
| 5771 |
|
|
|
| 5772 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 5773 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 5774 |
|
|
related logic packing.
|
| 5775 |
|
|
|
| 5776 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 5777 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 5778 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 5779 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 5780 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 5781 |
|
|
of your design.
|
| 5782 |
|
|
|
| 5783 |
|
|
Mapping completed.
|
| 5784 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 5785 |
|
|
|
| 5786 |
|
|
|
| 5787 |
|
|
|
| 5788 |
|
|
|
| 5789 |
|
|
Started process "Place & Route".
|
| 5790 |
|
|
|
| 5791 |
|
|
|
| 5792 |
|
|
|
| 5793 |
|
|
|
| 5794 |
|
|
Constraints file: topbox.pcf.
|
| 5795 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 5796 |
|
|
C:/Xilinx71.
|
| 5797 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 5798 |
|
|
|
| 5799 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 5800 |
|
|
Celsius)
|
| 5801 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 5802 |
|
|
|
| 5803 |
|
|
|
| 5804 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 5805 |
|
|
|
| 5806 |
|
|
|
| 5807 |
|
|
Device Utilization Summary:
|
| 5808 |
|
|
|
| 5809 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 5810 |
|
|
Number of DCMs 1 out of 4 25%
|
| 5811 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 5812 |
|
|
Number of LOCed IOBs 6 out of 74 8%
|
| 5813 |
|
|
|
| 5814 |
|
|
Number of Slices 714 out of 1920 37%
|
| 5815 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 5816 |
|
|
|
| 5817 |
|
|
|
| 5818 |
|
|
|
| 5819 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 5820 |
|
|
Placer effort level (-pl): Standard (set by user)
|
| 5821 |
|
|
Placer cost table entry (-t): 1
|
| 5822 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 5823 |
|
|
|
| 5824 |
|
|
|
| 5825 |
|
|
Starting Placer
|
| 5826 |
|
|
|
| 5827 |
|
|
Phase 1.1
|
| 5828 |
|
|
Phase 1.1 (Checksum:98b020) REAL time: 1 secs
|
| 5829 |
|
|
|
| 5830 |
|
|
Phase 2.31
|
| 5831 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
|
| 5832 |
|
|
|
| 5833 |
|
|
Phase 3.2
|
| 5834 |
|
|
.
|
| 5835 |
|
|
|
| 5836 |
|
|
|
| 5837 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs
|
| 5838 |
|
|
|
| 5839 |
|
|
Phase 4.3
|
| 5840 |
|
|
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs
|
| 5841 |
|
|
|
| 5842 |
|
|
Phase 5.5
|
| 5843 |
|
|
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs
|
| 5844 |
|
|
|
| 5845 |
|
|
Phase 6.8
|
| 5846 |
|
|
.......................
|
| 5847 |
|
|
Phase 6.8 (Checksum:abcfab) REAL time: 1 secs
|
| 5848 |
|
|
|
| 5849 |
|
|
Phase 7.5
|
| 5850 |
|
|
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs
|
| 5851 |
|
|
|
| 5852 |
|
|
Phase 8.18
|
| 5853 |
|
|
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs
|
| 5854 |
|
|
|
| 5855 |
|
|
Phase 9.5
|
| 5856 |
|
|
Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs
|
| 5857 |
|
|
|
| 5858 |
|
|
Writing design to file topbox.ncd
|
| 5859 |
|
|
|
| 5860 |
|
|
|
| 5861 |
|
|
Total REAL time to Placer completion: 2 secs
|
| 5862 |
|
|
Total CPU time to Placer completion: 2 secs
|
| 5863 |
|
|
|
| 5864 |
|
|
Starting Router
|
| 5865 |
|
|
|
| 5866 |
|
|
Phase 1: 4902 unrouted; REAL time: 2 secs
|
| 5867 |
|
|
|
| 5868 |
|
|
Phase 2: 4634 unrouted; REAL time: 2 secs
|
| 5869 |
|
|
|
| 5870 |
|
|
Phase 3: 2271 unrouted; REAL time: 3 secs
|
| 5871 |
|
|
|
| 5872 |
|
|
Phase 4: 0 unrouted; REAL time: 4 secs
|
| 5873 |
|
|
|
| 5874 |
|
|
|
| 5875 |
|
|
Total REAL time to Router completion: 4 secs
|
| 5876 |
|
|
Total CPU time to Router completion: 4 secs
|
| 5877 |
|
|
|
| 5878 |
|
|
Generating "PAR" statistics.
|
| 5879 |
|
|
|
| 5880 |
|
|
**************************
|
| 5881 |
|
|
Generating Clock Report
|
| 5882 |
|
|
**************************
|
| 5883 |
|
|
|
| 5884 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 5885 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 5886 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 5887 |
|
|
| clk | BUFGMUX0| No | 248 | 0.042 | 1.052 |
|
| 5888 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 5889 |
|
|
|
| 5890 |
|
|
Generating Pad Report.
|
| 5891 |
|
|
|
| 5892 |
|
|
All signals are completely routed.
|
| 5893 |
|
|
|
| 5894 |
|
|
Total REAL time to PAR completion: 5 secs
|
| 5895 |
|
|
Total CPU time to PAR completion: 5 secs
|
| 5896 |
|
|
|
| 5897 |
|
|
Peak Memory Usage: 83 MB
|
| 5898 |
|
|
|
| 5899 |
|
|
Placement: Completed - No errors found.
|
| 5900 |
|
|
Routing: Completed - No errors found.
|
| 5901 |
|
|
|
| 5902 |
|
|
Number of error messages: 0
|
| 5903 |
|
|
Number of warning messages: 0
|
| 5904 |
|
|
Number of info messages: 1
|
| 5905 |
|
|
|
| 5906 |
|
|
Writing design to file topbox.ncd
|
| 5907 |
|
|
|
| 5908 |
|
|
|
| 5909 |
|
|
|
| 5910 |
|
|
PAR done!
|
| 5911 |
|
|
|
| 5912 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 5913 |
|
|
|
| 5914 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 5915 |
|
|
C:/Xilinx71.
|
| 5916 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 5917 |
|
|
|
| 5918 |
|
|
Analysis completed Sun Sep 24 10:35:47 2006
|
| 5919 |
|
|
--------------------------------------------------------------------------------
|
| 5920 |
|
|
|
| 5921 |
|
|
Generating Report ...
|
| 5922 |
|
|
|
| 5923 |
|
|
Number of warnings: 0
|
| 5924 |
|
|
Total time: 2 secs
|
| 5925 |
|
|
|
| 5926 |
|
|
|
| 5927 |
|
|
|
| 5928 |
|
|
|
| 5929 |
|
|
|
| 5930 |
|
|
|
| 5931 |
|
|
|
| 5932 |
|
|
Started process "Generate Programming File".
|
| 5933 |
|
|
|
| 5934 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 5935 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 5936 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 5937 |
|
|
Interactive Data Sheet.
|
| 5938 |
|
|
|
| 5939 |
|
|
|
| 5940 |
|
|
Project Navigator Auto-Make Log File
|
| 5941 |
|
|
-------------------------------------
|
| 5942 |
|
|
|
| 5943 |
|
|
|
| 5944 |
|
|
|
| 5945 |
|
|
|
| 5946 |
|
|
Started process "Synthesize".
|
| 5947 |
|
|
|
| 5948 |
|
|
|
| 5949 |
|
|
=========================================================================
|
| 5950 |
|
|
* HDL Compilation *
|
| 5951 |
|
|
=========================================================================
|
| 5952 |
|
|
Compiling verilog file "io.v"
|
| 5953 |
|
|
Module compiled
|
| 5954 |
|
|
Module compiled
|
| 5955 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 5956 |
|
|
Module compiled
|
| 5957 |
|
|
Compiling verilog file "misc.v"
|
| 5958 |
|
|
Module compiled
|
| 5959 |
|
|
Module compiled
|
| 5960 |
|
|
Module compiled
|
| 5961 |
|
|
Module compiled
|
| 5962 |
|
|
Module compiled
|
| 5963 |
|
|
Module compiled
|
| 5964 |
|
|
Compiling verilog file "alu.v"
|
| 5965 |
|
|
Module compiled
|
| 5966 |
|
|
Compiling verilog file "switchsync.v"
|
| 5967 |
|
|
Module compiled
|
| 5968 |
|
|
Compiling verilog file "jkff.v"
|
| 5969 |
|
|
Module compiled
|
| 5970 |
|
|
Compiling verilog file "control.v"
|
| 5971 |
|
|
Module compiled
|
| 5972 |
|
|
Module compiled
|
| 5973 |
|
|
Compiling verilog file "maindcm.v"
|
| 5974 |
|
|
Module compiled
|
| 5975 |
|
|
Compiling verilog file "idecode.v"
|
| 5976 |
|
|
Module compiled
|
| 5977 |
|
|
Compiling verilog file "top.v"
|
| 5978 |
|
|
Module compiled
|
| 5979 |
|
|
Compiling verilog file "rcvr.v"
|
| 5980 |
|
|
Module compiled
|
| 5981 |
|
|
Compiling verilog file "txmit.v"
|
| 5982 |
|
|
Module compiled
|
| 5983 |
|
|
Compiling verilog file "uart.v"
|
| 5984 |
|
|
Module compiled
|
| 5985 |
|
|
Compiling verilog file "topbox.v"
|
| 5986 |
|
|
Module compiled
|
| 5987 |
|
|
No errors in compilation
|
| 5988 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 5989 |
|
|
|
| 5990 |
|
|
|
| 5991 |
|
|
=========================================================================
|
| 5992 |
|
|
* HDL Analysis *
|
| 5993 |
|
|
=========================================================================
|
| 5994 |
|
|
Analyzing top module .
|
| 5995 |
|
|
Module is correct for synthesis.
|
| 5996 |
|
|
|
| 5997 |
|
|
Analyzing module .
|
| 5998 |
|
|
Module is correct for synthesis.
|
| 5999 |
|
|
|
| 6000 |
|
|
Analyzing module .
|
| 6001 |
|
|
pClockFrequency = 50
|
| 6002 |
|
|
pRefreshFrequency = 100
|
| 6003 |
|
|
pUpperLimit = 125000
|
| 6004 |
|
|
pDividerCounterBits = 24
|
| 6005 |
|
|
Module is correct for synthesis.
|
| 6006 |
|
|
|
| 6007 |
|
|
Analyzing module .
|
| 6008 |
|
|
pInitialValue = 0
|
| 6009 |
|
|
pTimerWidth = 19
|
| 6010 |
|
|
pInitialTimerValue = 500000
|
| 6011 |
|
|
Module is correct for synthesis.
|
| 6012 |
|
|
|
| 6013 |
|
|
Analyzing module .
|
| 6014 |
|
|
Module is correct for synthesis.
|
| 6015 |
|
|
|
| 6016 |
|
|
Analyzing module .
|
| 6017 |
|
|
SIZE = 16
|
| 6018 |
|
|
Module is correct for synthesis.
|
| 6019 |
|
|
|
| 6020 |
|
|
Analyzing module .
|
| 6021 |
|
|
Module is correct for synthesis.
|
| 6022 |
|
|
|
| 6023 |
|
|
Analyzing module .
|
| 6024 |
|
|
SIZE = 12
|
| 6025 |
|
|
Module is correct for synthesis.
|
| 6026 |
|
|
|
| 6027 |
|
|
Analyzing module .
|
| 6028 |
|
|
Module is correct for synthesis.
|
| 6029 |
|
|
|
| 6030 |
|
|
Analyzing module .
|
| 6031 |
|
|
VALUE = 0000000000000001
|
| 6032 |
|
|
Module is correct for synthesis.
|
| 6033 |
|
|
|
| 6034 |
|
|
Analyzing module .
|
| 6035 |
|
|
Module is correct for synthesis.
|
| 6036 |
|
|
|
| 6037 |
|
|
Analyzing module .
|
| 6038 |
|
|
VALUE = 1111111111111111
|
| 6039 |
|
|
Module is correct for synthesis.
|
| 6040 |
|
|
|
| 6041 |
|
|
Analyzing module .
|
| 6042 |
|
|
Module is correct for synthesis.
|
| 6043 |
|
|
|
| 6044 |
|
|
Analyzing module .
|
| 6045 |
|
|
VALUE = 0000000000000000
|
| 6046 |
|
|
Module is correct for synthesis.
|
| 6047 |
|
|
|
| 6048 |
|
|
Analyzing module .
|
| 6049 |
|
|
Module is correct for synthesis.
|
| 6050 |
|
|
|
| 6051 |
|
|
Analyzing module .
|
| 6052 |
|
|
Module is correct for synthesis.
|
| 6053 |
|
|
|
| 6054 |
|
|
Analyzing module .
|
| 6055 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 6056 |
|
|
Module is correct for synthesis.
|
| 6057 |
|
|
|
| 6058 |
|
|
Analyzing module .
|
| 6059 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 6060 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 6061 |
|
|
Module is correct for synthesis.
|
| 6062 |
|
|
|
| 6063 |
|
|
Analyzing module .
|
| 6064 |
|
|
Module is correct for synthesis.
|
| 6065 |
|
|
|
| 6066 |
|
|
Analyzing module .
|
| 6067 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6068 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6069 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6070 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6071 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6072 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6073 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6074 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6075 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6076 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6077 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6078 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6079 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6080 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6081 |
|
|
Module is correct for synthesis.
|
| 6082 |
|
|
|
| 6083 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 6084 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 6085 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 6086 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 6087 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 6088 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 6089 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 6090 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 6091 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 6092 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 6093 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 6094 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 6095 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 6096 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 6097 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 6098 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 6099 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 6100 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 6101 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 6102 |
|
|
Analyzing module .
|
| 6103 |
|
|
Module is correct for synthesis.
|
| 6104 |
|
|
|
| 6105 |
|
|
Analyzing module .
|
| 6106 |
|
|
XTAL_CLK = 35000000
|
| 6107 |
|
|
BAUD = 9600
|
| 6108 |
|
|
CLK_DIV = 113
|
| 6109 |
|
|
CW = 8
|
| 6110 |
|
|
Module is correct for synthesis.
|
| 6111 |
|
|
|
| 6112 |
|
|
Analyzing module .
|
| 6113 |
|
|
Module is correct for synthesis.
|
| 6114 |
|
|
|
| 6115 |
|
|
Analyzing module .
|
| 6116 |
|
|
Module is correct for synthesis.
|
| 6117 |
|
|
|
| 6118 |
|
|
|
| 6119 |
|
|
=========================================================================
|
| 6120 |
|
|
* HDL Synthesis *
|
| 6121 |
|
|
=========================================================================
|
| 6122 |
|
|
|
| 6123 |
|
|
Synthesizing Unit .
|
| 6124 |
|
|
Related source file is "txmit.v".
|
| 6125 |
|
|
Found 1-bit register for signal .
|
| 6126 |
|
|
Found 1-bit register for signal .
|
| 6127 |
|
|
Found 1-bit register for signal .
|
| 6128 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 6129 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 6130 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 6131 |
|
|
Found 1-bit register for signal .
|
| 6132 |
|
|
Found 1-bit register for signal .
|
| 6133 |
|
|
Found 4-bit up counter for signal .
|
| 6134 |
|
|
Found 4-bit up counter for signal .
|
| 6135 |
|
|
Found 8-bit register for signal .
|
| 6136 |
|
|
Found 8-bit register for signal .
|
| 6137 |
|
|
Summary:
|
| 6138 |
|
|
inferred 2 Counter(s).
|
| 6139 |
|
|
inferred 21 D-type flip-flop(s).
|
| 6140 |
|
|
inferred 2 Comparator(s).
|
| 6141 |
|
|
inferred 1 Multiplexer(s).
|
| 6142 |
|
|
Unit synthesized.
|
| 6143 |
|
|
|
| 6144 |
|
|
|
| 6145 |
|
|
Synthesizing Unit .
|
| 6146 |
|
|
Related source file is "rcvr.v".
|
| 6147 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 6148 |
|
|
Found 1-bit register for signal .
|
| 6149 |
|
|
Found 1-bit register for signal .
|
| 6150 |
|
|
Found 1-bit register for signal .
|
| 6151 |
|
|
Found 8-bit tristate buffer for signal .
|
| 6152 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 6153 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 6154 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 6155 |
|
|
Found 1-bit register for signal .
|
| 6156 |
|
|
Found 1-bit register for signal .
|
| 6157 |
|
|
Found 4-bit register for signal .
|
| 6158 |
|
|
Found 4-bit up counter for signal .
|
| 6159 |
|
|
Found 8-bit register for signal .
|
| 6160 |
|
|
Found 7-bit register for signal >.
|
| 6161 |
|
|
Found 1-bit register for signal .
|
| 6162 |
|
|
Found 1-bit register for signal .
|
| 6163 |
|
|
Summary:
|
| 6164 |
|
|
inferred 1 Counter(s).
|
| 6165 |
|
|
inferred 26 D-type flip-flop(s).
|
| 6166 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 6167 |
|
|
inferred 1 Comparator(s).
|
| 6168 |
|
|
inferred 1 Multiplexer(s).
|
| 6169 |
|
|
inferred 8 Tristate(s).
|
| 6170 |
|
|
Unit synthesized.
|
| 6171 |
|
|
|
| 6172 |
|
|
|
| 6173 |
|
|
Synthesizing Unit .
|
| 6174 |
|
|
Related source file is "jkff.v".
|
| 6175 |
|
|
Found 1-bit register for signal .
|
| 6176 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 6177 |
|
|
Summary:
|
| 6178 |
|
|
inferred 1 D-type flip-flop(s).
|
| 6179 |
|
|
inferred 1 Multiplexer(s).
|
| 6180 |
|
|
Unit synthesized.
|
| 6181 |
|
|
|
| 6182 |
|
|
|
| 6183 |
|
|
Synthesizing Unit .
|
| 6184 |
|
|
Related source file is "switchsync.v".
|
| 6185 |
|
|
Found 1-bit register for signal .
|
| 6186 |
|
|
Found 1-bit register for signal .
|
| 6187 |
|
|
Summary:
|
| 6188 |
|
|
inferred 2 D-type flip-flop(s).
|
| 6189 |
|
|
Unit synthesized.
|
| 6190 |
|
|
|
| 6191 |
|
|
|
| 6192 |
|
|
Synthesizing Unit .
|
| 6193 |
|
|
Related source file is "maindcm.v".
|
| 6194 |
|
|
Unit synthesized.
|
| 6195 |
|
|
|
| 6196 |
|
|
|
| 6197 |
|
|
Synthesizing Unit .
|
| 6198 |
|
|
Related source file is "control.v".
|
| 6199 |
|
|
Found 1-bit register for signal .
|
| 6200 |
|
|
Found 1-bit register for signal .
|
| 6201 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 6202 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 6203 |
|
|
Found 3-bit up counter for signal .
|
| 6204 |
|
|
Summary:
|
| 6205 |
|
|
inferred 1 Counter(s).
|
| 6206 |
|
|
inferred 2 D-type flip-flop(s).
|
| 6207 |
|
|
inferred 2 Multiplexer(s).
|
| 6208 |
|
|
Unit synthesized.
|
| 6209 |
|
|
|
| 6210 |
|
|
|
| 6211 |
|
|
Synthesizing Unit .
|
| 6212 |
|
|
Related source file is "misc.v".
|
| 6213 |
|
|
Found 16-bit tristate buffer for signal .
|
| 6214 |
|
|
Summary:
|
| 6215 |
|
|
inferred 16 Tristate(s).
|
| 6216 |
|
|
Unit synthesized.
|
| 6217 |
|
|
|
| 6218 |
|
|
|
| 6219 |
|
|
Synthesizing Unit .
|
| 6220 |
|
|
Related source file is "misc.v".
|
| 6221 |
|
|
Found 16-bit tristate buffer for signal .
|
| 6222 |
|
|
Summary:
|
| 6223 |
|
|
inferred 16 Tristate(s).
|
| 6224 |
|
|
Unit synthesized.
|
| 6225 |
|
|
|
| 6226 |
|
|
|
| 6227 |
|
|
Synthesizing Unit .
|
| 6228 |
|
|
Related source file is "misc.v".
|
| 6229 |
|
|
Found 16-bit tristate buffer for signal .
|
| 6230 |
|
|
Summary:
|
| 6231 |
|
|
inferred 16 Tristate(s).
|
| 6232 |
|
|
Unit synthesized.
|
| 6233 |
|
|
|
| 6234 |
|
|
|
| 6235 |
|
|
Synthesizing Unit .
|
| 6236 |
|
|
Related source file is "misc.v".
|
| 6237 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 6238 |
|
|
Found 16-bit tristate buffer for signal .
|
| 6239 |
|
|
Found 12-bit register for signal .
|
| 6240 |
|
|
Summary:
|
| 6241 |
|
|
inferred 12 D-type flip-flop(s).
|
| 6242 |
|
|
inferred 16 Tristate(s).
|
| 6243 |
|
|
Unit synthesized.
|
| 6244 |
|
|
|
| 6245 |
|
|
|
| 6246 |
|
|
Synthesizing Unit .
|
| 6247 |
|
|
Related source file is "idecode.v".
|
| 6248 |
|
|
Unit synthesized.
|
| 6249 |
|
|
|
| 6250 |
|
|
|
| 6251 |
|
|
Synthesizing Unit .
|
| 6252 |
|
|
Related source file is "control.v".
|
| 6253 |
|
|
Unit synthesized.
|
| 6254 |
|
|
|
| 6255 |
|
|
|
| 6256 |
|
|
Synthesizing Unit .
|
| 6257 |
|
|
Related source file is "alu.v".
|
| 6258 |
|
|
Found 16-bit tristate buffer for signal .
|
| 6259 |
|
|
Found 17-bit subtractor for signal <$AUX_108>.
|
| 6260 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 6261 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 6262 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 6263 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 6264 |
|
|
Summary:
|
| 6265 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 6266 |
|
|
inferred 16 Tristate(s).
|
| 6267 |
|
|
Unit synthesized.
|
| 6268 |
|
|
|
| 6269 |
|
|
|
| 6270 |
|
|
Synthesizing Unit .
|
| 6271 |
|
|
Related source file is "misc.v".
|
| 6272 |
|
|
Unit synthesized.
|
| 6273 |
|
|
|
| 6274 |
|
|
|
| 6275 |
|
|
Synthesizing Unit .
|
| 6276 |
|
|
Related source file is "misc.v".
|
| 6277 |
|
|
Unit synthesized.
|
| 6278 |
|
|
|
| 6279 |
|
|
|
| 6280 |
|
|
Synthesizing Unit .
|
| 6281 |
|
|
Related source file is "misc.v".
|
| 6282 |
|
|
Unit synthesized.
|
| 6283 |
|
|
|
| 6284 |
|
|
|
| 6285 |
|
|
Synthesizing Unit .
|
| 6286 |
|
|
Related source file is "misc.v".
|
| 6287 |
|
|
Unit synthesized.
|
| 6288 |
|
|
|
| 6289 |
|
|
|
| 6290 |
|
|
Synthesizing Unit .
|
| 6291 |
|
|
Related source file is "misc.v".
|
| 6292 |
|
|
Found 16-bit tristate buffer for signal .
|
| 6293 |
|
|
Found 16-bit register for signal .
|
| 6294 |
|
|
Summary:
|
| 6295 |
|
|
inferred 16 D-type flip-flop(s).
|
| 6296 |
|
|
inferred 16 Tristate(s).
|
| 6297 |
|
|
Unit synthesized.
|
| 6298 |
|
|
|
| 6299 |
|
|
|
| 6300 |
|
|
Synthesizing Unit .
|
| 6301 |
|
|
Related source file is "io.v".
|
| 6302 |
|
|
Found 1-bit register for signal .
|
| 6303 |
|
|
Found 1-bit register for signal .
|
| 6304 |
|
|
Found 1-bit register for signal .
|
| 6305 |
|
|
Found 1-bit register for signal .
|
| 6306 |
|
|
Found 1-bit register for signal .
|
| 6307 |
|
|
Found 1-bit register for signal .
|
| 6308 |
|
|
Found 19-bit down counter for signal .
|
| 6309 |
|
|
Found 1-bit register for signal .
|
| 6310 |
|
|
Found 1-bit xor2 for signal .
|
| 6311 |
|
|
Summary:
|
| 6312 |
|
|
inferred 1 Counter(s).
|
| 6313 |
|
|
inferred 7 D-type flip-flop(s).
|
| 6314 |
|
|
Unit synthesized.
|
| 6315 |
|
|
|
| 6316 |
|
|
|
| 6317 |
|
|
Synthesizing Unit .
|
| 6318 |
|
|
Related source file is "io.v".
|
| 6319 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 6320 |
|
|
Found 1-bit register for signal .
|
| 6321 |
|
|
Found 1-bit register for signal .
|
| 6322 |
|
|
Found 1-bit register for signal .
|
| 6323 |
|
|
Found 1-bit register for signal .
|
| 6324 |
|
|
Found 1-bit register for signal .
|
| 6325 |
|
|
Found 1-bit register for signal .
|
| 6326 |
|
|
Found 1-bit register for signal .
|
| 6327 |
|
|
Found 1-bit register for signal .
|
| 6328 |
|
|
Found 1-bit register for signal .
|
| 6329 |
|
|
Found 1-bit register for signal .
|
| 6330 |
|
|
Found 1-bit register for signal .
|
| 6331 |
|
|
Found 1-bit register for signal .
|
| 6332 |
|
|
Found 24-bit up counter for signal .
|
| 6333 |
|
|
Found 1-of-4 decoder for signal .
|
| 6334 |
|
|
Found 2-bit down counter for signal .
|
| 6335 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 6336 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 6337 |
|
|
Summary:
|
| 6338 |
|
|
inferred 1 ROM(s).
|
| 6339 |
|
|
inferred 2 Counter(s).
|
| 6340 |
|
|
inferred 12 D-type flip-flop(s).
|
| 6341 |
|
|
inferred 9 Multiplexer(s).
|
| 6342 |
|
|
inferred 1 Decoder(s).
|
| 6343 |
|
|
Unit synthesized.
|
| 6344 |
|
|
|
| 6345 |
|
|
|
| 6346 |
|
|
Synthesizing Unit .
|
| 6347 |
|
|
Related source file is "uart.v".
|
| 6348 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 6349 |
|
|
Found 1-bit register for signal .
|
| 6350 |
|
|
Found 8-bit up counter for signal .
|
| 6351 |
|
|
Found 1-bit register for signal .
|
| 6352 |
|
|
Summary:
|
| 6353 |
|
|
inferred 1 Counter(s).
|
| 6354 |
|
|
inferred 2 D-type flip-flop(s).
|
| 6355 |
|
|
inferred 1 Multiplexer(s).
|
| 6356 |
|
|
Unit synthesized.
|
| 6357 |
|
|
|
| 6358 |
|
|
|
| 6359 |
|
|
Synthesizing Unit .
|
| 6360 |
|
|
Related source file is "top.v".
|
| 6361 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 6362 |
|
|
Found 16-bit tristate buffer for signal .
|
| 6363 |
|
|
Found 1-bit register for signal .
|
| 6364 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 6365 |
|
|
Found 16-bit tristate buffer for signal .
|
| 6366 |
|
|
Found 1-bit register for signal .
|
| 6367 |
|
|
Found 1-bit register for signal .
|
| 6368 |
|
|
Found 1-bit register for signal .
|
| 6369 |
|
|
Summary:
|
| 6370 |
|
|
inferred 4 D-type flip-flop(s).
|
| 6371 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 6372 |
|
|
inferred 96 Tristate(s).
|
| 6373 |
|
|
Unit synthesized.
|
| 6374 |
|
|
|
| 6375 |
|
|
|
| 6376 |
|
|
Synthesizing Unit .
|
| 6377 |
|
|
Related source file is "FrontPanel.v".
|
| 6378 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 6379 |
|
|
Found finite state machine for signal .
|
| 6380 |
|
|
-----------------------------------------------------------------------
|
| 6381 |
|
|
| States | 6 |
|
| 6382 |
|
|
| Transitions | 6 |
|
| 6383 |
|
|
| Inputs | 0 |
|
| 6384 |
|
|
| Outputs | 12 |
|
| 6385 |
|
|
| Clock | clockin (rising_edge) |
|
| 6386 |
|
|
| Clock enable | select (positive) |
|
| 6387 |
|
|
| Reset | clear (positive) |
|
| 6388 |
|
|
| Reset type | synchronous |
|
| 6389 |
|
|
| Reset State | 000001 |
|
| 6390 |
|
|
| Encoding | automatic |
|
| 6391 |
|
|
| Implementation | LUT |
|
| 6392 |
|
|
-----------------------------------------------------------------------
|
| 6393 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 6394 |
|
|
Found 4-bit register for signal .
|
| 6395 |
|
|
Found 16-bit register for signal .
|
| 6396 |
|
|
Summary:
|
| 6397 |
|
|
inferred 1 Finite State Machine(s).
|
| 6398 |
|
|
inferred 16 D-type flip-flop(s).
|
| 6399 |
|
|
inferred 16 Multiplexer(s).
|
| 6400 |
|
|
Unit synthesized.
|
| 6401 |
|
|
|
| 6402 |
|
|
|
| 6403 |
|
|
Synthesizing Unit .
|
| 6404 |
|
|
Related source file is "topbox.v".
|
| 6405 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 6406 |
|
|
Found 16-bit tristate buffer for signal .
|
| 6407 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 6408 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 6409 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 6410 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 6411 |
|
|
Found 4-bit register for signal .
|
| 6412 |
|
|
Found 1-bit register for signal .
|
| 6413 |
|
|
Found 1-bit register for signal .
|
| 6414 |
|
|
Found 16-bit register for signal .
|
| 6415 |
|
|
Summary:
|
| 6416 |
|
|
inferred 22 D-type flip-flop(s).
|
| 6417 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 6418 |
|
|
inferred 6 Multiplexer(s).
|
| 6419 |
|
|
inferred 48 Tristate(s).
|
| 6420 |
|
|
Unit synthesized.
|
| 6421 |
|
|
|
| 6422 |
|
|
|
| 6423 |
|
|
=========================================================================
|
| 6424 |
|
|
* Advanced HDL Synthesis *
|
| 6425 |
|
|
=========================================================================
|
| 6426 |
|
|
|
| 6427 |
|
|
Advanced RAM inference ...
|
| 6428 |
|
|
Advanced multiplier inference ...
|
| 6429 |
|
|
Advanced Registered AddSub inference ...
|
| 6430 |
|
|
Analyzing FSM for best encoding.
|
| 6431 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 6432 |
|
|
--------------------
|
| 6433 |
|
|
State | Encoding
|
| 6434 |
|
|
--------------------
|
| 6435 |
|
|
000001 | 100000
|
| 6436 |
|
|
000010 | 010000
|
| 6437 |
|
|
000100 | 001000
|
| 6438 |
|
|
001000 | 000100
|
| 6439 |
|
|
010000 | 000010
|
| 6440 |
|
|
100000 | 000001
|
| 6441 |
|
|
--------------------
|
| 6442 |
|
|
Dynamic shift register inference ...
|
| 6443 |
|
|
|
| 6444 |
|
|
=========================================================================
|
| 6445 |
|
|
HDL Synthesis Report
|
| 6446 |
|
|
|
| 6447 |
|
|
Macro Statistics
|
| 6448 |
|
|
# FSMs : 1
|
| 6449 |
|
|
# ROMs : 1
|
| 6450 |
|
|
16x7-bit ROM : 1
|
| 6451 |
|
|
# Adders/Subtractors : 5
|
| 6452 |
|
|
12-bit adder carry out : 1
|
| 6453 |
|
|
16-bit adder carry out : 1
|
| 6454 |
|
|
17-bit subtractor : 1
|
| 6455 |
|
|
4-bit adder : 2
|
| 6456 |
|
|
# Counters : 10
|
| 6457 |
|
|
19-bit down counter : 3
|
| 6458 |
|
|
2-bit down counter : 1
|
| 6459 |
|
|
24-bit up counter : 1
|
| 6460 |
|
|
3-bit up counter : 1
|
| 6461 |
|
|
4-bit up counter : 3
|
| 6462 |
|
|
8-bit up counter : 1
|
| 6463 |
|
|
# Registers : 138
|
| 6464 |
|
|
1-bit register : 125
|
| 6465 |
|
|
12-bit register : 4
|
| 6466 |
|
|
16-bit register : 4
|
| 6467 |
|
|
4-bit register : 3
|
| 6468 |
|
|
8-bit register : 2
|
| 6469 |
|
|
# Comparators : 3
|
| 6470 |
|
|
4-bit comparator greater : 2
|
| 6471 |
|
|
4-bit comparator less : 1
|
| 6472 |
|
|
# Multiplexers : 15
|
| 6473 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 6474 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 6475 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 6476 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 6477 |
|
|
# Decoders : 1
|
| 6478 |
|
|
1-of-4 decoder : 1
|
| 6479 |
|
|
# Tristates : 97
|
| 6480 |
|
|
1-bit tristate buffer : 80
|
| 6481 |
|
|
16-bit tristate buffer : 16
|
| 6482 |
|
|
8-bit tristate buffer : 1
|
| 6483 |
|
|
# Xors : 6
|
| 6484 |
|
|
1-bit xor2 : 5
|
| 6485 |
|
|
16-bit xor2 : 1
|
| 6486 |
|
|
|
| 6487 |
|
|
=========================================================================
|
| 6488 |
|
|
|
| 6489 |
|
|
=========================================================================
|
| 6490 |
|
|
* Low Level Synthesis *
|
| 6491 |
|
|
=========================================================================
|
| 6492 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 6493 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 6494 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 6495 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 6496 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 6497 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 6498 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 6499 |
|
|
|
| 6500 |
|
|
Optimizing unit ...
|
| 6501 |
|
|
|
| 6502 |
|
|
Optimizing unit ...
|
| 6503 |
|
|
|
| 6504 |
|
|
Optimizing unit ...
|
| 6505 |
|
|
|
| 6506 |
|
|
Optimizing unit ...
|
| 6507 |
|
|
|
| 6508 |
|
|
Optimizing unit ...
|
| 6509 |
|
|
|
| 6510 |
|
|
Optimizing unit ...
|
| 6511 |
|
|
|
| 6512 |
|
|
Optimizing unit ...
|
| 6513 |
|
|
|
| 6514 |
|
|
Optimizing unit ...
|
| 6515 |
|
|
|
| 6516 |
|
|
Optimizing unit ...
|
| 6517 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 6518 |
|
|
|
| 6519 |
|
|
Mapping all equations...
|
| 6520 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 6521 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 6522 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 6523 |
|
|
Building and optimizing final netlist ...
|
| 6524 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
|
| 6525 |
|
|
|
| 6526 |
|
|
=========================================================================
|
| 6527 |
|
|
* Final Report *
|
| 6528 |
|
|
=========================================================================
|
| 6529 |
|
|
|
| 6530 |
|
|
Device utilization summary:
|
| 6531 |
|
|
---------------------------
|
| 6532 |
|
|
|
| 6533 |
|
|
Selected Device : 3s200ft256-4
|
| 6534 |
|
|
|
| 6535 |
|
|
Number of Slices: 609 out of 1920 31%
|
| 6536 |
|
|
Number of Slice Flip Flops: 368 out of 3840 9%
|
| 6537 |
|
|
Number of 4 input LUTs: 1078 out of 3840 28%
|
| 6538 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 6539 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 6540 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 6541 |
|
|
|
| 6542 |
|
|
|
| 6543 |
|
|
=========================================================================
|
| 6544 |
|
|
TIMING REPORT
|
| 6545 |
|
|
|
| 6546 |
|
|
|
| 6547 |
|
|
Clock Information:
|
| 6548 |
|
|
------------------
|
| 6549 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 6550 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 6551 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 6552 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 368 |
|
| 6553 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 6554 |
|
|
|
| 6555 |
|
|
Timing Summary:
|
| 6556 |
|
|
---------------
|
| 6557 |
|
|
Speed Grade: -4
|
| 6558 |
|
|
|
| 6559 |
|
|
Minimum period: 14.634ns (Maximum Frequency: 68.333MHz)
|
| 6560 |
|
|
Minimum input arrival time before clock: 10.576ns
|
| 6561 |
|
|
Maximum output required time after clock: 24.823ns
|
| 6562 |
|
|
Maximum combinational path delay: 14.545ns
|
| 6563 |
|
|
|
| 6564 |
|
|
=========================================================================
|
| 6565 |
|
|
|
| 6566 |
|
|
|
| 6567 |
|
|
Project Navigator Auto-Make Log File
|
| 6568 |
|
|
-------------------------------------
|
| 6569 |
|
|
|
| 6570 |
|
|
|
| 6571 |
|
|
|
| 6572 |
|
|
|
| 6573 |
|
|
Started process "Translate".
|
| 6574 |
|
|
|
| 6575 |
|
|
|
| 6576 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 6577 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 6578 |
|
|
|
| 6579 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 6580 |
|
|
|
| 6581 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 6582 |
|
|
|
| 6583 |
|
|
Checking timing specifications ...
|
| 6584 |
|
|
Checking expanded design ...
|
| 6585 |
|
|
|
| 6586 |
|
|
NGDBUILD Design Results Summary:
|
| 6587 |
|
|
Number of errors: 0
|
| 6588 |
|
|
Number of warnings: 0
|
| 6589 |
|
|
|
| 6590 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 6591 |
|
|
|
| 6592 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 6593 |
|
|
|
| 6594 |
|
|
NGDBUILD done.
|
| 6595 |
|
|
|
| 6596 |
|
|
|
| 6597 |
|
|
|
| 6598 |
|
|
|
| 6599 |
|
|
Started process "Map".
|
| 6600 |
|
|
|
| 6601 |
|
|
Using target part "3s200ft256-4".
|
| 6602 |
|
|
Mapping design into LUTs...
|
| 6603 |
|
|
Running directed packing...
|
| 6604 |
|
|
Running delay-based LUT packing...
|
| 6605 |
|
|
Running related packing...
|
| 6606 |
|
|
|
| 6607 |
|
|
Design Summary:
|
| 6608 |
|
|
Number of errors: 0
|
| 6609 |
|
|
Number of warnings: 2
|
| 6610 |
|
|
Logic Utilization:
|
| 6611 |
|
|
Number of Slice Flip Flops: 342 out of 3,840 8%
|
| 6612 |
|
|
Number of 4 input LUTs: 1,128 out of 3,840 29%
|
| 6613 |
|
|
Logic Distribution:
|
| 6614 |
|
|
Number of occupied Slices: 661 out of 1,920 34%
|
| 6615 |
|
|
Number of Slices containing only related logic: 661 out of 661 100%
|
| 6616 |
|
|
Number of Slices containing unrelated logic: 0 out of 661 0%
|
| 6617 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 6618 |
|
|
Total Number 4 input LUTs: 1,132 out of 3,840 29%
|
| 6619 |
|
|
Number used as logic: 1,128
|
| 6620 |
|
|
Number used as a route-thru: 4
|
| 6621 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 6622 |
|
|
IOB Flip Flops: 26
|
| 6623 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 6624 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 6625 |
|
|
|
| 6626 |
|
|
Total equivalent gate count for design: 17,594
|
| 6627 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 6628 |
|
|
Peak Memory Usage: 114 MB
|
| 6629 |
|
|
|
| 6630 |
|
|
NOTES:
|
| 6631 |
|
|
|
| 6632 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 6633 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 6634 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 6635 |
|
|
the best timing performance.
|
| 6636 |
|
|
|
| 6637 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 6638 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 6639 |
|
|
related logic packing.
|
| 6640 |
|
|
|
| 6641 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 6642 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 6643 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 6644 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 6645 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 6646 |
|
|
of your design.
|
| 6647 |
|
|
|
| 6648 |
|
|
Mapping completed.
|
| 6649 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 6650 |
|
|
|
| 6651 |
|
|
|
| 6652 |
|
|
|
| 6653 |
|
|
|
| 6654 |
|
|
Started process "Place & Route".
|
| 6655 |
|
|
|
| 6656 |
|
|
|
| 6657 |
|
|
|
| 6658 |
|
|
|
| 6659 |
|
|
Constraints file: topbox.pcf.
|
| 6660 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 6661 |
|
|
C:/Xilinx71.
|
| 6662 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 6663 |
|
|
|
| 6664 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 6665 |
|
|
Celsius)
|
| 6666 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 6667 |
|
|
|
| 6668 |
|
|
|
| 6669 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 6670 |
|
|
|
| 6671 |
|
|
|
| 6672 |
|
|
Device Utilization Summary:
|
| 6673 |
|
|
|
| 6674 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 6675 |
|
|
Number of DCMs 1 out of 4 25%
|
| 6676 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 6677 |
|
|
Number of LOCed IOBs 6 out of 74 8%
|
| 6678 |
|
|
|
| 6679 |
|
|
Number of Slices 661 out of 1920 34%
|
| 6680 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 6681 |
|
|
|
| 6682 |
|
|
|
| 6683 |
|
|
|
| 6684 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 6685 |
|
|
Placer effort level (-pl): Standard (set by user)
|
| 6686 |
|
|
Placer cost table entry (-t): 1
|
| 6687 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 6688 |
|
|
|
| 6689 |
|
|
|
| 6690 |
|
|
Starting Placer
|
| 6691 |
|
|
|
| 6692 |
|
|
Phase 1.1
|
| 6693 |
|
|
Phase 1.1 (Checksum:98ae43) REAL time: 1 secs
|
| 6694 |
|
|
|
| 6695 |
|
|
Phase 2.31
|
| 6696 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
|
| 6697 |
|
|
|
| 6698 |
|
|
Phase 3.2
|
| 6699 |
|
|
.
|
| 6700 |
|
|
|
| 6701 |
|
|
|
| 6702 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs
|
| 6703 |
|
|
|
| 6704 |
|
|
Phase 4.3
|
| 6705 |
|
|
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs
|
| 6706 |
|
|
|
| 6707 |
|
|
Phase 5.5
|
| 6708 |
|
|
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs
|
| 6709 |
|
|
|
| 6710 |
|
|
Phase 6.8
|
| 6711 |
|
|
..................................
|
| 6712 |
|
|
Phase 6.8 (Checksum:a893f9) REAL time: 1 secs
|
| 6713 |
|
|
|
| 6714 |
|
|
Phase 7.5
|
| 6715 |
|
|
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs
|
| 6716 |
|
|
|
| 6717 |
|
|
Phase 8.18
|
| 6718 |
|
|
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs
|
| 6719 |
|
|
|
| 6720 |
|
|
Phase 9.5
|
| 6721 |
|
|
Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs
|
| 6722 |
|
|
|
| 6723 |
|
|
Writing design to file topbox.ncd
|
| 6724 |
|
|
|
| 6725 |
|
|
|
| 6726 |
|
|
Total REAL time to Placer completion: 2 secs
|
| 6727 |
|
|
Total CPU time to Placer completion: 2 secs
|
| 6728 |
|
|
|
| 6729 |
|
|
Starting Router
|
| 6730 |
|
|
|
| 6731 |
|
|
Phase 1: 4597 unrouted; REAL time: 2 secs
|
| 6732 |
|
|
|
| 6733 |
|
|
Phase 2: 4346 unrouted; REAL time: 2 secs
|
| 6734 |
|
|
|
| 6735 |
|
|
Phase 3: 2122 unrouted; REAL time: 3 secs
|
| 6736 |
|
|
|
| 6737 |
|
|
Phase 4: 0 unrouted; REAL time: 4 secs
|
| 6738 |
|
|
|
| 6739 |
|
|
|
| 6740 |
|
|
Total REAL time to Router completion: 4 secs
|
| 6741 |
|
|
Total CPU time to Router completion: 4 secs
|
| 6742 |
|
|
|
| 6743 |
|
|
Generating "PAR" statistics.
|
| 6744 |
|
|
|
| 6745 |
|
|
**************************
|
| 6746 |
|
|
Generating Clock Report
|
| 6747 |
|
|
**************************
|
| 6748 |
|
|
|
| 6749 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 6750 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 6751 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 6752 |
|
|
| clk | BUFGMUX0| No | 231 | 0.042 | 1.052 |
|
| 6753 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 6754 |
|
|
|
| 6755 |
|
|
Generating Pad Report.
|
| 6756 |
|
|
|
| 6757 |
|
|
All signals are completely routed.
|
| 6758 |
|
|
|
| 6759 |
|
|
Total REAL time to PAR completion: 4 secs
|
| 6760 |
|
|
Total CPU time to PAR completion: 4 secs
|
| 6761 |
|
|
|
| 6762 |
|
|
Peak Memory Usage: 82 MB
|
| 6763 |
|
|
|
| 6764 |
|
|
Placement: Completed - No errors found.
|
| 6765 |
|
|
Routing: Completed - No errors found.
|
| 6766 |
|
|
|
| 6767 |
|
|
Number of error messages: 0
|
| 6768 |
|
|
Number of warning messages: 0
|
| 6769 |
|
|
Number of info messages: 1
|
| 6770 |
|
|
|
| 6771 |
|
|
Writing design to file topbox.ncd
|
| 6772 |
|
|
|
| 6773 |
|
|
|
| 6774 |
|
|
|
| 6775 |
|
|
PAR done!
|
| 6776 |
|
|
|
| 6777 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 6778 |
|
|
|
| 6779 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 6780 |
|
|
C:/Xilinx71.
|
| 6781 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 6782 |
|
|
|
| 6783 |
|
|
Analysis completed Sun Sep 24 10:39:12 2006
|
| 6784 |
|
|
--------------------------------------------------------------------------------
|
| 6785 |
|
|
|
| 6786 |
|
|
Generating Report ...
|
| 6787 |
|
|
|
| 6788 |
|
|
Number of warnings: 0
|
| 6789 |
|
|
Total time: 2 secs
|
| 6790 |
|
|
|
| 6791 |
|
|
|
| 6792 |
|
|
|
| 6793 |
|
|
|
| 6794 |
|
|
|
| 6795 |
|
|
|
| 6796 |
|
|
|
| 6797 |
|
|
Started process "Generate Programming File".
|
| 6798 |
|
|
|
| 6799 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 6800 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 6801 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 6802 |
|
|
Interactive Data Sheet.
|
| 6803 |
|
|
|
| 6804 |
|
|
|
| 6805 |
|
|
Project Navigator Auto-Make Log File
|
| 6806 |
|
|
-------------------------------------
|
| 6807 |
|
|
|
| 6808 |
|
|
|
| 6809 |
|
|
|
| 6810 |
|
|
|
| 6811 |
|
|
Started process "View HDL Source".
|
| 6812 |
|
|
|
| 6813 |
|
|
xaw2verilog: Completed successfully
|
| 6814 |
|
|
|
| 6815 |
|
|
|
| 6816 |
|
|
|
| 6817 |
|
|
|
| 6818 |
|
|
|
| 6819 |
|
|
|
| 6820 |
|
|
|
| 6821 |
|
|
|
| 6822 |
|
|
|
| 6823 |
|
|
|
| 6824 |
|
|
Started process "Synthesize".
|
| 6825 |
|
|
|
| 6826 |
|
|
|
| 6827 |
|
|
=========================================================================
|
| 6828 |
|
|
* HDL Compilation *
|
| 6829 |
|
|
=========================================================================
|
| 6830 |
|
|
Compiling verilog file "io.v"
|
| 6831 |
|
|
Module compiled
|
| 6832 |
|
|
Module compiled
|
| 6833 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 6834 |
|
|
Module compiled
|
| 6835 |
|
|
Compiling verilog file "misc.v"
|
| 6836 |
|
|
Module compiled
|
| 6837 |
|
|
Module compiled
|
| 6838 |
|
|
Module compiled
|
| 6839 |
|
|
Module compiled
|
| 6840 |
|
|
Module compiled
|
| 6841 |
|
|
Module compiled
|
| 6842 |
|
|
Compiling verilog file "alu.v"
|
| 6843 |
|
|
Module compiled
|
| 6844 |
|
|
Compiling verilog file "switchsync.v"
|
| 6845 |
|
|
Module compiled
|
| 6846 |
|
|
Compiling verilog file "jkff.v"
|
| 6847 |
|
|
Module compiled
|
| 6848 |
|
|
Compiling verilog file "control.v"
|
| 6849 |
|
|
Module compiled
|
| 6850 |
|
|
Module compiled
|
| 6851 |
|
|
Compiling verilog file "maindcm.v"
|
| 6852 |
|
|
Module compiled
|
| 6853 |
|
|
Compiling verilog file "idecode.v"
|
| 6854 |
|
|
Module compiled
|
| 6855 |
|
|
Compiling verilog file "top.v"
|
| 6856 |
|
|
Module compiled
|
| 6857 |
|
|
Compiling verilog file "rcvr.v"
|
| 6858 |
|
|
Module compiled
|
| 6859 |
|
|
Compiling verilog file "txmit.v"
|
| 6860 |
|
|
Module compiled
|
| 6861 |
|
|
Compiling verilog file "uart.v"
|
| 6862 |
|
|
Module compiled
|
| 6863 |
|
|
Compiling verilog file "topbox.v"
|
| 6864 |
|
|
Module compiled
|
| 6865 |
|
|
No errors in compilation
|
| 6866 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 6867 |
|
|
|
| 6868 |
|
|
|
| 6869 |
|
|
=========================================================================
|
| 6870 |
|
|
* HDL Analysis *
|
| 6871 |
|
|
=========================================================================
|
| 6872 |
|
|
Analyzing top module .
|
| 6873 |
|
|
Module is correct for synthesis.
|
| 6874 |
|
|
|
| 6875 |
|
|
Set property "resynthesize = true" for unit .
|
| 6876 |
|
|
Analyzing module .
|
| 6877 |
|
|
Module is correct for synthesis.
|
| 6878 |
|
|
|
| 6879 |
|
|
Analyzing module .
|
| 6880 |
|
|
pClockFrequency = 50
|
| 6881 |
|
|
pRefreshFrequency = 100
|
| 6882 |
|
|
pUpperLimit = 125000
|
| 6883 |
|
|
pDividerCounterBits = 24
|
| 6884 |
|
|
Module is correct for synthesis.
|
| 6885 |
|
|
|
| 6886 |
|
|
Analyzing module .
|
| 6887 |
|
|
pInitialValue = 0
|
| 6888 |
|
|
pTimerWidth = 19
|
| 6889 |
|
|
pInitialTimerValue = 500000
|
| 6890 |
|
|
Module is correct for synthesis.
|
| 6891 |
|
|
|
| 6892 |
|
|
Analyzing module .
|
| 6893 |
|
|
Module is correct for synthesis.
|
| 6894 |
|
|
|
| 6895 |
|
|
Analyzing module .
|
| 6896 |
|
|
SIZE = 16
|
| 6897 |
|
|
Module is correct for synthesis.
|
| 6898 |
|
|
|
| 6899 |
|
|
Analyzing module .
|
| 6900 |
|
|
Module is correct for synthesis.
|
| 6901 |
|
|
|
| 6902 |
|
|
Analyzing module .
|
| 6903 |
|
|
SIZE = 12
|
| 6904 |
|
|
Module is correct for synthesis.
|
| 6905 |
|
|
|
| 6906 |
|
|
Analyzing module .
|
| 6907 |
|
|
Module is correct for synthesis.
|
| 6908 |
|
|
|
| 6909 |
|
|
Analyzing module .
|
| 6910 |
|
|
VALUE = 0000000000000001
|
| 6911 |
|
|
Module is correct for synthesis.
|
| 6912 |
|
|
|
| 6913 |
|
|
Analyzing module .
|
| 6914 |
|
|
Module is correct for synthesis.
|
| 6915 |
|
|
|
| 6916 |
|
|
Analyzing module .
|
| 6917 |
|
|
VALUE = 1111111111111111
|
| 6918 |
|
|
Module is correct for synthesis.
|
| 6919 |
|
|
|
| 6920 |
|
|
Analyzing module .
|
| 6921 |
|
|
Module is correct for synthesis.
|
| 6922 |
|
|
|
| 6923 |
|
|
Analyzing module .
|
| 6924 |
|
|
VALUE = 0000000000000000
|
| 6925 |
|
|
Module is correct for synthesis.
|
| 6926 |
|
|
|
| 6927 |
|
|
Analyzing module .
|
| 6928 |
|
|
Module is correct for synthesis.
|
| 6929 |
|
|
|
| 6930 |
|
|
Analyzing module .
|
| 6931 |
|
|
Module is correct for synthesis.
|
| 6932 |
|
|
|
| 6933 |
|
|
Analyzing module .
|
| 6934 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 6935 |
|
|
Module is correct for synthesis.
|
| 6936 |
|
|
|
| 6937 |
|
|
Analyzing module .
|
| 6938 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 6939 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 6940 |
|
|
Module is correct for synthesis.
|
| 6941 |
|
|
|
| 6942 |
|
|
Analyzing module .
|
| 6943 |
|
|
Module is correct for synthesis.
|
| 6944 |
|
|
|
| 6945 |
|
|
Analyzing module .
|
| 6946 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6947 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6948 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6949 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6950 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6951 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6952 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6953 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6954 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6955 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6956 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6957 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6958 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6959 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 6960 |
|
|
Module is correct for synthesis.
|
| 6961 |
|
|
|
| 6962 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 6963 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 6964 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 6965 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 6966 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 6967 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 6968 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 6969 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 6970 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 6971 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 6972 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 6973 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 6974 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 6975 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 6976 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 6977 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 6978 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 6979 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 6980 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 6981 |
|
|
Analyzing module .
|
| 6982 |
|
|
Module is correct for synthesis.
|
| 6983 |
|
|
|
| 6984 |
|
|
Analyzing module .
|
| 6985 |
|
|
XTAL_CLK = 35000000
|
| 6986 |
|
|
BAUD = 9600
|
| 6987 |
|
|
CLK_DIV = 113
|
| 6988 |
|
|
CW = 8
|
| 6989 |
|
|
Module is correct for synthesis.
|
| 6990 |
|
|
|
| 6991 |
|
|
Analyzing module .
|
| 6992 |
|
|
Module is correct for synthesis.
|
| 6993 |
|
|
|
| 6994 |
|
|
Analyzing module .
|
| 6995 |
|
|
Module is correct for synthesis.
|
| 6996 |
|
|
|
| 6997 |
|
|
|
| 6998 |
|
|
=========================================================================
|
| 6999 |
|
|
* HDL Synthesis *
|
| 7000 |
|
|
=========================================================================
|
| 7001 |
|
|
|
| 7002 |
|
|
Synthesizing Unit .
|
| 7003 |
|
|
Related source file is "txmit.v".
|
| 7004 |
|
|
Found 1-bit register for signal .
|
| 7005 |
|
|
Found 1-bit register for signal .
|
| 7006 |
|
|
Found 1-bit register for signal .
|
| 7007 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 7008 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 7009 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 7010 |
|
|
Found 1-bit register for signal .
|
| 7011 |
|
|
Found 1-bit register for signal .
|
| 7012 |
|
|
Found 4-bit up counter for signal .
|
| 7013 |
|
|
Found 4-bit up counter for signal .
|
| 7014 |
|
|
Found 8-bit register for signal .
|
| 7015 |
|
|
Found 8-bit register for signal .
|
| 7016 |
|
|
Summary:
|
| 7017 |
|
|
inferred 2 Counter(s).
|
| 7018 |
|
|
inferred 21 D-type flip-flop(s).
|
| 7019 |
|
|
inferred 2 Comparator(s).
|
| 7020 |
|
|
inferred 1 Multiplexer(s).
|
| 7021 |
|
|
Unit synthesized.
|
| 7022 |
|
|
|
| 7023 |
|
|
|
| 7024 |
|
|
Synthesizing Unit .
|
| 7025 |
|
|
Related source file is "rcvr.v".
|
| 7026 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 7027 |
|
|
Found 1-bit register for signal .
|
| 7028 |
|
|
Found 1-bit register for signal .
|
| 7029 |
|
|
Found 1-bit register for signal .
|
| 7030 |
|
|
Found 8-bit tristate buffer for signal .
|
| 7031 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 7032 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 7033 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 7034 |
|
|
Found 1-bit register for signal .
|
| 7035 |
|
|
Found 1-bit register for signal .
|
| 7036 |
|
|
Found 4-bit register for signal .
|
| 7037 |
|
|
Found 4-bit up counter for signal .
|
| 7038 |
|
|
Found 8-bit register for signal .
|
| 7039 |
|
|
Found 7-bit register for signal >.
|
| 7040 |
|
|
Found 1-bit register for signal .
|
| 7041 |
|
|
Found 1-bit register for signal .
|
| 7042 |
|
|
Summary:
|
| 7043 |
|
|
inferred 1 Counter(s).
|
| 7044 |
|
|
inferred 26 D-type flip-flop(s).
|
| 7045 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 7046 |
|
|
inferred 1 Comparator(s).
|
| 7047 |
|
|
inferred 1 Multiplexer(s).
|
| 7048 |
|
|
inferred 8 Tristate(s).
|
| 7049 |
|
|
Unit synthesized.
|
| 7050 |
|
|
|
| 7051 |
|
|
|
| 7052 |
|
|
Synthesizing Unit .
|
| 7053 |
|
|
Related source file is "jkff.v".
|
| 7054 |
|
|
Found 1-bit register for signal .
|
| 7055 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 7056 |
|
|
Summary:
|
| 7057 |
|
|
inferred 1 D-type flip-flop(s).
|
| 7058 |
|
|
inferred 1 Multiplexer(s).
|
| 7059 |
|
|
Unit synthesized.
|
| 7060 |
|
|
|
| 7061 |
|
|
|
| 7062 |
|
|
Synthesizing Unit .
|
| 7063 |
|
|
Related source file is "switchsync.v".
|
| 7064 |
|
|
Found 1-bit register for signal .
|
| 7065 |
|
|
Found 1-bit register for signal .
|
| 7066 |
|
|
Summary:
|
| 7067 |
|
|
inferred 2 D-type flip-flop(s).
|
| 7068 |
|
|
Unit synthesized.
|
| 7069 |
|
|
|
| 7070 |
|
|
|
| 7071 |
|
|
Synthesizing Unit .
|
| 7072 |
|
|
Related source file is "maindcm.v".
|
| 7073 |
|
|
Unit synthesized.
|
| 7074 |
|
|
|
| 7075 |
|
|
|
| 7076 |
|
|
Synthesizing Unit .
|
| 7077 |
|
|
Related source file is "control.v".
|
| 7078 |
|
|
Found 1-bit register for signal .
|
| 7079 |
|
|
Found 1-bit register for signal .
|
| 7080 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 7081 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 7082 |
|
|
Found 3-bit up counter for signal .
|
| 7083 |
|
|
Summary:
|
| 7084 |
|
|
inferred 1 Counter(s).
|
| 7085 |
|
|
inferred 2 D-type flip-flop(s).
|
| 7086 |
|
|
inferred 2 Multiplexer(s).
|
| 7087 |
|
|
Unit synthesized.
|
| 7088 |
|
|
|
| 7089 |
|
|
|
| 7090 |
|
|
Synthesizing Unit .
|
| 7091 |
|
|
Related source file is "misc.v".
|
| 7092 |
|
|
Found 16-bit tristate buffer for signal .
|
| 7093 |
|
|
Summary:
|
| 7094 |
|
|
inferred 16 Tristate(s).
|
| 7095 |
|
|
Unit synthesized.
|
| 7096 |
|
|
|
| 7097 |
|
|
|
| 7098 |
|
|
Synthesizing Unit .
|
| 7099 |
|
|
Related source file is "misc.v".
|
| 7100 |
|
|
Found 16-bit tristate buffer for signal .
|
| 7101 |
|
|
Summary:
|
| 7102 |
|
|
inferred 16 Tristate(s).
|
| 7103 |
|
|
Unit synthesized.
|
| 7104 |
|
|
|
| 7105 |
|
|
|
| 7106 |
|
|
Synthesizing Unit .
|
| 7107 |
|
|
Related source file is "misc.v".
|
| 7108 |
|
|
Found 16-bit tristate buffer for signal .
|
| 7109 |
|
|
Summary:
|
| 7110 |
|
|
inferred 16 Tristate(s).
|
| 7111 |
|
|
Unit synthesized.
|
| 7112 |
|
|
|
| 7113 |
|
|
|
| 7114 |
|
|
Synthesizing Unit .
|
| 7115 |
|
|
Related source file is "misc.v".
|
| 7116 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 7117 |
|
|
Found 16-bit tristate buffer for signal .
|
| 7118 |
|
|
Found 12-bit register for signal .
|
| 7119 |
|
|
Summary:
|
| 7120 |
|
|
inferred 12 D-type flip-flop(s).
|
| 7121 |
|
|
inferred 16 Tristate(s).
|
| 7122 |
|
|
Unit synthesized.
|
| 7123 |
|
|
|
| 7124 |
|
|
|
| 7125 |
|
|
Synthesizing Unit .
|
| 7126 |
|
|
Related source file is "idecode.v".
|
| 7127 |
|
|
Unit synthesized.
|
| 7128 |
|
|
|
| 7129 |
|
|
|
| 7130 |
|
|
Synthesizing Unit .
|
| 7131 |
|
|
Related source file is "control.v".
|
| 7132 |
|
|
Unit synthesized.
|
| 7133 |
|
|
|
| 7134 |
|
|
|
| 7135 |
|
|
Synthesizing Unit .
|
| 7136 |
|
|
Related source file is "alu.v".
|
| 7137 |
|
|
Found 16-bit tristate buffer for signal .
|
| 7138 |
|
|
Found 17-bit subtractor for signal <$AUX_108>.
|
| 7139 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 7140 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 7141 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 7142 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 7143 |
|
|
Summary:
|
| 7144 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 7145 |
|
|
inferred 16 Tristate(s).
|
| 7146 |
|
|
Unit synthesized.
|
| 7147 |
|
|
|
| 7148 |
|
|
|
| 7149 |
|
|
Synthesizing Unit .
|
| 7150 |
|
|
Related source file is "misc.v".
|
| 7151 |
|
|
Unit synthesized.
|
| 7152 |
|
|
|
| 7153 |
|
|
|
| 7154 |
|
|
Synthesizing Unit .
|
| 7155 |
|
|
Related source file is "misc.v".
|
| 7156 |
|
|
Unit synthesized.
|
| 7157 |
|
|
|
| 7158 |
|
|
|
| 7159 |
|
|
Synthesizing Unit .
|
| 7160 |
|
|
Related source file is "misc.v".
|
| 7161 |
|
|
Unit synthesized.
|
| 7162 |
|
|
|
| 7163 |
|
|
|
| 7164 |
|
|
Synthesizing Unit .
|
| 7165 |
|
|
Related source file is "misc.v".
|
| 7166 |
|
|
Unit synthesized.
|
| 7167 |
|
|
|
| 7168 |
|
|
|
| 7169 |
|
|
Synthesizing Unit .
|
| 7170 |
|
|
Related source file is "misc.v".
|
| 7171 |
|
|
Found 16-bit tristate buffer for signal .
|
| 7172 |
|
|
Found 16-bit register for signal .
|
| 7173 |
|
|
Summary:
|
| 7174 |
|
|
inferred 16 D-type flip-flop(s).
|
| 7175 |
|
|
inferred 16 Tristate(s).
|
| 7176 |
|
|
Unit synthesized.
|
| 7177 |
|
|
|
| 7178 |
|
|
|
| 7179 |
|
|
Synthesizing Unit .
|
| 7180 |
|
|
Related source file is "io.v".
|
| 7181 |
|
|
Found 1-bit register for signal .
|
| 7182 |
|
|
Found 1-bit register for signal .
|
| 7183 |
|
|
Found 1-bit register for signal .
|
| 7184 |
|
|
Found 1-bit register for signal .
|
| 7185 |
|
|
Found 1-bit register for signal .
|
| 7186 |
|
|
Found 1-bit register for signal .
|
| 7187 |
|
|
Found 19-bit down counter for signal .
|
| 7188 |
|
|
Found 1-bit register for signal .
|
| 7189 |
|
|
Found 1-bit xor2 for signal .
|
| 7190 |
|
|
Summary:
|
| 7191 |
|
|
inferred 1 Counter(s).
|
| 7192 |
|
|
inferred 7 D-type flip-flop(s).
|
| 7193 |
|
|
Unit synthesized.
|
| 7194 |
|
|
|
| 7195 |
|
|
|
| 7196 |
|
|
Synthesizing Unit .
|
| 7197 |
|
|
Related source file is "io.v".
|
| 7198 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 7199 |
|
|
Found 1-bit register for signal .
|
| 7200 |
|
|
Found 1-bit register for signal .
|
| 7201 |
|
|
Found 1-bit register for signal .
|
| 7202 |
|
|
Found 1-bit register for signal .
|
| 7203 |
|
|
Found 1-bit register for signal .
|
| 7204 |
|
|
Found 1-bit register for signal .
|
| 7205 |
|
|
Found 1-bit register for signal .
|
| 7206 |
|
|
Found 1-bit register for signal .
|
| 7207 |
|
|
Found 1-bit register for signal .
|
| 7208 |
|
|
Found 1-bit register for signal .
|
| 7209 |
|
|
Found 1-bit register for signal .
|
| 7210 |
|
|
Found 1-bit register for signal .
|
| 7211 |
|
|
Found 24-bit up counter for signal .
|
| 7212 |
|
|
Found 1-of-4 decoder for signal .
|
| 7213 |
|
|
Found 2-bit down counter for signal .
|
| 7214 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 7215 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 7216 |
|
|
Summary:
|
| 7217 |
|
|
inferred 1 ROM(s).
|
| 7218 |
|
|
inferred 2 Counter(s).
|
| 7219 |
|
|
inferred 12 D-type flip-flop(s).
|
| 7220 |
|
|
inferred 9 Multiplexer(s).
|
| 7221 |
|
|
inferred 1 Decoder(s).
|
| 7222 |
|
|
Unit synthesized.
|
| 7223 |
|
|
|
| 7224 |
|
|
|
| 7225 |
|
|
Synthesizing Unit .
|
| 7226 |
|
|
Related source file is "uart.v".
|
| 7227 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 7228 |
|
|
Found 1-bit register for signal .
|
| 7229 |
|
|
Found 8-bit up counter for signal .
|
| 7230 |
|
|
Found 1-bit register for signal .
|
| 7231 |
|
|
Summary:
|
| 7232 |
|
|
inferred 1 Counter(s).
|
| 7233 |
|
|
inferred 2 D-type flip-flop(s).
|
| 7234 |
|
|
inferred 1 Multiplexer(s).
|
| 7235 |
|
|
Unit synthesized.
|
| 7236 |
|
|
|
| 7237 |
|
|
|
| 7238 |
|
|
Synthesizing Unit .
|
| 7239 |
|
|
Related source file is "top.v".
|
| 7240 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 7241 |
|
|
Found 16-bit tristate buffer for signal .
|
| 7242 |
|
|
Found 1-bit register for signal .
|
| 7243 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 7244 |
|
|
Found 16-bit tristate buffer for signal .
|
| 7245 |
|
|
Found 1-bit register for signal .
|
| 7246 |
|
|
Found 1-bit register for signal .
|
| 7247 |
|
|
Found 1-bit register for signal .
|
| 7248 |
|
|
Summary:
|
| 7249 |
|
|
inferred 4 D-type flip-flop(s).
|
| 7250 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 7251 |
|
|
inferred 96 Tristate(s).
|
| 7252 |
|
|
Unit synthesized.
|
| 7253 |
|
|
|
| 7254 |
|
|
|
| 7255 |
|
|
Synthesizing Unit .
|
| 7256 |
|
|
Related source file is "FrontPanel.v".
|
| 7257 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 7258 |
|
|
Found finite state machine for signal .
|
| 7259 |
|
|
-----------------------------------------------------------------------
|
| 7260 |
|
|
| States | 6 |
|
| 7261 |
|
|
| Transitions | 6 |
|
| 7262 |
|
|
| Inputs | 0 |
|
| 7263 |
|
|
| Outputs | 12 |
|
| 7264 |
|
|
| Clock | clockin (rising_edge) |
|
| 7265 |
|
|
| Clock enable | select (positive) |
|
| 7266 |
|
|
| Reset | clear (positive) |
|
| 7267 |
|
|
| Reset type | synchronous |
|
| 7268 |
|
|
| Reset State | 000001 |
|
| 7269 |
|
|
| Encoding | automatic |
|
| 7270 |
|
|
| Implementation | LUT |
|
| 7271 |
|
|
-----------------------------------------------------------------------
|
| 7272 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 7273 |
|
|
Found 4-bit register for signal .
|
| 7274 |
|
|
Found 16-bit register for signal .
|
| 7275 |
|
|
Summary:
|
| 7276 |
|
|
inferred 1 Finite State Machine(s).
|
| 7277 |
|
|
inferred 16 D-type flip-flop(s).
|
| 7278 |
|
|
inferred 16 Multiplexer(s).
|
| 7279 |
|
|
Unit synthesized.
|
| 7280 |
|
|
|
| 7281 |
|
|
|
| 7282 |
|
|
Synthesizing Unit .
|
| 7283 |
|
|
Related source file is "topbox.v".
|
| 7284 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 7285 |
|
|
Found 16-bit tristate buffer for signal .
|
| 7286 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 7287 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 7288 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 7289 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 7290 |
|
|
Found 4-bit register for signal .
|
| 7291 |
|
|
Found 1-bit register for signal .
|
| 7292 |
|
|
Found 1-bit register for signal .
|
| 7293 |
|
|
Found 16-bit register for signal .
|
| 7294 |
|
|
Summary:
|
| 7295 |
|
|
inferred 22 D-type flip-flop(s).
|
| 7296 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 7297 |
|
|
inferred 6 Multiplexer(s).
|
| 7298 |
|
|
inferred 48 Tristate(s).
|
| 7299 |
|
|
Unit synthesized.
|
| 7300 |
|
|
|
| 7301 |
|
|
|
| 7302 |
|
|
=========================================================================
|
| 7303 |
|
|
* Advanced HDL Synthesis *
|
| 7304 |
|
|
=========================================================================
|
| 7305 |
|
|
|
| 7306 |
|
|
Advanced RAM inference ...
|
| 7307 |
|
|
Advanced multiplier inference ...
|
| 7308 |
|
|
Advanced Registered AddSub inference ...
|
| 7309 |
|
|
Analyzing FSM for best encoding.
|
| 7310 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 7311 |
|
|
--------------------
|
| 7312 |
|
|
State | Encoding
|
| 7313 |
|
|
--------------------
|
| 7314 |
|
|
000001 | 100000
|
| 7315 |
|
|
000010 | 010000
|
| 7316 |
|
|
000100 | 001000
|
| 7317 |
|
|
001000 | 000100
|
| 7318 |
|
|
010000 | 000010
|
| 7319 |
|
|
100000 | 000001
|
| 7320 |
|
|
--------------------
|
| 7321 |
|
|
Dynamic shift register inference ...
|
| 7322 |
|
|
|
| 7323 |
|
|
=========================================================================
|
| 7324 |
|
|
HDL Synthesis Report
|
| 7325 |
|
|
|
| 7326 |
|
|
Macro Statistics
|
| 7327 |
|
|
# FSMs : 1
|
| 7328 |
|
|
# ROMs : 1
|
| 7329 |
|
|
16x7-bit ROM : 1
|
| 7330 |
|
|
# Adders/Subtractors : 5
|
| 7331 |
|
|
12-bit adder carry out : 1
|
| 7332 |
|
|
16-bit adder carry out : 1
|
| 7333 |
|
|
17-bit subtractor : 1
|
| 7334 |
|
|
4-bit adder : 2
|
| 7335 |
|
|
# Counters : 10
|
| 7336 |
|
|
19-bit down counter : 3
|
| 7337 |
|
|
2-bit down counter : 1
|
| 7338 |
|
|
24-bit up counter : 1
|
| 7339 |
|
|
3-bit up counter : 1
|
| 7340 |
|
|
4-bit up counter : 3
|
| 7341 |
|
|
8-bit up counter : 1
|
| 7342 |
|
|
# Registers : 138
|
| 7343 |
|
|
1-bit register : 125
|
| 7344 |
|
|
12-bit register : 4
|
| 7345 |
|
|
16-bit register : 4
|
| 7346 |
|
|
4-bit register : 3
|
| 7347 |
|
|
8-bit register : 2
|
| 7348 |
|
|
# Comparators : 3
|
| 7349 |
|
|
4-bit comparator greater : 2
|
| 7350 |
|
|
4-bit comparator less : 1
|
| 7351 |
|
|
# Multiplexers : 15
|
| 7352 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 7353 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 7354 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 7355 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 7356 |
|
|
# Decoders : 1
|
| 7357 |
|
|
1-of-4 decoder : 1
|
| 7358 |
|
|
# Tristates : 97
|
| 7359 |
|
|
1-bit tristate buffer : 80
|
| 7360 |
|
|
16-bit tristate buffer : 16
|
| 7361 |
|
|
8-bit tristate buffer : 1
|
| 7362 |
|
|
# Xors : 6
|
| 7363 |
|
|
1-bit xor2 : 5
|
| 7364 |
|
|
16-bit xor2 : 1
|
| 7365 |
|
|
|
| 7366 |
|
|
=========================================================================
|
| 7367 |
|
|
|
| 7368 |
|
|
=========================================================================
|
| 7369 |
|
|
* Low Level Synthesis *
|
| 7370 |
|
|
=========================================================================
|
| 7371 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 7372 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 7373 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 7374 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 7375 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 7376 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 7377 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 7378 |
|
|
|
| 7379 |
|
|
Optimizing unit ...
|
| 7380 |
|
|
|
| 7381 |
|
|
Optimizing unit ...
|
| 7382 |
|
|
|
| 7383 |
|
|
Optimizing unit ...
|
| 7384 |
|
|
|
| 7385 |
|
|
Optimizing unit ...
|
| 7386 |
|
|
|
| 7387 |
|
|
Optimizing unit ...
|
| 7388 |
|
|
|
| 7389 |
|
|
Optimizing unit ...
|
| 7390 |
|
|
|
| 7391 |
|
|
Optimizing unit ...
|
| 7392 |
|
|
|
| 7393 |
|
|
Optimizing unit ...
|
| 7394 |
|
|
|
| 7395 |
|
|
Optimizing unit ...
|
| 7396 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 7397 |
|
|
|
| 7398 |
|
|
Mapping all equations...
|
| 7399 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 7400 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 7401 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 7402 |
|
|
Building and optimizing final netlist ...
|
| 7403 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
|
| 7404 |
|
|
|
| 7405 |
|
|
=========================================================================
|
| 7406 |
|
|
* Final Report *
|
| 7407 |
|
|
=========================================================================
|
| 7408 |
|
|
|
| 7409 |
|
|
Device utilization summary:
|
| 7410 |
|
|
---------------------------
|
| 7411 |
|
|
|
| 7412 |
|
|
Selected Device : 3s200ft256-4
|
| 7413 |
|
|
|
| 7414 |
|
|
Number of Slices: 609 out of 1920 31%
|
| 7415 |
|
|
Number of Slice Flip Flops: 368 out of 3840 9%
|
| 7416 |
|
|
Number of 4 input LUTs: 1078 out of 3840 28%
|
| 7417 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 7418 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 7419 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 7420 |
|
|
|
| 7421 |
|
|
|
| 7422 |
|
|
=========================================================================
|
| 7423 |
|
|
TIMING REPORT
|
| 7424 |
|
|
|
| 7425 |
|
|
|
| 7426 |
|
|
Clock Information:
|
| 7427 |
|
|
------------------
|
| 7428 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 7429 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 7430 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 7431 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 368 |
|
| 7432 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 7433 |
|
|
|
| 7434 |
|
|
Timing Summary:
|
| 7435 |
|
|
---------------
|
| 7436 |
|
|
Speed Grade: -4
|
| 7437 |
|
|
|
| 7438 |
|
|
Minimum period: 14.634ns (Maximum Frequency: 68.333MHz)
|
| 7439 |
|
|
Minimum input arrival time before clock: 10.576ns
|
| 7440 |
|
|
Maximum output required time after clock: 24.823ns
|
| 7441 |
|
|
Maximum combinational path delay: 14.545ns
|
| 7442 |
|
|
|
| 7443 |
|
|
=========================================================================
|
| 7444 |
|
|
|
| 7445 |
|
|
|
| 7446 |
|
|
|
| 7447 |
|
|
|
| 7448 |
|
|
Started process "Translate".
|
| 7449 |
|
|
|
| 7450 |
|
|
|
| 7451 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 7452 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 7453 |
|
|
|
| 7454 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 7455 |
|
|
|
| 7456 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 7457 |
|
|
|
| 7458 |
|
|
Checking timing specifications ...
|
| 7459 |
|
|
Checking expanded design ...
|
| 7460 |
|
|
|
| 7461 |
|
|
NGDBUILD Design Results Summary:
|
| 7462 |
|
|
Number of errors: 0
|
| 7463 |
|
|
Number of warnings: 0
|
| 7464 |
|
|
|
| 7465 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 7466 |
|
|
|
| 7467 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 7468 |
|
|
|
| 7469 |
|
|
NGDBUILD done.
|
| 7470 |
|
|
|
| 7471 |
|
|
|
| 7472 |
|
|
|
| 7473 |
|
|
|
| 7474 |
|
|
Started process "Map".
|
| 7475 |
|
|
|
| 7476 |
|
|
Using target part "3s200ft256-4".
|
| 7477 |
|
|
Mapping design into LUTs...
|
| 7478 |
|
|
Running directed packing...
|
| 7479 |
|
|
Running delay-based LUT packing...
|
| 7480 |
|
|
Running related packing...
|
| 7481 |
|
|
|
| 7482 |
|
|
Design Summary:
|
| 7483 |
|
|
Number of errors: 0
|
| 7484 |
|
|
Number of warnings: 2
|
| 7485 |
|
|
Logic Utilization:
|
| 7486 |
|
|
Number of Slice Flip Flops: 342 out of 3,840 8%
|
| 7487 |
|
|
Number of 4 input LUTs: 1,128 out of 3,840 29%
|
| 7488 |
|
|
Logic Distribution:
|
| 7489 |
|
|
Number of occupied Slices: 661 out of 1,920 34%
|
| 7490 |
|
|
Number of Slices containing only related logic: 661 out of 661 100%
|
| 7491 |
|
|
Number of Slices containing unrelated logic: 0 out of 661 0%
|
| 7492 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 7493 |
|
|
Total Number 4 input LUTs: 1,132 out of 3,840 29%
|
| 7494 |
|
|
Number used as logic: 1,128
|
| 7495 |
|
|
Number used as a route-thru: 4
|
| 7496 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 7497 |
|
|
IOB Flip Flops: 26
|
| 7498 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 7499 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 7500 |
|
|
|
| 7501 |
|
|
Total equivalent gate count for design: 17,594
|
| 7502 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 7503 |
|
|
Peak Memory Usage: 113 MB
|
| 7504 |
|
|
|
| 7505 |
|
|
NOTES:
|
| 7506 |
|
|
|
| 7507 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 7508 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 7509 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 7510 |
|
|
the best timing performance.
|
| 7511 |
|
|
|
| 7512 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 7513 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 7514 |
|
|
related logic packing.
|
| 7515 |
|
|
|
| 7516 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 7517 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 7518 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 7519 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 7520 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 7521 |
|
|
of your design.
|
| 7522 |
|
|
|
| 7523 |
|
|
Mapping completed.
|
| 7524 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 7525 |
|
|
|
| 7526 |
|
|
|
| 7527 |
|
|
|
| 7528 |
|
|
|
| 7529 |
|
|
Started process "Place & Route".
|
| 7530 |
|
|
|
| 7531 |
|
|
|
| 7532 |
|
|
|
| 7533 |
|
|
|
| 7534 |
|
|
Constraints file: topbox.pcf.
|
| 7535 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 7536 |
|
|
C:/Xilinx71.
|
| 7537 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 7538 |
|
|
|
| 7539 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 7540 |
|
|
Celsius)
|
| 7541 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 7542 |
|
|
|
| 7543 |
|
|
|
| 7544 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 7545 |
|
|
|
| 7546 |
|
|
|
| 7547 |
|
|
Device Utilization Summary:
|
| 7548 |
|
|
|
| 7549 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 7550 |
|
|
Number of DCMs 1 out of 4 25%
|
| 7551 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 7552 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 7553 |
|
|
|
| 7554 |
|
|
Number of Slices 661 out of 1920 34%
|
| 7555 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 7556 |
|
|
|
| 7557 |
|
|
|
| 7558 |
|
|
|
| 7559 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 7560 |
|
|
Placer effort level (-pl): Standard (set by user)
|
| 7561 |
|
|
Placer cost table entry (-t): 1
|
| 7562 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 7563 |
|
|
|
| 7564 |
|
|
|
| 7565 |
|
|
Starting Placer
|
| 7566 |
|
|
|
| 7567 |
|
|
Phase 1.1
|
| 7568 |
|
|
Phase 1.1 (Checksum:98ae43) REAL time: 1 secs
|
| 7569 |
|
|
|
| 7570 |
|
|
Phase 2.31
|
| 7571 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
|
| 7572 |
|
|
|
| 7573 |
|
|
Phase 3.2
|
| 7574 |
|
|
.
|
| 7575 |
|
|
|
| 7576 |
|
|
|
| 7577 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs
|
| 7578 |
|
|
|
| 7579 |
|
|
Phase 4.8
|
| 7580 |
|
|
..............................
|
| 7581 |
|
|
Phase 4.8 (Checksum:a3e327) REAL time: 1 secs
|
| 7582 |
|
|
|
| 7583 |
|
|
Phase 5.5
|
| 7584 |
|
|
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs
|
| 7585 |
|
|
|
| 7586 |
|
|
Phase 6.18
|
| 7587 |
|
|
Phase 6.18 (Checksum:39386fa) REAL time: 2 secs
|
| 7588 |
|
|
|
| 7589 |
|
|
Phase 7.5
|
| 7590 |
|
|
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs
|
| 7591 |
|
|
|
| 7592 |
|
|
Writing design to file topbox.ncd
|
| 7593 |
|
|
|
| 7594 |
|
|
|
| 7595 |
|
|
Total REAL time to Placer completion: 2 secs
|
| 7596 |
|
|
Total CPU time to Placer completion: 2 secs
|
| 7597 |
|
|
|
| 7598 |
|
|
Starting Router
|
| 7599 |
|
|
|
| 7600 |
|
|
Phase 1: 4597 unrouted; REAL time: 2 secs
|
| 7601 |
|
|
|
| 7602 |
|
|
Phase 2: 4347 unrouted; REAL time: 2 secs
|
| 7603 |
|
|
|
| 7604 |
|
|
Phase 3: 2175 unrouted; REAL time: 2 secs
|
| 7605 |
|
|
|
| 7606 |
|
|
Phase 4: 0 unrouted; REAL time: 4 secs
|
| 7607 |
|
|
|
| 7608 |
|
|
|
| 7609 |
|
|
Total REAL time to Router completion: 4 secs
|
| 7610 |
|
|
Total CPU time to Router completion: 4 secs
|
| 7611 |
|
|
|
| 7612 |
|
|
Generating "PAR" statistics.
|
| 7613 |
|
|
|
| 7614 |
|
|
**************************
|
| 7615 |
|
|
Generating Clock Report
|
| 7616 |
|
|
**************************
|
| 7617 |
|
|
|
| 7618 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 7619 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 7620 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 7621 |
|
|
| clk | BUFGMUX3| No | 231 | 0.041 | 1.051 |
|
| 7622 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 7623 |
|
|
|
| 7624 |
|
|
Generating Pad Report.
|
| 7625 |
|
|
|
| 7626 |
|
|
All signals are completely routed.
|
| 7627 |
|
|
|
| 7628 |
|
|
Total REAL time to PAR completion: 4 secs
|
| 7629 |
|
|
Total CPU time to PAR completion: 4 secs
|
| 7630 |
|
|
|
| 7631 |
|
|
Peak Memory Usage: 82 MB
|
| 7632 |
|
|
|
| 7633 |
|
|
Placement: Completed - No errors found.
|
| 7634 |
|
|
Routing: Completed - No errors found.
|
| 7635 |
|
|
|
| 7636 |
|
|
Number of error messages: 0
|
| 7637 |
|
|
Number of warning messages: 0
|
| 7638 |
|
|
Number of info messages: 1
|
| 7639 |
|
|
|
| 7640 |
|
|
Writing design to file topbox.ncd
|
| 7641 |
|
|
|
| 7642 |
|
|
|
| 7643 |
|
|
|
| 7644 |
|
|
PAR done!
|
| 7645 |
|
|
|
| 7646 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 7647 |
|
|
|
| 7648 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 7649 |
|
|
C:/Xilinx71.
|
| 7650 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 7651 |
|
|
|
| 7652 |
|
|
Analysis completed Sun Sep 24 10:42:52 2006
|
| 7653 |
|
|
--------------------------------------------------------------------------------
|
| 7654 |
|
|
|
| 7655 |
|
|
Generating Report ...
|
| 7656 |
|
|
|
| 7657 |
|
|
Number of warnings: 0
|
| 7658 |
|
|
Total time: 2 secs
|
| 7659 |
|
|
|
| 7660 |
|
|
|
| 7661 |
|
|
|
| 7662 |
|
|
|
| 7663 |
|
|
|
| 7664 |
|
|
|
| 7665 |
|
|
|
| 7666 |
|
|
Started process "Generate Programming File".
|
| 7667 |
|
|
|
| 7668 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 7669 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 7670 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 7671 |
|
|
Interactive Data Sheet.
|
| 7672 |
|
|
|
| 7673 |
|
|
|
| 7674 |
|
|
Project Navigator Auto-Make Log File
|
| 7675 |
|
|
-------------------------------------
|
| 7676 |
|
|
|
| 7677 |
|
|
|
| 7678 |
|
|
|
| 7679 |
|
|
|
| 7680 |
|
|
Started process "Translate".
|
| 7681 |
|
|
|
| 7682 |
|
|
|
| 7683 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 7684 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 7685 |
|
|
|
| 7686 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 7687 |
|
|
|
| 7688 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 7689 |
|
|
|
| 7690 |
|
|
Checking timing specifications ...
|
| 7691 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 7692 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 7693 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 7694 |
|
|
20.408000 nS HIGH 50.000000%
|
| 7695 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 7696 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 7697 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 7698 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 7699 |
|
|
from this group.
|
| 7700 |
|
|
Checking expanded design ...
|
| 7701 |
|
|
|
| 7702 |
|
|
NGDBUILD Design Results Summary:
|
| 7703 |
|
|
Number of errors: 0
|
| 7704 |
|
|
Number of warnings: 1
|
| 7705 |
|
|
|
| 7706 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 7707 |
|
|
|
| 7708 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 7709 |
|
|
|
| 7710 |
|
|
NGDBUILD done.
|
| 7711 |
|
|
|
| 7712 |
|
|
|
| 7713 |
|
|
|
| 7714 |
|
|
|
| 7715 |
|
|
Started process "Map".
|
| 7716 |
|
|
|
| 7717 |
|
|
Using target part "3s200ft256-4".
|
| 7718 |
|
|
Mapping design into LUTs...
|
| 7719 |
|
|
Running directed packing...
|
| 7720 |
|
|
Running delay-based LUT packing...
|
| 7721 |
|
|
Running related packing...
|
| 7722 |
|
|
|
| 7723 |
|
|
Design Summary:
|
| 7724 |
|
|
Number of errors: 0
|
| 7725 |
|
|
Number of warnings: 2
|
| 7726 |
|
|
Logic Utilization:
|
| 7727 |
|
|
Number of Slice Flip Flops: 342 out of 3,840 8%
|
| 7728 |
|
|
Number of 4 input LUTs: 1,128 out of 3,840 29%
|
| 7729 |
|
|
Logic Distribution:
|
| 7730 |
|
|
Number of occupied Slices: 661 out of 1,920 34%
|
| 7731 |
|
|
Number of Slices containing only related logic: 661 out of 661 100%
|
| 7732 |
|
|
Number of Slices containing unrelated logic: 0 out of 661 0%
|
| 7733 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 7734 |
|
|
Total Number 4 input LUTs: 1,132 out of 3,840 29%
|
| 7735 |
|
|
Number used as logic: 1,128
|
| 7736 |
|
|
Number used as a route-thru: 4
|
| 7737 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 7738 |
|
|
IOB Flip Flops: 26
|
| 7739 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 7740 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 7741 |
|
|
|
| 7742 |
|
|
Total equivalent gate count for design: 17,594
|
| 7743 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 7744 |
|
|
Peak Memory Usage: 113 MB
|
| 7745 |
|
|
|
| 7746 |
|
|
NOTES:
|
| 7747 |
|
|
|
| 7748 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 7749 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 7750 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 7751 |
|
|
the best timing performance.
|
| 7752 |
|
|
|
| 7753 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 7754 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 7755 |
|
|
related logic packing.
|
| 7756 |
|
|
|
| 7757 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 7758 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 7759 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 7760 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 7761 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 7762 |
|
|
of your design.
|
| 7763 |
|
|
|
| 7764 |
|
|
Mapping completed.
|
| 7765 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 7766 |
|
|
|
| 7767 |
|
|
|
| 7768 |
|
|
|
| 7769 |
|
|
|
| 7770 |
|
|
Started process "Place & Route".
|
| 7771 |
|
|
|
| 7772 |
|
|
|
| 7773 |
|
|
|
| 7774 |
|
|
|
| 7775 |
|
|
Constraints file: topbox.pcf.
|
| 7776 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 7777 |
|
|
C:/Xilinx71.
|
| 7778 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 7779 |
|
|
|
| 7780 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 7781 |
|
|
Celsius)
|
| 7782 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 7783 |
|
|
|
| 7784 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 7785 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 7786 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 7787 |
|
|
ps (24.00 Mhz).
|
| 7788 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 7789 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 7790 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 7791 |
|
|
(210.04 Mhz).
|
| 7792 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 7793 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 7794 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 7795 |
|
|
ps (24.00 Mhz).
|
| 7796 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 7797 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 7798 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 7799 |
|
|
(210.04 Mhz).
|
| 7800 |
|
|
|
| 7801 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 7802 |
|
|
|
| 7803 |
|
|
|
| 7804 |
|
|
Device Utilization Summary:
|
| 7805 |
|
|
|
| 7806 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 7807 |
|
|
Number of DCMs 1 out of 4 25%
|
| 7808 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 7809 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 7810 |
|
|
|
| 7811 |
|
|
Number of Slices 661 out of 1920 34%
|
| 7812 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 7813 |
|
|
|
| 7814 |
|
|
|
| 7815 |
|
|
|
| 7816 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 7817 |
|
|
Placer effort level (-pl): Standard (set by user)
|
| 7818 |
|
|
Placer cost table entry (-t): 1
|
| 7819 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 7820 |
|
|
|
| 7821 |
|
|
Starting initial Timing Analysis. REAL time: 2 secs
|
| 7822 |
|
|
Finished initial Timing Analysis. REAL time: 2 secs
|
| 7823 |
|
|
|
| 7824 |
|
|
|
| 7825 |
|
|
Starting Placer
|
| 7826 |
|
|
|
| 7827 |
|
|
Phase 1.1
|
| 7828 |
|
|
Phase 1.1 (Checksum:98ae43) REAL time: 2 secs
|
| 7829 |
|
|
|
| 7830 |
|
|
Phase 2.31
|
| 7831 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs
|
| 7832 |
|
|
|
| 7833 |
|
|
Phase 3.2
|
| 7834 |
|
|
.
|
| 7835 |
|
|
|
| 7836 |
|
|
|
| 7837 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs
|
| 7838 |
|
|
|
| 7839 |
|
|
Phase 4.8
|
| 7840 |
|
|
..............................
|
| 7841 |
|
|
....
|
| 7842 |
|
|
Phase 4.8 (Checksum:a448b3) REAL time: 5 secs
|
| 7843 |
|
|
|
| 7844 |
|
|
Phase 5.5
|
| 7845 |
|
|
Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs
|
| 7846 |
|
|
|
| 7847 |
|
|
Phase 6.18
|
| 7848 |
|
|
Phase 6.18 (Checksum:39386fa) REAL time: 7 secs
|
| 7849 |
|
|
|
| 7850 |
|
|
Phase 7.5
|
| 7851 |
|
|
Phase 7.5 (Checksum:42c1d79) REAL time: 7 secs
|
| 7852 |
|
|
|
| 7853 |
|
|
Writing design to file topbox.ncd
|
| 7854 |
|
|
|
| 7855 |
|
|
|
| 7856 |
|
|
Total REAL time to Placer completion: 7 secs
|
| 7857 |
|
|
Total CPU time to Placer completion: 7 secs
|
| 7858 |
|
|
|
| 7859 |
|
|
Starting Router
|
| 7860 |
|
|
|
| 7861 |
|
|
Phase 1: 4597 unrouted; REAL time: 7 secs
|
| 7862 |
|
|
|
| 7863 |
|
|
Phase 2: 4348 unrouted; REAL time: 7 secs
|
| 7864 |
|
|
|
| 7865 |
|
|
Phase 3: 2125 unrouted; REAL time: 8 secs
|
| 7866 |
|
|
|
| 7867 |
|
|
Phase 4: 2125 unrouted; (0) REAL time: 8 secs
|
| 7868 |
|
|
|
| 7869 |
|
|
Phase 5: 2125 unrouted; (0) REAL time: 8 secs
|
| 7870 |
|
|
|
| 7871 |
|
|
Phase 6: 2125 unrouted; (0) REAL time: 9 secs
|
| 7872 |
|
|
|
| 7873 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 11 secs
|
| 7874 |
|
|
|
| 7875 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 11 secs
|
| 7876 |
|
|
|
| 7877 |
|
|
|
| 7878 |
|
|
Total REAL time to Router completion: 11 secs
|
| 7879 |
|
|
Total CPU time to Router completion: 11 secs
|
| 7880 |
|
|
|
| 7881 |
|
|
Generating "PAR" statistics.
|
| 7882 |
|
|
|
| 7883 |
|
|
**************************
|
| 7884 |
|
|
Generating Clock Report
|
| 7885 |
|
|
**************************
|
| 7886 |
|
|
|
| 7887 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 7888 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 7889 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 7890 |
|
|
| clk | BUFGMUX3| No | 231 | 0.041 | 1.051 |
|
| 7891 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 7892 |
|
|
|
| 7893 |
|
|
Timing Score: 0
|
| 7894 |
|
|
|
| 7895 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 7896 |
|
|
This may be due to a setup or hold violation.
|
| 7897 |
|
|
|
| 7898 |
|
|
--------------------------------------------------------------------------------
|
| 7899 |
|
|
Constraint | Requested | Actual | Logic
|
| 7900 |
|
|
| | | Levels
|
| 7901 |
|
|
--------------------------------------------------------------------------------
|
| 7902 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 7903 |
|
|
HIGH 50% | | |
|
| 7904 |
|
|
--------------------------------------------------------------------------------
|
| 7905 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 30.442ns | 7
|
| 7906 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 7907 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 7908 |
|
|
--------------------------------------------------------------------------------
|
| 7909 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 39.710ns | 12
|
| 7910 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 7911 |
|
|
HIGH 50% | | |
|
| 7912 |
|
|
--------------------------------------------------------------------------------
|
| 7913 |
|
|
|
| 7914 |
|
|
|
| 7915 |
|
|
All constraints were met.
|
| 7916 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 7917 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 7918 |
|
|
Generating Pad Report.
|
| 7919 |
|
|
|
| 7920 |
|
|
All signals are completely routed.
|
| 7921 |
|
|
|
| 7922 |
|
|
Total REAL time to PAR completion: 12 secs
|
| 7923 |
|
|
Total CPU time to PAR completion: 12 secs
|
| 7924 |
|
|
|
| 7925 |
|
|
Peak Memory Usage: 96 MB
|
| 7926 |
|
|
|
| 7927 |
|
|
Placement: Completed - No errors found.
|
| 7928 |
|
|
Routing: Completed - No errors found.
|
| 7929 |
|
|
Timing: Completed - No errors found.
|
| 7930 |
|
|
|
| 7931 |
|
|
Number of error messages: 0
|
| 7932 |
|
|
Number of warning messages: 4
|
| 7933 |
|
|
Number of info messages: 0
|
| 7934 |
|
|
|
| 7935 |
|
|
Writing design to file topbox.ncd
|
| 7936 |
|
|
|
| 7937 |
|
|
|
| 7938 |
|
|
|
| 7939 |
|
|
PAR done!
|
| 7940 |
|
|
|
| 7941 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 7942 |
|
|
|
| 7943 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 7944 |
|
|
C:/Xilinx71.
|
| 7945 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 7946 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 7947 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 7948 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 7949 |
|
|
ps (24.00 Mhz).
|
| 7950 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 7951 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 7952 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 7953 |
|
|
(210.04 Mhz).
|
| 7954 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 7955 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 7956 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 7957 |
|
|
ps (24.00 Mhz).
|
| 7958 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 7959 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 7960 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 7961 |
|
|
(210.04 Mhz).
|
| 7962 |
|
|
|
| 7963 |
|
|
Analysis completed Sun Sep 24 11:49:52 2006
|
| 7964 |
|
|
--------------------------------------------------------------------------------
|
| 7965 |
|
|
|
| 7966 |
|
|
Generating Report ...
|
| 7967 |
|
|
|
| 7968 |
|
|
Number of warnings: 4
|
| 7969 |
|
|
Total time: 2 secs
|
| 7970 |
|
|
|
| 7971 |
|
|
|
| 7972 |
|
|
|
| 7973 |
|
|
|
| 7974 |
|
|
|
| 7975 |
|
|
|
| 7976 |
|
|
|
| 7977 |
|
|
Started process "Generate Programming File".
|
| 7978 |
|
|
|
| 7979 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 7980 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 7981 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 7982 |
|
|
Interactive Data Sheet.
|
| 7983 |
|
|
|
| 7984 |
|
|
|
| 7985 |
|
|
Project Navigator Auto-Make Log File
|
| 7986 |
|
|
-------------------------------------
|
| 7987 |
|
|
|
| 7988 |
|
|
|
| 7989 |
|
|
|
| 7990 |
|
|
|
| 7991 |
|
|
Started process "Synthesize".
|
| 7992 |
|
|
|
| 7993 |
|
|
|
| 7994 |
|
|
=========================================================================
|
| 7995 |
|
|
* HDL Compilation *
|
| 7996 |
|
|
=========================================================================
|
| 7997 |
|
|
Compiling verilog file "io.v"
|
| 7998 |
|
|
Module compiled
|
| 7999 |
|
|
Module compiled
|
| 8000 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 8001 |
|
|
Module compiled
|
| 8002 |
|
|
Compiling verilog file "misc.v"
|
| 8003 |
|
|
Module compiled
|
| 8004 |
|
|
Module compiled
|
| 8005 |
|
|
Module compiled
|
| 8006 |
|
|
Module compiled
|
| 8007 |
|
|
Module compiled
|
| 8008 |
|
|
Module compiled
|
| 8009 |
|
|
Compiling verilog file "alu.v"
|
| 8010 |
|
|
Module compiled
|
| 8011 |
|
|
Compiling verilog file "switchsync.v"
|
| 8012 |
|
|
Module compiled
|
| 8013 |
|
|
Compiling verilog file "jkff.v"
|
| 8014 |
|
|
Module compiled
|
| 8015 |
|
|
Compiling verilog file "control.v"
|
| 8016 |
|
|
Module compiled
|
| 8017 |
|
|
Module compiled
|
| 8018 |
|
|
Compiling verilog file "maindcm.v"
|
| 8019 |
|
|
Module compiled
|
| 8020 |
|
|
Compiling verilog file "idecode.v"
|
| 8021 |
|
|
Module compiled
|
| 8022 |
|
|
Compiling verilog file "top.v"
|
| 8023 |
|
|
Module compiled
|
| 8024 |
|
|
Compiling verilog file "rcvr.v"
|
| 8025 |
|
|
Module compiled
|
| 8026 |
|
|
Compiling verilog file "txmit.v"
|
| 8027 |
|
|
Module compiled
|
| 8028 |
|
|
Compiling verilog file "uart.v"
|
| 8029 |
|
|
Module compiled
|
| 8030 |
|
|
Compiling verilog file "topbox.v"
|
| 8031 |
|
|
Module compiled
|
| 8032 |
|
|
No errors in compilation
|
| 8033 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 8034 |
|
|
|
| 8035 |
|
|
|
| 8036 |
|
|
=========================================================================
|
| 8037 |
|
|
* HDL Analysis *
|
| 8038 |
|
|
=========================================================================
|
| 8039 |
|
|
Analyzing top module .
|
| 8040 |
|
|
Module is correct for synthesis.
|
| 8041 |
|
|
|
| 8042 |
|
|
Analyzing module .
|
| 8043 |
|
|
Module is correct for synthesis.
|
| 8044 |
|
|
|
| 8045 |
|
|
Analyzing module .
|
| 8046 |
|
|
pClockFrequency = 50
|
| 8047 |
|
|
pRefreshFrequency = 100
|
| 8048 |
|
|
pUpperLimit = 125000
|
| 8049 |
|
|
pDividerCounterBits = 24
|
| 8050 |
|
|
Module is correct for synthesis.
|
| 8051 |
|
|
|
| 8052 |
|
|
Analyzing module .
|
| 8053 |
|
|
pInitialValue = 0
|
| 8054 |
|
|
pTimerWidth = 19
|
| 8055 |
|
|
pInitialTimerValue = 500000
|
| 8056 |
|
|
Module is correct for synthesis.
|
| 8057 |
|
|
|
| 8058 |
|
|
Analyzing module .
|
| 8059 |
|
|
Module is correct for synthesis.
|
| 8060 |
|
|
|
| 8061 |
|
|
Analyzing module .
|
| 8062 |
|
|
SIZE = 16
|
| 8063 |
|
|
Module is correct for synthesis.
|
| 8064 |
|
|
|
| 8065 |
|
|
Analyzing module .
|
| 8066 |
|
|
Module is correct for synthesis.
|
| 8067 |
|
|
|
| 8068 |
|
|
Analyzing module .
|
| 8069 |
|
|
SIZE = 12
|
| 8070 |
|
|
Module is correct for synthesis.
|
| 8071 |
|
|
|
| 8072 |
|
|
Analyzing module .
|
| 8073 |
|
|
Module is correct for synthesis.
|
| 8074 |
|
|
|
| 8075 |
|
|
Analyzing module .
|
| 8076 |
|
|
VALUE = 0000000000000001
|
| 8077 |
|
|
Module is correct for synthesis.
|
| 8078 |
|
|
|
| 8079 |
|
|
Analyzing module .
|
| 8080 |
|
|
Module is correct for synthesis.
|
| 8081 |
|
|
|
| 8082 |
|
|
Analyzing module .
|
| 8083 |
|
|
VALUE = 1111111111111111
|
| 8084 |
|
|
Module is correct for synthesis.
|
| 8085 |
|
|
|
| 8086 |
|
|
Analyzing module .
|
| 8087 |
|
|
Module is correct for synthesis.
|
| 8088 |
|
|
|
| 8089 |
|
|
Analyzing module .
|
| 8090 |
|
|
VALUE = 0000000000000000
|
| 8091 |
|
|
Module is correct for synthesis.
|
| 8092 |
|
|
|
| 8093 |
|
|
Analyzing module .
|
| 8094 |
|
|
Module is correct for synthesis.
|
| 8095 |
|
|
|
| 8096 |
|
|
Analyzing module .
|
| 8097 |
|
|
Module is correct for synthesis.
|
| 8098 |
|
|
|
| 8099 |
|
|
Analyzing module .
|
| 8100 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 8101 |
|
|
Module is correct for synthesis.
|
| 8102 |
|
|
|
| 8103 |
|
|
Analyzing module .
|
| 8104 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 8105 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 8106 |
|
|
Module is correct for synthesis.
|
| 8107 |
|
|
|
| 8108 |
|
|
Analyzing module .
|
| 8109 |
|
|
Module is correct for synthesis.
|
| 8110 |
|
|
|
| 8111 |
|
|
Analyzing module .
|
| 8112 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8113 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8114 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8115 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8116 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8117 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8118 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8119 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8120 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8121 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8122 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8123 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8124 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8125 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 8126 |
|
|
Module is correct for synthesis.
|
| 8127 |
|
|
|
| 8128 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 8129 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 8130 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 8131 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 8132 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 8133 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 8134 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 8135 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 8136 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 8137 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 8138 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 8139 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 8140 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 8141 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 8142 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 8143 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 8144 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 8145 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 8146 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 8147 |
|
|
Analyzing module .
|
| 8148 |
|
|
Module is correct for synthesis.
|
| 8149 |
|
|
|
| 8150 |
|
|
Analyzing module .
|
| 8151 |
|
|
XTAL_CLK = 35000000
|
| 8152 |
|
|
BAUD = 9600
|
| 8153 |
|
|
CLK_DIV = 113
|
| 8154 |
|
|
CW = 8
|
| 8155 |
|
|
Module is correct for synthesis.
|
| 8156 |
|
|
|
| 8157 |
|
|
Analyzing module .
|
| 8158 |
|
|
Module is correct for synthesis.
|
| 8159 |
|
|
|
| 8160 |
|
|
Analyzing module .
|
| 8161 |
|
|
Module is correct for synthesis.
|
| 8162 |
|
|
|
| 8163 |
|
|
|
| 8164 |
|
|
=========================================================================
|
| 8165 |
|
|
* HDL Synthesis *
|
| 8166 |
|
|
=========================================================================
|
| 8167 |
|
|
|
| 8168 |
|
|
Synthesizing Unit .
|
| 8169 |
|
|
Related source file is "txmit.v".
|
| 8170 |
|
|
Found 1-bit register for signal .
|
| 8171 |
|
|
Found 1-bit register for signal .
|
| 8172 |
|
|
Found 1-bit register for signal .
|
| 8173 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 8174 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 8175 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 8176 |
|
|
Found 1-bit register for signal .
|
| 8177 |
|
|
Found 1-bit register for signal .
|
| 8178 |
|
|
Found 4-bit up counter for signal .
|
| 8179 |
|
|
Found 4-bit up counter for signal .
|
| 8180 |
|
|
Found 8-bit register for signal .
|
| 8181 |
|
|
Found 8-bit register for signal .
|
| 8182 |
|
|
Summary:
|
| 8183 |
|
|
inferred 2 Counter(s).
|
| 8184 |
|
|
inferred 21 D-type flip-flop(s).
|
| 8185 |
|
|
inferred 2 Comparator(s).
|
| 8186 |
|
|
inferred 1 Multiplexer(s).
|
| 8187 |
|
|
Unit synthesized.
|
| 8188 |
|
|
|
| 8189 |
|
|
|
| 8190 |
|
|
Synthesizing Unit .
|
| 8191 |
|
|
Related source file is "rcvr.v".
|
| 8192 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 8193 |
|
|
Found 1-bit register for signal .
|
| 8194 |
|
|
Found 1-bit register for signal .
|
| 8195 |
|
|
Found 1-bit register for signal .
|
| 8196 |
|
|
Found 8-bit tristate buffer for signal .
|
| 8197 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 8198 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 8199 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 8200 |
|
|
Found 1-bit register for signal .
|
| 8201 |
|
|
Found 1-bit register for signal .
|
| 8202 |
|
|
Found 4-bit register for signal .
|
| 8203 |
|
|
Found 4-bit up counter for signal .
|
| 8204 |
|
|
Found 8-bit register for signal .
|
| 8205 |
|
|
Found 7-bit register for signal >.
|
| 8206 |
|
|
Found 1-bit register for signal .
|
| 8207 |
|
|
Found 1-bit register for signal .
|
| 8208 |
|
|
Summary:
|
| 8209 |
|
|
inferred 1 Counter(s).
|
| 8210 |
|
|
inferred 26 D-type flip-flop(s).
|
| 8211 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 8212 |
|
|
inferred 1 Comparator(s).
|
| 8213 |
|
|
inferred 1 Multiplexer(s).
|
| 8214 |
|
|
inferred 8 Tristate(s).
|
| 8215 |
|
|
Unit synthesized.
|
| 8216 |
|
|
|
| 8217 |
|
|
|
| 8218 |
|
|
Synthesizing Unit .
|
| 8219 |
|
|
Related source file is "jkff.v".
|
| 8220 |
|
|
Found 1-bit register for signal .
|
| 8221 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 8222 |
|
|
Summary:
|
| 8223 |
|
|
inferred 1 D-type flip-flop(s).
|
| 8224 |
|
|
inferred 1 Multiplexer(s).
|
| 8225 |
|
|
Unit synthesized.
|
| 8226 |
|
|
|
| 8227 |
|
|
|
| 8228 |
|
|
Synthesizing Unit .
|
| 8229 |
|
|
Related source file is "switchsync.v".
|
| 8230 |
|
|
Found 1-bit register for signal .
|
| 8231 |
|
|
Found 1-bit register for signal .
|
| 8232 |
|
|
Summary:
|
| 8233 |
|
|
inferred 2 D-type flip-flop(s).
|
| 8234 |
|
|
Unit synthesized.
|
| 8235 |
|
|
|
| 8236 |
|
|
|
| 8237 |
|
|
Synthesizing Unit .
|
| 8238 |
|
|
Related source file is "maindcm.v".
|
| 8239 |
|
|
Unit synthesized.
|
| 8240 |
|
|
|
| 8241 |
|
|
|
| 8242 |
|
|
Synthesizing Unit .
|
| 8243 |
|
|
Related source file is "control.v".
|
| 8244 |
|
|
Found 1-bit register for signal .
|
| 8245 |
|
|
Found 1-bit register for signal .
|
| 8246 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 8247 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 8248 |
|
|
Found 3-bit up counter for signal .
|
| 8249 |
|
|
Summary:
|
| 8250 |
|
|
inferred 1 Counter(s).
|
| 8251 |
|
|
inferred 2 D-type flip-flop(s).
|
| 8252 |
|
|
inferred 2 Multiplexer(s).
|
| 8253 |
|
|
Unit synthesized.
|
| 8254 |
|
|
|
| 8255 |
|
|
|
| 8256 |
|
|
Synthesizing Unit .
|
| 8257 |
|
|
Related source file is "misc.v".
|
| 8258 |
|
|
Found 16-bit tristate buffer for signal .
|
| 8259 |
|
|
Summary:
|
| 8260 |
|
|
inferred 16 Tristate(s).
|
| 8261 |
|
|
Unit synthesized.
|
| 8262 |
|
|
|
| 8263 |
|
|
|
| 8264 |
|
|
Synthesizing Unit .
|
| 8265 |
|
|
Related source file is "misc.v".
|
| 8266 |
|
|
Found 16-bit tristate buffer for signal .
|
| 8267 |
|
|
Summary:
|
| 8268 |
|
|
inferred 16 Tristate(s).
|
| 8269 |
|
|
Unit synthesized.
|
| 8270 |
|
|
|
| 8271 |
|
|
|
| 8272 |
|
|
Synthesizing Unit .
|
| 8273 |
|
|
Related source file is "misc.v".
|
| 8274 |
|
|
Found 16-bit tristate buffer for signal .
|
| 8275 |
|
|
Summary:
|
| 8276 |
|
|
inferred 16 Tristate(s).
|
| 8277 |
|
|
Unit synthesized.
|
| 8278 |
|
|
|
| 8279 |
|
|
|
| 8280 |
|
|
Synthesizing Unit .
|
| 8281 |
|
|
Related source file is "misc.v".
|
| 8282 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 8283 |
|
|
Found 16-bit tristate buffer for signal .
|
| 8284 |
|
|
Found 12-bit register for signal .
|
| 8285 |
|
|
Summary:
|
| 8286 |
|
|
inferred 12 D-type flip-flop(s).
|
| 8287 |
|
|
inferred 16 Tristate(s).
|
| 8288 |
|
|
Unit synthesized.
|
| 8289 |
|
|
|
| 8290 |
|
|
|
| 8291 |
|
|
Synthesizing Unit .
|
| 8292 |
|
|
Related source file is "idecode.v".
|
| 8293 |
|
|
Unit synthesized.
|
| 8294 |
|
|
|
| 8295 |
|
|
|
| 8296 |
|
|
Synthesizing Unit .
|
| 8297 |
|
|
Related source file is "control.v".
|
| 8298 |
|
|
Unit synthesized.
|
| 8299 |
|
|
|
| 8300 |
|
|
|
| 8301 |
|
|
Synthesizing Unit .
|
| 8302 |
|
|
Related source file is "alu.v".
|
| 8303 |
|
|
Found 16-bit tristate buffer for signal .
|
| 8304 |
|
|
Found 17-bit subtractor for signal <$AUX_108>.
|
| 8305 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 8306 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 8307 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 8308 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 8309 |
|
|
Summary:
|
| 8310 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 8311 |
|
|
inferred 16 Tristate(s).
|
| 8312 |
|
|
Unit synthesized.
|
| 8313 |
|
|
|
| 8314 |
|
|
|
| 8315 |
|
|
Synthesizing Unit .
|
| 8316 |
|
|
Related source file is "misc.v".
|
| 8317 |
|
|
Unit synthesized.
|
| 8318 |
|
|
|
| 8319 |
|
|
|
| 8320 |
|
|
Synthesizing Unit .
|
| 8321 |
|
|
Related source file is "misc.v".
|
| 8322 |
|
|
Unit synthesized.
|
| 8323 |
|
|
|
| 8324 |
|
|
|
| 8325 |
|
|
Synthesizing Unit .
|
| 8326 |
|
|
Related source file is "misc.v".
|
| 8327 |
|
|
Unit synthesized.
|
| 8328 |
|
|
|
| 8329 |
|
|
|
| 8330 |
|
|
Synthesizing Unit .
|
| 8331 |
|
|
Related source file is "misc.v".
|
| 8332 |
|
|
Unit synthesized.
|
| 8333 |
|
|
|
| 8334 |
|
|
|
| 8335 |
|
|
Synthesizing Unit .
|
| 8336 |
|
|
Related source file is "misc.v".
|
| 8337 |
|
|
Found 16-bit tristate buffer for signal .
|
| 8338 |
|
|
Found 16-bit register for signal .
|
| 8339 |
|
|
Summary:
|
| 8340 |
|
|
inferred 16 D-type flip-flop(s).
|
| 8341 |
|
|
inferred 16 Tristate(s).
|
| 8342 |
|
|
Unit synthesized.
|
| 8343 |
|
|
|
| 8344 |
|
|
|
| 8345 |
|
|
Synthesizing Unit .
|
| 8346 |
|
|
Related source file is "io.v".
|
| 8347 |
|
|
Found 1-bit register for signal .
|
| 8348 |
|
|
Found 1-bit register for signal .
|
| 8349 |
|
|
Found 1-bit register for signal .
|
| 8350 |
|
|
Found 1-bit register for signal .
|
| 8351 |
|
|
Found 1-bit register for signal .
|
| 8352 |
|
|
Found 1-bit register for signal .
|
| 8353 |
|
|
Found 19-bit down counter for signal .
|
| 8354 |
|
|
Found 1-bit register for signal .
|
| 8355 |
|
|
Found 1-bit xor2 for signal .
|
| 8356 |
|
|
Summary:
|
| 8357 |
|
|
inferred 1 Counter(s).
|
| 8358 |
|
|
inferred 7 D-type flip-flop(s).
|
| 8359 |
|
|
Unit synthesized.
|
| 8360 |
|
|
|
| 8361 |
|
|
|
| 8362 |
|
|
Synthesizing Unit .
|
| 8363 |
|
|
Related source file is "io.v".
|
| 8364 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 8365 |
|
|
Found 1-bit register for signal .
|
| 8366 |
|
|
Found 1-bit register for signal .
|
| 8367 |
|
|
Found 1-bit register for signal .
|
| 8368 |
|
|
Found 1-bit register for signal .
|
| 8369 |
|
|
Found 1-bit register for signal .
|
| 8370 |
|
|
Found 1-bit register for signal .
|
| 8371 |
|
|
Found 1-bit register for signal .
|
| 8372 |
|
|
Found 1-bit register for signal .
|
| 8373 |
|
|
Found 1-bit register for signal .
|
| 8374 |
|
|
Found 1-bit register for signal .
|
| 8375 |
|
|
Found 1-bit register for signal .
|
| 8376 |
|
|
Found 1-bit register for signal .
|
| 8377 |
|
|
Found 24-bit up counter for signal .
|
| 8378 |
|
|
Found 1-of-4 decoder for signal .
|
| 8379 |
|
|
Found 2-bit down counter for signal .
|
| 8380 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 8381 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 8382 |
|
|
Summary:
|
| 8383 |
|
|
inferred 1 ROM(s).
|
| 8384 |
|
|
inferred 2 Counter(s).
|
| 8385 |
|
|
inferred 12 D-type flip-flop(s).
|
| 8386 |
|
|
inferred 9 Multiplexer(s).
|
| 8387 |
|
|
inferred 1 Decoder(s).
|
| 8388 |
|
|
Unit synthesized.
|
| 8389 |
|
|
|
| 8390 |
|
|
|
| 8391 |
|
|
Synthesizing Unit .
|
| 8392 |
|
|
Related source file is "uart.v".
|
| 8393 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 8394 |
|
|
Found 1-bit register for signal .
|
| 8395 |
|
|
Found 8-bit up counter for signal .
|
| 8396 |
|
|
Found 1-bit register for signal .
|
| 8397 |
|
|
Summary:
|
| 8398 |
|
|
inferred 1 Counter(s).
|
| 8399 |
|
|
inferred 2 D-type flip-flop(s).
|
| 8400 |
|
|
inferred 1 Multiplexer(s).
|
| 8401 |
|
|
Unit synthesized.
|
| 8402 |
|
|
|
| 8403 |
|
|
|
| 8404 |
|
|
Synthesizing Unit .
|
| 8405 |
|
|
Related source file is "top.v".
|
| 8406 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 8407 |
|
|
Found 16-bit tristate buffer for signal .
|
| 8408 |
|
|
Found 1-bit register for signal .
|
| 8409 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 8410 |
|
|
Found 16-bit tristate buffer for signal .
|
| 8411 |
|
|
Found 1-bit register for signal .
|
| 8412 |
|
|
Found 1-bit register for signal .
|
| 8413 |
|
|
Found 1-bit register for signal .
|
| 8414 |
|
|
Summary:
|
| 8415 |
|
|
inferred 4 D-type flip-flop(s).
|
| 8416 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 8417 |
|
|
inferred 96 Tristate(s).
|
| 8418 |
|
|
Unit synthesized.
|
| 8419 |
|
|
|
| 8420 |
|
|
|
| 8421 |
|
|
Synthesizing Unit .
|
| 8422 |
|
|
Related source file is "FrontPanel.v".
|
| 8423 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 8424 |
|
|
Found finite state machine for signal .
|
| 8425 |
|
|
-----------------------------------------------------------------------
|
| 8426 |
|
|
| States | 6 |
|
| 8427 |
|
|
| Transitions | 6 |
|
| 8428 |
|
|
| Inputs | 0 |
|
| 8429 |
|
|
| Outputs | 12 |
|
| 8430 |
|
|
| Clock | clockin (rising_edge) |
|
| 8431 |
|
|
| Clock enable | select (positive) |
|
| 8432 |
|
|
| Reset | clear (positive) |
|
| 8433 |
|
|
| Reset type | synchronous |
|
| 8434 |
|
|
| Reset State | 000001 |
|
| 8435 |
|
|
| Encoding | automatic |
|
| 8436 |
|
|
| Implementation | LUT |
|
| 8437 |
|
|
-----------------------------------------------------------------------
|
| 8438 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 8439 |
|
|
Found 4-bit register for signal .
|
| 8440 |
|
|
Found 16-bit register for signal .
|
| 8441 |
|
|
Summary:
|
| 8442 |
|
|
inferred 1 Finite State Machine(s).
|
| 8443 |
|
|
inferred 16 D-type flip-flop(s).
|
| 8444 |
|
|
inferred 16 Multiplexer(s).
|
| 8445 |
|
|
Unit synthesized.
|
| 8446 |
|
|
|
| 8447 |
|
|
|
| 8448 |
|
|
Synthesizing Unit .
|
| 8449 |
|
|
Related source file is "topbox.v".
|
| 8450 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 8451 |
|
|
Found 16-bit tristate buffer for signal .
|
| 8452 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 8453 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 8454 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 8455 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 8456 |
|
|
Found 4-bit register for signal .
|
| 8457 |
|
|
Found 1-bit register for signal .
|
| 8458 |
|
|
Found 1-bit register for signal .
|
| 8459 |
|
|
Found 16-bit register for signal .
|
| 8460 |
|
|
Summary:
|
| 8461 |
|
|
inferred 22 D-type flip-flop(s).
|
| 8462 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 8463 |
|
|
inferred 6 Multiplexer(s).
|
| 8464 |
|
|
inferred 48 Tristate(s).
|
| 8465 |
|
|
Unit synthesized.
|
| 8466 |
|
|
|
| 8467 |
|
|
|
| 8468 |
|
|
=========================================================================
|
| 8469 |
|
|
* Advanced HDL Synthesis *
|
| 8470 |
|
|
=========================================================================
|
| 8471 |
|
|
|
| 8472 |
|
|
Advanced RAM inference ...
|
| 8473 |
|
|
Advanced multiplier inference ...
|
| 8474 |
|
|
Advanced Registered AddSub inference ...
|
| 8475 |
|
|
Analyzing FSM for best encoding.
|
| 8476 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 8477 |
|
|
--------------------
|
| 8478 |
|
|
State | Encoding
|
| 8479 |
|
|
--------------------
|
| 8480 |
|
|
000001 | 100000
|
| 8481 |
|
|
000010 | 010000
|
| 8482 |
|
|
000100 | 001000
|
| 8483 |
|
|
001000 | 000100
|
| 8484 |
|
|
010000 | 000010
|
| 8485 |
|
|
100000 | 000001
|
| 8486 |
|
|
--------------------
|
| 8487 |
|
|
Dynamic shift register inference ...
|
| 8488 |
|
|
|
| 8489 |
|
|
=========================================================================
|
| 8490 |
|
|
HDL Synthesis Report
|
| 8491 |
|
|
|
| 8492 |
|
|
Macro Statistics
|
| 8493 |
|
|
# FSMs : 1
|
| 8494 |
|
|
# ROMs : 1
|
| 8495 |
|
|
16x7-bit ROM : 1
|
| 8496 |
|
|
# Adders/Subtractors : 5
|
| 8497 |
|
|
12-bit adder carry out : 1
|
| 8498 |
|
|
16-bit adder carry out : 1
|
| 8499 |
|
|
17-bit subtractor : 1
|
| 8500 |
|
|
4-bit adder : 2
|
| 8501 |
|
|
# Counters : 10
|
| 8502 |
|
|
19-bit down counter : 3
|
| 8503 |
|
|
2-bit down counter : 1
|
| 8504 |
|
|
24-bit up counter : 1
|
| 8505 |
|
|
3-bit up counter : 1
|
| 8506 |
|
|
4-bit up counter : 3
|
| 8507 |
|
|
8-bit up counter : 1
|
| 8508 |
|
|
# Registers : 138
|
| 8509 |
|
|
1-bit register : 125
|
| 8510 |
|
|
12-bit register : 4
|
| 8511 |
|
|
16-bit register : 4
|
| 8512 |
|
|
4-bit register : 3
|
| 8513 |
|
|
8-bit register : 2
|
| 8514 |
|
|
# Comparators : 3
|
| 8515 |
|
|
4-bit comparator greater : 2
|
| 8516 |
|
|
4-bit comparator less : 1
|
| 8517 |
|
|
# Multiplexers : 15
|
| 8518 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 8519 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 8520 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 8521 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 8522 |
|
|
# Decoders : 1
|
| 8523 |
|
|
1-of-4 decoder : 1
|
| 8524 |
|
|
# Tristates : 97
|
| 8525 |
|
|
1-bit tristate buffer : 80
|
| 8526 |
|
|
16-bit tristate buffer : 16
|
| 8527 |
|
|
8-bit tristate buffer : 1
|
| 8528 |
|
|
# Xors : 6
|
| 8529 |
|
|
1-bit xor2 : 5
|
| 8530 |
|
|
16-bit xor2 : 1
|
| 8531 |
|
|
|
| 8532 |
|
|
=========================================================================
|
| 8533 |
|
|
|
| 8534 |
|
|
=========================================================================
|
| 8535 |
|
|
* Low Level Synthesis *
|
| 8536 |
|
|
=========================================================================
|
| 8537 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 8538 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 8539 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 8540 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 8541 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 8542 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 8543 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 8544 |
|
|
|
| 8545 |
|
|
Optimizing unit ...
|
| 8546 |
|
|
|
| 8547 |
|
|
Optimizing unit ...
|
| 8548 |
|
|
|
| 8549 |
|
|
Optimizing unit ...
|
| 8550 |
|
|
|
| 8551 |
|
|
Optimizing unit ...
|
| 8552 |
|
|
|
| 8553 |
|
|
Optimizing unit ...
|
| 8554 |
|
|
|
| 8555 |
|
|
Optimizing unit ...
|
| 8556 |
|
|
|
| 8557 |
|
|
Optimizing unit ...
|
| 8558 |
|
|
|
| 8559 |
|
|
Optimizing unit ...
|
| 8560 |
|
|
|
| 8561 |
|
|
Optimizing unit ...
|
| 8562 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 8563 |
|
|
|
| 8564 |
|
|
Mapping all equations...
|
| 8565 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 8566 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 8567 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 8568 |
|
|
Building and optimizing final netlist ...
|
| 8569 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
|
| 8570 |
|
|
FlipFlop CPU/IR/regvalue_0 has been replicated 3 time(s)
|
| 8571 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
|
| 8572 |
|
|
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
|
| 8573 |
|
|
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
|
| 8574 |
|
|
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
|
| 8575 |
|
|
FlipFlop CPU/IR/regvalue_15 has been replicated 1 time(s)
|
| 8576 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
|
| 8577 |
|
|
FlipFlop CPU/IR/regvalue_4 has been replicated 1 time(s)
|
| 8578 |
|
|
FlipFlop CPU/IR/regvalue_6 has been replicated 1 time(s)
|
| 8579 |
|
|
FlipFlop CPU/ctl/sim/counter_0 has been replicated 4 time(s)
|
| 8580 |
|
|
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
|
| 8581 |
|
|
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
|
| 8582 |
|
|
FlipFlop loadnow has been replicated 2 time(s)
|
| 8583 |
|
|
|
| 8584 |
|
|
=========================================================================
|
| 8585 |
|
|
* Final Report *
|
| 8586 |
|
|
=========================================================================
|
| 8587 |
|
|
|
| 8588 |
|
|
Device utilization summary:
|
| 8589 |
|
|
---------------------------
|
| 8590 |
|
|
|
| 8591 |
|
|
Selected Device : 3s200ft256-4
|
| 8592 |
|
|
|
| 8593 |
|
|
Number of Slices: 611 out of 1920 31%
|
| 8594 |
|
|
Number of Slice Flip Flops: 393 out of 3840 10%
|
| 8595 |
|
|
Number of 4 input LUTs: 1081 out of 3840 28%
|
| 8596 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 8597 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 8598 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 8599 |
|
|
|
| 8600 |
|
|
|
| 8601 |
|
|
=========================================================================
|
| 8602 |
|
|
TIMING REPORT
|
| 8603 |
|
|
|
| 8604 |
|
|
|
| 8605 |
|
|
Clock Information:
|
| 8606 |
|
|
------------------
|
| 8607 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 8608 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 8609 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 8610 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 393 |
|
| 8611 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 8612 |
|
|
|
| 8613 |
|
|
Timing Summary:
|
| 8614 |
|
|
---------------
|
| 8615 |
|
|
Speed Grade: -4
|
| 8616 |
|
|
|
| 8617 |
|
|
Minimum period: 14.217ns (Maximum Frequency: 70.338MHz)
|
| 8618 |
|
|
Minimum input arrival time before clock: 10.576ns
|
| 8619 |
|
|
Maximum output required time after clock: 24.383ns
|
| 8620 |
|
|
Maximum combinational path delay: 14.555ns
|
| 8621 |
|
|
|
| 8622 |
|
|
=========================================================================
|
| 8623 |
|
|
|
| 8624 |
|
|
|
| 8625 |
|
|
|
| 8626 |
|
|
|
| 8627 |
|
|
Started process "Translate".
|
| 8628 |
|
|
|
| 8629 |
|
|
|
| 8630 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 8631 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 8632 |
|
|
|
| 8633 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 8634 |
|
|
|
| 8635 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 8636 |
|
|
|
| 8637 |
|
|
Checking timing specifications ...
|
| 8638 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 8639 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 8640 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 8641 |
|
|
20.408000 nS HIGH 50.000000%
|
| 8642 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 8643 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 8644 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 8645 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 8646 |
|
|
from this group.
|
| 8647 |
|
|
Checking expanded design ...
|
| 8648 |
|
|
|
| 8649 |
|
|
NGDBUILD Design Results Summary:
|
| 8650 |
|
|
Number of errors: 0
|
| 8651 |
|
|
Number of warnings: 1
|
| 8652 |
|
|
|
| 8653 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 8654 |
|
|
|
| 8655 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 8656 |
|
|
|
| 8657 |
|
|
NGDBUILD done.
|
| 8658 |
|
|
|
| 8659 |
|
|
|
| 8660 |
|
|
|
| 8661 |
|
|
|
| 8662 |
|
|
Started process "Map".
|
| 8663 |
|
|
|
| 8664 |
|
|
Using target part "3s200ft256-4".
|
| 8665 |
|
|
Mapping design into LUTs...
|
| 8666 |
|
|
Running directed packing...
|
| 8667 |
|
|
Running delay-based LUT packing...
|
| 8668 |
|
|
Running related packing...
|
| 8669 |
|
|
|
| 8670 |
|
|
Design Summary:
|
| 8671 |
|
|
Number of errors: 0
|
| 8672 |
|
|
Number of warnings: 2
|
| 8673 |
|
|
Logic Utilization:
|
| 8674 |
|
|
Number of Slice Flip Flops: 367 out of 3,840 9%
|
| 8675 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 8676 |
|
|
Logic Distribution:
|
| 8677 |
|
|
Number of occupied Slices: 694 out of 1,920 36%
|
| 8678 |
|
|
Number of Slices containing only related logic: 694 out of 694 100%
|
| 8679 |
|
|
Number of Slices containing unrelated logic: 0 out of 694 0%
|
| 8680 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 8681 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 8682 |
|
|
Number used as logic: 1,131
|
| 8683 |
|
|
Number used as a route-thru: 4
|
| 8684 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 8685 |
|
|
IOB Flip Flops: 26
|
| 8686 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 8687 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 8688 |
|
|
|
| 8689 |
|
|
Total equivalent gate count for design: 17,815
|
| 8690 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 8691 |
|
|
Peak Memory Usage: 114 MB
|
| 8692 |
|
|
|
| 8693 |
|
|
NOTES:
|
| 8694 |
|
|
|
| 8695 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 8696 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 8697 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 8698 |
|
|
the best timing performance.
|
| 8699 |
|
|
|
| 8700 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 8701 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 8702 |
|
|
related logic packing.
|
| 8703 |
|
|
|
| 8704 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 8705 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 8706 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 8707 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 8708 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 8709 |
|
|
of your design.
|
| 8710 |
|
|
|
| 8711 |
|
|
Mapping completed.
|
| 8712 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 8713 |
|
|
|
| 8714 |
|
|
|
| 8715 |
|
|
|
| 8716 |
|
|
|
| 8717 |
|
|
Started process "Place & Route".
|
| 8718 |
|
|
|
| 8719 |
|
|
|
| 8720 |
|
|
|
| 8721 |
|
|
|
| 8722 |
|
|
Constraints file: topbox.pcf.
|
| 8723 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 8724 |
|
|
C:/Xilinx71.
|
| 8725 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 8726 |
|
|
|
| 8727 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 8728 |
|
|
Celsius)
|
| 8729 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 8730 |
|
|
|
| 8731 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 8732 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 8733 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 8734 |
|
|
ps (24.00 Mhz).
|
| 8735 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 8736 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 8737 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 8738 |
|
|
(210.04 Mhz).
|
| 8739 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 8740 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 8741 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 8742 |
|
|
ps (24.00 Mhz).
|
| 8743 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 8744 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 8745 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 8746 |
|
|
(210.04 Mhz).
|
| 8747 |
|
|
|
| 8748 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 8749 |
|
|
|
| 8750 |
|
|
|
| 8751 |
|
|
Device Utilization Summary:
|
| 8752 |
|
|
|
| 8753 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 8754 |
|
|
Number of DCMs 1 out of 4 25%
|
| 8755 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 8756 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 8757 |
|
|
|
| 8758 |
|
|
Number of Slices 694 out of 1920 36%
|
| 8759 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 8760 |
|
|
|
| 8761 |
|
|
|
| 8762 |
|
|
|
| 8763 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 8764 |
|
|
Placer effort level (-pl): Standard (set by user)
|
| 8765 |
|
|
Placer cost table entry (-t): 1
|
| 8766 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 8767 |
|
|
|
| 8768 |
|
|
Starting initial Timing Analysis. REAL time: 2 secs
|
| 8769 |
|
|
Finished initial Timing Analysis. REAL time: 2 secs
|
| 8770 |
|
|
|
| 8771 |
|
|
|
| 8772 |
|
|
Starting Placer
|
| 8773 |
|
|
|
| 8774 |
|
|
Phase 1.1
|
| 8775 |
|
|
Phase 1.1 (Checksum:98af6c) REAL time: 3 secs
|
| 8776 |
|
|
|
| 8777 |
|
|
Phase 2.31
|
| 8778 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs
|
| 8779 |
|
|
|
| 8780 |
|
|
Phase 3.2
|
| 8781 |
|
|
.
|
| 8782 |
|
|
|
| 8783 |
|
|
|
| 8784 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 5 secs
|
| 8785 |
|
|
|
| 8786 |
|
|
Phase 4.8
|
| 8787 |
|
|
................
|
| 8788 |
|
|
.....
|
| 8789 |
|
|
Phase 4.8 (Checksum:a5b7b7) REAL time: 6 secs
|
| 8790 |
|
|
|
| 8791 |
|
|
Phase 5.5
|
| 8792 |
|
|
Phase 5.5 (Checksum:2faf07b) REAL time: 6 secs
|
| 8793 |
|
|
|
| 8794 |
|
|
Phase 6.18
|
| 8795 |
|
|
Phase 6.18 (Checksum:39386fa) REAL time: 8 secs
|
| 8796 |
|
|
|
| 8797 |
|
|
Phase 7.5
|
| 8798 |
|
|
Phase 7.5 (Checksum:42c1d79) REAL time: 8 secs
|
| 8799 |
|
|
|
| 8800 |
|
|
Writing design to file topbox.ncd
|
| 8801 |
|
|
|
| 8802 |
|
|
|
| 8803 |
|
|
Total REAL time to Placer completion: 8 secs
|
| 8804 |
|
|
Total CPU time to Placer completion: 7 secs
|
| 8805 |
|
|
|
| 8806 |
|
|
Starting Router
|
| 8807 |
|
|
|
| 8808 |
|
|
Phase 1: 4717 unrouted; REAL time: 8 secs
|
| 8809 |
|
|
|
| 8810 |
|
|
Phase 2: 4443 unrouted; REAL time: 8 secs
|
| 8811 |
|
|
|
| 8812 |
|
|
Phase 3: 2140 unrouted; REAL time: 9 secs
|
| 8813 |
|
|
|
| 8814 |
|
|
Phase 4: 2140 unrouted; (0) REAL time: 9 secs
|
| 8815 |
|
|
|
| 8816 |
|
|
Phase 5: 2140 unrouted; (0) REAL time: 9 secs
|
| 8817 |
|
|
|
| 8818 |
|
|
Phase 6: 2140 unrouted; (0) REAL time: 10 secs
|
| 8819 |
|
|
|
| 8820 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 11 secs
|
| 8821 |
|
|
|
| 8822 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 12 secs
|
| 8823 |
|
|
|
| 8824 |
|
|
|
| 8825 |
|
|
Total REAL time to Router completion: 12 secs
|
| 8826 |
|
|
Total CPU time to Router completion: 11 secs
|
| 8827 |
|
|
|
| 8828 |
|
|
Generating "PAR" statistics.
|
| 8829 |
|
|
|
| 8830 |
|
|
**************************
|
| 8831 |
|
|
Generating Clock Report
|
| 8832 |
|
|
**************************
|
| 8833 |
|
|
|
| 8834 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 8835 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 8836 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 8837 |
|
|
| clk | BUFGMUX3| No | 255 | 0.042 | 1.052 |
|
| 8838 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 8839 |
|
|
|
| 8840 |
|
|
Timing Score: 0
|
| 8841 |
|
|
|
| 8842 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 8843 |
|
|
This may be due to a setup or hold violation.
|
| 8844 |
|
|
|
| 8845 |
|
|
--------------------------------------------------------------------------------
|
| 8846 |
|
|
Constraint | Requested | Actual | Logic
|
| 8847 |
|
|
| | | Levels
|
| 8848 |
|
|
--------------------------------------------------------------------------------
|
| 8849 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 8850 |
|
|
HIGH 50% | | |
|
| 8851 |
|
|
--------------------------------------------------------------------------------
|
| 8852 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 30.474ns | 7
|
| 8853 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 8854 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 8855 |
|
|
--------------------------------------------------------------------------------
|
| 8856 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 37.488ns | 6
|
| 8857 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 8858 |
|
|
HIGH 50% | | |
|
| 8859 |
|
|
--------------------------------------------------------------------------------
|
| 8860 |
|
|
|
| 8861 |
|
|
|
| 8862 |
|
|
All constraints were met.
|
| 8863 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 8864 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 8865 |
|
|
Generating Pad Report.
|
| 8866 |
|
|
|
| 8867 |
|
|
All signals are completely routed.
|
| 8868 |
|
|
|
| 8869 |
|
|
Total REAL time to PAR completion: 13 secs
|
| 8870 |
|
|
Total CPU time to PAR completion: 12 secs
|
| 8871 |
|
|
|
| 8872 |
|
|
Peak Memory Usage: 96 MB
|
| 8873 |
|
|
|
| 8874 |
|
|
Placement: Completed - No errors found.
|
| 8875 |
|
|
Routing: Completed - No errors found.
|
| 8876 |
|
|
Timing: Completed - No errors found.
|
| 8877 |
|
|
|
| 8878 |
|
|
Number of error messages: 0
|
| 8879 |
|
|
Number of warning messages: 4
|
| 8880 |
|
|
Number of info messages: 0
|
| 8881 |
|
|
|
| 8882 |
|
|
Writing design to file topbox.ncd
|
| 8883 |
|
|
|
| 8884 |
|
|
|
| 8885 |
|
|
|
| 8886 |
|
|
PAR done!
|
| 8887 |
|
|
|
| 8888 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 8889 |
|
|
|
| 8890 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 8891 |
|
|
C:/Xilinx71.
|
| 8892 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 8893 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 8894 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 8895 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 8896 |
|
|
ps (24.00 Mhz).
|
| 8897 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 8898 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 8899 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 8900 |
|
|
(210.04 Mhz).
|
| 8901 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 8902 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 8903 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 8904 |
|
|
ps (24.00 Mhz).
|
| 8905 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 8906 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 8907 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 8908 |
|
|
(210.04 Mhz).
|
| 8909 |
|
|
|
| 8910 |
|
|
Analysis completed Sun Sep 24 13:19:05 2006
|
| 8911 |
|
|
--------------------------------------------------------------------------------
|
| 8912 |
|
|
|
| 8913 |
|
|
Generating Report ...
|
| 8914 |
|
|
|
| 8915 |
|
|
Number of warnings: 4
|
| 8916 |
|
|
Total time: 2 secs
|
| 8917 |
|
|
|
| 8918 |
|
|
|
| 8919 |
|
|
|
| 8920 |
|
|
|
| 8921 |
|
|
|
| 8922 |
|
|
|
| 8923 |
|
|
|
| 8924 |
|
|
Started process "Generate Programming File".
|
| 8925 |
|
|
|
| 8926 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 8927 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 8928 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 8929 |
|
|
Interactive Data Sheet.
|
| 8930 |
|
|
|
| 8931 |
|
|
|
| 8932 |
|
|
Project Navigator Auto-Make Log File
|
| 8933 |
|
|
-------------------------------------
|
| 8934 |
|
|
|
| 8935 |
|
|
|
| 8936 |
|
|
|
| 8937 |
|
|
|
| 8938 |
|
|
Started process "Map".
|
| 8939 |
|
|
|
| 8940 |
|
|
Using target part "3s200ft256-4".
|
| 8941 |
|
|
Mapping design into LUTs...
|
| 8942 |
|
|
Running directed packing...
|
| 8943 |
|
|
Running delay-based LUT packing...
|
| 8944 |
|
|
Running timing-driven packing...
|
| 8945 |
|
|
|
| 8946 |
|
|
Phase 1.1
|
| 8947 |
|
|
Phase 1.1 (Checksum:98d72d) REAL time: 1 secs
|
| 8948 |
|
|
|
| 8949 |
|
|
Phase 2.31
|
| 8950 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
|
| 8951 |
|
|
|
| 8952 |
|
|
Phase 3.2
|
| 8953 |
|
|
.
|
| 8954 |
|
|
|
| 8955 |
|
|
|
| 8956 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
|
| 8957 |
|
|
|
| 8958 |
|
|
Phase 4.4
|
| 8959 |
|
|
.............................
|
| 8960 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 5 secs
|
| 8961 |
|
|
|
| 8962 |
|
|
Phase 5.28
|
| 8963 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 5 secs
|
| 8964 |
|
|
|
| 8965 |
|
|
Phase 6.8
|
| 8966 |
|
|
................................................................................
|
| 8967 |
|
|
.....
|
| 8968 |
|
|
......................................................................................................................................................
|
| 8969 |
|
|
...............
|
| 8970 |
|
|
...............
|
| 8971 |
|
|
Phase 6.8 (Checksum:ace7a1) REAL time: 22 secs
|
| 8972 |
|
|
|
| 8973 |
|
|
Phase 7.29
|
| 8974 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 22 secs
|
| 8975 |
|
|
|
| 8976 |
|
|
Phase 8.5
|
| 8977 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 22 secs
|
| 8978 |
|
|
|
| 8979 |
|
|
Phase 9.18
|
| 8980 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 31 secs
|
| 8981 |
|
|
|
| 8982 |
|
|
Phase 10.5
|
| 8983 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 31 secs
|
| 8984 |
|
|
|
| 8985 |
|
|
Invoking physical synthesis ...
|
| 8986 |
|
|
|
| 8987 |
|
|
Physical synthesis completed.
|
| 8988 |
|
|
|
| 8989 |
|
|
Design Summary:
|
| 8990 |
|
|
Number of errors: 0
|
| 8991 |
|
|
Number of warnings: 11
|
| 8992 |
|
|
Logic Utilization:
|
| 8993 |
|
|
Number of Slice Flip Flops: 366 out of 3,840 9%
|
| 8994 |
|
|
Number of 4 input LUTs: 1,146 out of 3,840 29%
|
| 8995 |
|
|
Logic Distribution:
|
| 8996 |
|
|
Number of occupied Slices: 759 out of 1,920 39%
|
| 8997 |
|
|
Number of Slices containing only related logic: 759 out of 759 100%
|
| 8998 |
|
|
Number of Slices containing unrelated logic: 0 out of 759 0%
|
| 8999 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 9000 |
|
|
Total Number 4 input LUTs: 1,150 out of 3,840 29%
|
| 9001 |
|
|
Number used as logic: 1,146
|
| 9002 |
|
|
Number used as a route-thru: 4
|
| 9003 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 9004 |
|
|
IOB Flip Flops: 26
|
| 9005 |
|
|
Number of Block RAMs: 1 out of 12 8%
|
| 9006 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 9007 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 9008 |
|
|
|
| 9009 |
|
|
Total equivalent gate count for design: 83,433
|
| 9010 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 9011 |
|
|
Peak Memory Usage: 154 MB
|
| 9012 |
|
|
|
| 9013 |
|
|
Mapping completed.
|
| 9014 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 9015 |
|
|
|
| 9016 |
|
|
|
| 9017 |
|
|
|
| 9018 |
|
|
|
| 9019 |
|
|
Started process "Place & Route".
|
| 9020 |
|
|
|
| 9021 |
|
|
|
| 9022 |
|
|
|
| 9023 |
|
|
|
| 9024 |
|
|
Constraints file: topbox.pcf.
|
| 9025 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 9026 |
|
|
C:/Xilinx71.
|
| 9027 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 9028 |
|
|
|
| 9029 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 9030 |
|
|
Celsius)
|
| 9031 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 9032 |
|
|
|
| 9033 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 9034 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9035 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9036 |
|
|
ps (24.00 Mhz).
|
| 9037 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 9038 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9039 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9040 |
|
|
(210.04 Mhz).
|
| 9041 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9042 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9043 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9044 |
|
|
ps (24.00 Mhz).
|
| 9045 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9046 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9047 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9048 |
|
|
(210.04 Mhz).
|
| 9049 |
|
|
|
| 9050 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 9051 |
|
|
|
| 9052 |
|
|
|
| 9053 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 9054 |
|
|
achieve better performance.
|
| 9055 |
|
|
|
| 9056 |
|
|
Device Utilization Summary:
|
| 9057 |
|
|
|
| 9058 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 9059 |
|
|
Number of DCMs 1 out of 4 25%
|
| 9060 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 9061 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 9062 |
|
|
|
| 9063 |
|
|
Number of RAMB16s 1 out of 12 8%
|
| 9064 |
|
|
Number of Slices 759 out of 1920 39%
|
| 9065 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 9066 |
|
|
|
| 9067 |
|
|
|
| 9068 |
|
|
|
| 9069 |
|
|
Overall effort level (-ol): High (set by user)
|
| 9070 |
|
|
Router effort level (-rl): High (set by user)
|
| 9071 |
|
|
|
| 9072 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 9073 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 9074 |
|
|
|
| 9075 |
|
|
Starting Router
|
| 9076 |
|
|
|
| 9077 |
|
|
Phase 1: 5000 unrouted; REAL time: 4 secs
|
| 9078 |
|
|
|
| 9079 |
|
|
Phase 2: 4653 unrouted; REAL time: 4 secs
|
| 9080 |
|
|
|
| 9081 |
|
|
Phase 3: 2167 unrouted; REAL time: 5 secs
|
| 9082 |
|
|
|
| 9083 |
|
|
Phase 4: 2167 unrouted; (0) REAL time: 5 secs
|
| 9084 |
|
|
|
| 9085 |
|
|
Phase 5: 2167 unrouted; (0) REAL time: 6 secs
|
| 9086 |
|
|
|
| 9087 |
|
|
Phase 6: 2167 unrouted; (0) REAL time: 6 secs
|
| 9088 |
|
|
|
| 9089 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 8 secs
|
| 9090 |
|
|
|
| 9091 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 8 secs
|
| 9092 |
|
|
|
| 9093 |
|
|
|
| 9094 |
|
|
Total REAL time to Router completion: 9 secs
|
| 9095 |
|
|
Total CPU time to Router completion: 8 secs
|
| 9096 |
|
|
|
| 9097 |
|
|
Generating "PAR" statistics.
|
| 9098 |
|
|
|
| 9099 |
|
|
**************************
|
| 9100 |
|
|
Generating Clock Report
|
| 9101 |
|
|
**************************
|
| 9102 |
|
|
|
| 9103 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9104 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 9105 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9106 |
|
|
| clk | BUFGMUX2| No | 323 | 0.041 | 1.051 |
|
| 9107 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9108 |
|
|
|
| 9109 |
|
|
Timing Score: 0
|
| 9110 |
|
|
|
| 9111 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 9112 |
|
|
This may be due to a setup or hold violation.
|
| 9113 |
|
|
|
| 9114 |
|
|
--------------------------------------------------------------------------------
|
| 9115 |
|
|
Constraint | Requested | Actual | Logic
|
| 9116 |
|
|
| | | Levels
|
| 9117 |
|
|
--------------------------------------------------------------------------------
|
| 9118 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 9119 |
|
|
HIGH 50% | | |
|
| 9120 |
|
|
--------------------------------------------------------------------------------
|
| 9121 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 30.474ns | 7
|
| 9122 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 9123 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 9124 |
|
|
--------------------------------------------------------------------------------
|
| 9125 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 38.970ns | 7
|
| 9126 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 9127 |
|
|
HIGH 50% | | |
|
| 9128 |
|
|
--------------------------------------------------------------------------------
|
| 9129 |
|
|
|
| 9130 |
|
|
|
| 9131 |
|
|
All constraints were met.
|
| 9132 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 9133 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 9134 |
|
|
Generating Pad Report.
|
| 9135 |
|
|
|
| 9136 |
|
|
All signals are completely routed.
|
| 9137 |
|
|
|
| 9138 |
|
|
Total REAL time to PAR completion: 10 secs
|
| 9139 |
|
|
Total CPU time to PAR completion: 9 secs
|
| 9140 |
|
|
|
| 9141 |
|
|
Peak Memory Usage: 93 MB
|
| 9142 |
|
|
|
| 9143 |
|
|
Placer: Not run.
|
| 9144 |
|
|
Routing: Completed - No errors found.
|
| 9145 |
|
|
Timing: Completed - No errors found.
|
| 9146 |
|
|
|
| 9147 |
|
|
Number of error messages: 0
|
| 9148 |
|
|
Number of warning messages: 4
|
| 9149 |
|
|
Number of info messages: 1
|
| 9150 |
|
|
|
| 9151 |
|
|
Writing design to file topbox.ncd
|
| 9152 |
|
|
|
| 9153 |
|
|
|
| 9154 |
|
|
|
| 9155 |
|
|
PAR done!
|
| 9156 |
|
|
|
| 9157 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 9158 |
|
|
|
| 9159 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 9160 |
|
|
C:/Xilinx71.
|
| 9161 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 9162 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 9163 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9164 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9165 |
|
|
ps (24.00 Mhz).
|
| 9166 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 9167 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9168 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9169 |
|
|
(210.04 Mhz).
|
| 9170 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9171 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9172 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9173 |
|
|
ps (24.00 Mhz).
|
| 9174 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9175 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9176 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9177 |
|
|
(210.04 Mhz).
|
| 9178 |
|
|
|
| 9179 |
|
|
Analysis completed Sun Sep 24 14:57:41 2006
|
| 9180 |
|
|
--------------------------------------------------------------------------------
|
| 9181 |
|
|
|
| 9182 |
|
|
Generating Report ...
|
| 9183 |
|
|
|
| 9184 |
|
|
Number of warnings: 4
|
| 9185 |
|
|
Total time: 3 secs
|
| 9186 |
|
|
|
| 9187 |
|
|
|
| 9188 |
|
|
|
| 9189 |
|
|
|
| 9190 |
|
|
|
| 9191 |
|
|
|
| 9192 |
|
|
|
| 9193 |
|
|
Started process "Generate Programming File".
|
| 9194 |
|
|
|
| 9195 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 9196 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 9197 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 9198 |
|
|
Interactive Data Sheet.
|
| 9199 |
|
|
|
| 9200 |
|
|
|
| 9201 |
|
|
Project Navigator Auto-Make Log File
|
| 9202 |
|
|
-------------------------------------
|
| 9203 |
|
|
|
| 9204 |
|
|
|
| 9205 |
|
|
|
| 9206 |
|
|
|
| 9207 |
|
|
Started process "Map".
|
| 9208 |
|
|
|
| 9209 |
|
|
Using target part "3s200ft256-4".
|
| 9210 |
|
|
Mapping design into LUTs...
|
| 9211 |
|
|
Running directed packing...
|
| 9212 |
|
|
Running delay-based LUT packing...
|
| 9213 |
|
|
Running related packing...
|
| 9214 |
|
|
|
| 9215 |
|
|
Design Summary:
|
| 9216 |
|
|
Number of errors: 0
|
| 9217 |
|
|
Number of warnings: 2
|
| 9218 |
|
|
Logic Utilization:
|
| 9219 |
|
|
Number of Slice Flip Flops: 367 out of 3,840 9%
|
| 9220 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 9221 |
|
|
Logic Distribution:
|
| 9222 |
|
|
Number of occupied Slices: 694 out of 1,920 36%
|
| 9223 |
|
|
Number of Slices containing only related logic: 694 out of 694 100%
|
| 9224 |
|
|
Number of Slices containing unrelated logic: 0 out of 694 0%
|
| 9225 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 9226 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 9227 |
|
|
Number used as logic: 1,131
|
| 9228 |
|
|
Number used as a route-thru: 4
|
| 9229 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 9230 |
|
|
IOB Flip Flops: 26
|
| 9231 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 9232 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 9233 |
|
|
|
| 9234 |
|
|
Total equivalent gate count for design: 17,815
|
| 9235 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 9236 |
|
|
Peak Memory Usage: 114 MB
|
| 9237 |
|
|
|
| 9238 |
|
|
NOTES:
|
| 9239 |
|
|
|
| 9240 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 9241 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 9242 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 9243 |
|
|
the best timing performance.
|
| 9244 |
|
|
|
| 9245 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 9246 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 9247 |
|
|
related logic packing.
|
| 9248 |
|
|
|
| 9249 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 9250 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 9251 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 9252 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 9253 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 9254 |
|
|
of your design.
|
| 9255 |
|
|
|
| 9256 |
|
|
Mapping completed.
|
| 9257 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 9258 |
|
|
|
| 9259 |
|
|
|
| 9260 |
|
|
|
| 9261 |
|
|
|
| 9262 |
|
|
Started process "Place & Route".
|
| 9263 |
|
|
|
| 9264 |
|
|
|
| 9265 |
|
|
|
| 9266 |
|
|
|
| 9267 |
|
|
Constraints file: topbox.pcf.
|
| 9268 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 9269 |
|
|
C:/Xilinx71.
|
| 9270 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 9271 |
|
|
|
| 9272 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 9273 |
|
|
Celsius)
|
| 9274 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 9275 |
|
|
|
| 9276 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 9277 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9278 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9279 |
|
|
ps (24.00 Mhz).
|
| 9280 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 9281 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9282 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9283 |
|
|
(210.04 Mhz).
|
| 9284 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9285 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9286 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9287 |
|
|
ps (24.00 Mhz).
|
| 9288 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9289 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9290 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9291 |
|
|
(210.04 Mhz).
|
| 9292 |
|
|
|
| 9293 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 9294 |
|
|
|
| 9295 |
|
|
|
| 9296 |
|
|
Device Utilization Summary:
|
| 9297 |
|
|
|
| 9298 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 9299 |
|
|
Number of DCMs 1 out of 4 25%
|
| 9300 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 9301 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 9302 |
|
|
|
| 9303 |
|
|
Number of Slices 694 out of 1920 36%
|
| 9304 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 9305 |
|
|
|
| 9306 |
|
|
|
| 9307 |
|
|
|
| 9308 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 9309 |
|
|
Placer effort level (-pl): Standard (set by user)
|
| 9310 |
|
|
Placer cost table entry (-t): 1
|
| 9311 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 9312 |
|
|
|
| 9313 |
|
|
Starting initial Timing Analysis. REAL time: 2 secs
|
| 9314 |
|
|
Finished initial Timing Analysis. REAL time: 2 secs
|
| 9315 |
|
|
|
| 9316 |
|
|
|
| 9317 |
|
|
Starting Placer
|
| 9318 |
|
|
|
| 9319 |
|
|
Phase 1.1
|
| 9320 |
|
|
Phase 1.1 (Checksum:98af6c) REAL time: 2 secs
|
| 9321 |
|
|
|
| 9322 |
|
|
Phase 2.31
|
| 9323 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs
|
| 9324 |
|
|
|
| 9325 |
|
|
Phase 3.2
|
| 9326 |
|
|
.
|
| 9327 |
|
|
|
| 9328 |
|
|
|
| 9329 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs
|
| 9330 |
|
|
|
| 9331 |
|
|
Phase 4.8
|
| 9332 |
|
|
................
|
| 9333 |
|
|
.....
|
| 9334 |
|
|
Phase 4.8 (Checksum:a5b7b7) REAL time: 5 secs
|
| 9335 |
|
|
|
| 9336 |
|
|
Phase 5.5
|
| 9337 |
|
|
Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs
|
| 9338 |
|
|
|
| 9339 |
|
|
Phase 6.18
|
| 9340 |
|
|
Phase 6.18 (Checksum:39386fa) REAL time: 7 secs
|
| 9341 |
|
|
|
| 9342 |
|
|
Phase 7.5
|
| 9343 |
|
|
Phase 7.5 (Checksum:42c1d79) REAL time: 7 secs
|
| 9344 |
|
|
|
| 9345 |
|
|
Writing design to file topbox.ncd
|
| 9346 |
|
|
|
| 9347 |
|
|
|
| 9348 |
|
|
Total REAL time to Placer completion: 8 secs
|
| 9349 |
|
|
Total CPU time to Placer completion: 7 secs
|
| 9350 |
|
|
|
| 9351 |
|
|
Starting Router
|
| 9352 |
|
|
|
| 9353 |
|
|
Phase 1: 4717 unrouted; REAL time: 8 secs
|
| 9354 |
|
|
|
| 9355 |
|
|
Phase 2: 4443 unrouted; REAL time: 8 secs
|
| 9356 |
|
|
|
| 9357 |
|
|
Phase 3: 2140 unrouted; REAL time: 8 secs
|
| 9358 |
|
|
|
| 9359 |
|
|
Phase 4: 2140 unrouted; (0) REAL time: 9 secs
|
| 9360 |
|
|
|
| 9361 |
|
|
Phase 5: 2140 unrouted; (0) REAL time: 9 secs
|
| 9362 |
|
|
|
| 9363 |
|
|
Phase 6: 2140 unrouted; (0) REAL time: 9 secs
|
| 9364 |
|
|
|
| 9365 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 11 secs
|
| 9366 |
|
|
|
| 9367 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 11 secs
|
| 9368 |
|
|
|
| 9369 |
|
|
|
| 9370 |
|
|
Total REAL time to Router completion: 11 secs
|
| 9371 |
|
|
Total CPU time to Router completion: 11 secs
|
| 9372 |
|
|
|
| 9373 |
|
|
Generating "PAR" statistics.
|
| 9374 |
|
|
|
| 9375 |
|
|
**************************
|
| 9376 |
|
|
Generating Clock Report
|
| 9377 |
|
|
**************************
|
| 9378 |
|
|
|
| 9379 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9380 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 9381 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9382 |
|
|
| clk | BUFGMUX3| No | 255 | 0.042 | 1.052 |
|
| 9383 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9384 |
|
|
|
| 9385 |
|
|
Timing Score: 0
|
| 9386 |
|
|
|
| 9387 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 9388 |
|
|
This may be due to a setup or hold violation.
|
| 9389 |
|
|
|
| 9390 |
|
|
--------------------------------------------------------------------------------
|
| 9391 |
|
|
Constraint | Requested | Actual | Logic
|
| 9392 |
|
|
| | | Levels
|
| 9393 |
|
|
--------------------------------------------------------------------------------
|
| 9394 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 9395 |
|
|
HIGH 50% | | |
|
| 9396 |
|
|
--------------------------------------------------------------------------------
|
| 9397 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 30.474ns | 7
|
| 9398 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 9399 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 9400 |
|
|
--------------------------------------------------------------------------------
|
| 9401 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 37.488ns | 6
|
| 9402 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 9403 |
|
|
HIGH 50% | | |
|
| 9404 |
|
|
--------------------------------------------------------------------------------
|
| 9405 |
|
|
|
| 9406 |
|
|
|
| 9407 |
|
|
All constraints were met.
|
| 9408 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 9409 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 9410 |
|
|
Generating Pad Report.
|
| 9411 |
|
|
|
| 9412 |
|
|
All signals are completely routed.
|
| 9413 |
|
|
|
| 9414 |
|
|
Total REAL time to PAR completion: 12 secs
|
| 9415 |
|
|
Total CPU time to PAR completion: 12 secs
|
| 9416 |
|
|
|
| 9417 |
|
|
Peak Memory Usage: 96 MB
|
| 9418 |
|
|
|
| 9419 |
|
|
Placement: Completed - No errors found.
|
| 9420 |
|
|
Routing: Completed - No errors found.
|
| 9421 |
|
|
Timing: Completed - No errors found.
|
| 9422 |
|
|
|
| 9423 |
|
|
Number of error messages: 0
|
| 9424 |
|
|
Number of warning messages: 4
|
| 9425 |
|
|
Number of info messages: 0
|
| 9426 |
|
|
|
| 9427 |
|
|
Writing design to file topbox.ncd
|
| 9428 |
|
|
|
| 9429 |
|
|
|
| 9430 |
|
|
|
| 9431 |
|
|
PAR done!
|
| 9432 |
|
|
|
| 9433 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 9434 |
|
|
|
| 9435 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 9436 |
|
|
C:/Xilinx71.
|
| 9437 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 9438 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 9439 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9440 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9441 |
|
|
ps (24.00 Mhz).
|
| 9442 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 9443 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9444 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9445 |
|
|
(210.04 Mhz).
|
| 9446 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9447 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9448 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9449 |
|
|
ps (24.00 Mhz).
|
| 9450 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9451 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9452 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9453 |
|
|
(210.04 Mhz).
|
| 9454 |
|
|
|
| 9455 |
|
|
Analysis completed Sun Sep 24 15:14:45 2006
|
| 9456 |
|
|
--------------------------------------------------------------------------------
|
| 9457 |
|
|
|
| 9458 |
|
|
Generating Report ...
|
| 9459 |
|
|
|
| 9460 |
|
|
Number of warnings: 4
|
| 9461 |
|
|
Total time: 2 secs
|
| 9462 |
|
|
|
| 9463 |
|
|
|
| 9464 |
|
|
|
| 9465 |
|
|
|
| 9466 |
|
|
|
| 9467 |
|
|
|
| 9468 |
|
|
|
| 9469 |
|
|
Started process "Generate Programming File".
|
| 9470 |
|
|
|
| 9471 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 9472 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 9473 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 9474 |
|
|
Interactive Data Sheet.
|
| 9475 |
|
|
|
| 9476 |
|
|
|
| 9477 |
|
|
Project Navigator Auto-Make Log File
|
| 9478 |
|
|
-------------------------------------
|
| 9479 |
|
|
|
| 9480 |
|
|
|
| 9481 |
|
|
|
| 9482 |
|
|
|
| 9483 |
|
|
Started process "Map".
|
| 9484 |
|
|
|
| 9485 |
|
|
Using target part "3s200ft256-4".
|
| 9486 |
|
|
Mapping design into LUTs...
|
| 9487 |
|
|
Running directed packing...
|
| 9488 |
|
|
Running delay-based LUT packing...
|
| 9489 |
|
|
Running related packing...
|
| 9490 |
|
|
|
| 9491 |
|
|
Design Summary:
|
| 9492 |
|
|
Number of errors: 0
|
| 9493 |
|
|
Number of warnings: 2
|
| 9494 |
|
|
Logic Utilization:
|
| 9495 |
|
|
Number of Slice Flip Flops: 364 out of 3,840 9%
|
| 9496 |
|
|
Number of 4 input LUTs: 1,119 out of 3,840 29%
|
| 9497 |
|
|
Logic Distribution:
|
| 9498 |
|
|
Number of occupied Slices: 687 out of 1,920 35%
|
| 9499 |
|
|
Number of Slices containing only related logic: 687 out of 687 100%
|
| 9500 |
|
|
Number of Slices containing unrelated logic: 0 out of 687 0%
|
| 9501 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 9502 |
|
|
Total Number 4 input LUTs: 1,123 out of 3,840 29%
|
| 9503 |
|
|
Number used as logic: 1,119
|
| 9504 |
|
|
Number used as a route-thru: 4
|
| 9505 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 9506 |
|
|
IOB Flip Flops: 26
|
| 9507 |
|
|
Number of Block RAMs: 3 out of 12 25%
|
| 9508 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 9509 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 9510 |
|
|
|
| 9511 |
|
|
Total equivalent gate count for design: 214,327
|
| 9512 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 9513 |
|
|
Peak Memory Usage: 114 MB
|
| 9514 |
|
|
|
| 9515 |
|
|
NOTES:
|
| 9516 |
|
|
|
| 9517 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 9518 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 9519 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 9520 |
|
|
the best timing performance.
|
| 9521 |
|
|
|
| 9522 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 9523 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 9524 |
|
|
related logic packing.
|
| 9525 |
|
|
|
| 9526 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 9527 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 9528 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 9529 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 9530 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 9531 |
|
|
of your design.
|
| 9532 |
|
|
|
| 9533 |
|
|
Mapping completed.
|
| 9534 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 9535 |
|
|
|
| 9536 |
|
|
|
| 9537 |
|
|
|
| 9538 |
|
|
|
| 9539 |
|
|
Started process "Place & Route".
|
| 9540 |
|
|
|
| 9541 |
|
|
|
| 9542 |
|
|
|
| 9543 |
|
|
|
| 9544 |
|
|
Constraints file: topbox.pcf.
|
| 9545 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 9546 |
|
|
C:/Xilinx71.
|
| 9547 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 9548 |
|
|
|
| 9549 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 9550 |
|
|
Celsius)
|
| 9551 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 9552 |
|
|
|
| 9553 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 9554 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9555 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9556 |
|
|
ps (24.00 Mhz).
|
| 9557 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 9558 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9559 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9560 |
|
|
(210.04 Mhz).
|
| 9561 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9562 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9563 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9564 |
|
|
ps (24.00 Mhz).
|
| 9565 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9566 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9567 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9568 |
|
|
(210.04 Mhz).
|
| 9569 |
|
|
|
| 9570 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 9571 |
|
|
|
| 9572 |
|
|
|
| 9573 |
|
|
Device Utilization Summary:
|
| 9574 |
|
|
|
| 9575 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 9576 |
|
|
Number of DCMs 1 out of 4 25%
|
| 9577 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 9578 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 9579 |
|
|
|
| 9580 |
|
|
Number of RAMB16s 3 out of 12 25%
|
| 9581 |
|
|
Number of Slices 687 out of 1920 35%
|
| 9582 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 9583 |
|
|
|
| 9584 |
|
|
|
| 9585 |
|
|
|
| 9586 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 9587 |
|
|
Placer effort level (-pl): Standard (set by user)
|
| 9588 |
|
|
Placer cost table entry (-t): 1
|
| 9589 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 9590 |
|
|
|
| 9591 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 9592 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 9593 |
|
|
|
| 9594 |
|
|
|
| 9595 |
|
|
Starting Placer
|
| 9596 |
|
|
|
| 9597 |
|
|
Phase 1.1
|
| 9598 |
|
|
Phase 1.1 (Checksum:98b209) REAL time: 6 secs
|
| 9599 |
|
|
|
| 9600 |
|
|
Phase 2.31
|
| 9601 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 6 secs
|
| 9602 |
|
|
|
| 9603 |
|
|
Phase 3.2
|
| 9604 |
|
|
.
|
| 9605 |
|
|
|
| 9606 |
|
|
|
| 9607 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 8 secs
|
| 9608 |
|
|
|
| 9609 |
|
|
Phase 4.8
|
| 9610 |
|
|
........................................
|
| 9611 |
|
|
....
|
| 9612 |
|
|
Phase 4.8 (Checksum:a51b43) REAL time: 10 secs
|
| 9613 |
|
|
|
| 9614 |
|
|
Phase 5.5
|
| 9615 |
|
|
Phase 5.5 (Checksum:2faf07b) REAL time: 10 secs
|
| 9616 |
|
|
|
| 9617 |
|
|
Phase 6.18
|
| 9618 |
|
|
Phase 6.18 (Checksum:39386fa) REAL time: 12 secs
|
| 9619 |
|
|
|
| 9620 |
|
|
Phase 7.5
|
| 9621 |
|
|
Phase 7.5 (Checksum:42c1d79) REAL time: 12 secs
|
| 9622 |
|
|
|
| 9623 |
|
|
Writing design to file topbox.ncd
|
| 9624 |
|
|
|
| 9625 |
|
|
|
| 9626 |
|
|
Total REAL time to Placer completion: 12 secs
|
| 9627 |
|
|
Total CPU time to Placer completion: 8 secs
|
| 9628 |
|
|
|
| 9629 |
|
|
Starting Router
|
| 9630 |
|
|
|
| 9631 |
|
|
Phase 1: 4722 unrouted; REAL time: 12 secs
|
| 9632 |
|
|
|
| 9633 |
|
|
Phase 2: 4441 unrouted; REAL time: 13 secs
|
| 9634 |
|
|
|
| 9635 |
|
|
Phase 3: 2115 unrouted; REAL time: 13 secs
|
| 9636 |
|
|
|
| 9637 |
|
|
Phase 4: 2115 unrouted; (0) REAL time: 14 secs
|
| 9638 |
|
|
|
| 9639 |
|
|
Phase 5: 2115 unrouted; (0) REAL time: 14 secs
|
| 9640 |
|
|
|
| 9641 |
|
|
Phase 6: 2115 unrouted; (0) REAL time: 14 secs
|
| 9642 |
|
|
|
| 9643 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 16 secs
|
| 9644 |
|
|
|
| 9645 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 16 secs
|
| 9646 |
|
|
|
| 9647 |
|
|
|
| 9648 |
|
|
Total REAL time to Router completion: 17 secs
|
| 9649 |
|
|
Total CPU time to Router completion: 12 secs
|
| 9650 |
|
|
|
| 9651 |
|
|
Generating "PAR" statistics.
|
| 9652 |
|
|
|
| 9653 |
|
|
**************************
|
| 9654 |
|
|
Generating Clock Report
|
| 9655 |
|
|
**************************
|
| 9656 |
|
|
|
| 9657 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9658 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 9659 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9660 |
|
|
| clk | BUFGMUX3| No | 255 | 0.041 | 1.051 |
|
| 9661 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9662 |
|
|
|
| 9663 |
|
|
Timing Score: 0
|
| 9664 |
|
|
|
| 9665 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 9666 |
|
|
This may be due to a setup or hold violation.
|
| 9667 |
|
|
|
| 9668 |
|
|
--------------------------------------------------------------------------------
|
| 9669 |
|
|
Constraint | Requested | Actual | Logic
|
| 9670 |
|
|
| | | Levels
|
| 9671 |
|
|
--------------------------------------------------------------------------------
|
| 9672 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 9673 |
|
|
HIGH 50% | | |
|
| 9674 |
|
|
--------------------------------------------------------------------------------
|
| 9675 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 30.026ns | 8
|
| 9676 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 9677 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 9678 |
|
|
--------------------------------------------------------------------------------
|
| 9679 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 38.558ns | 8
|
| 9680 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 9681 |
|
|
HIGH 50% | | |
|
| 9682 |
|
|
--------------------------------------------------------------------------------
|
| 9683 |
|
|
|
| 9684 |
|
|
|
| 9685 |
|
|
All constraints were met.
|
| 9686 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 9687 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 9688 |
|
|
Generating Pad Report.
|
| 9689 |
|
|
|
| 9690 |
|
|
All signals are completely routed.
|
| 9691 |
|
|
|
| 9692 |
|
|
Total REAL time to PAR completion: 18 secs
|
| 9693 |
|
|
Total CPU time to PAR completion: 13 secs
|
| 9694 |
|
|
|
| 9695 |
|
|
Peak Memory Usage: 96 MB
|
| 9696 |
|
|
|
| 9697 |
|
|
Placement: Completed - No errors found.
|
| 9698 |
|
|
Routing: Completed - No errors found.
|
| 9699 |
|
|
Timing: Completed - No errors found.
|
| 9700 |
|
|
|
| 9701 |
|
|
Number of error messages: 0
|
| 9702 |
|
|
Number of warning messages: 4
|
| 9703 |
|
|
Number of info messages: 0
|
| 9704 |
|
|
|
| 9705 |
|
|
Writing design to file topbox.ncd
|
| 9706 |
|
|
|
| 9707 |
|
|
|
| 9708 |
|
|
|
| 9709 |
|
|
PAR done!
|
| 9710 |
|
|
|
| 9711 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 9712 |
|
|
|
| 9713 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 9714 |
|
|
C:/Xilinx71.
|
| 9715 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 9716 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 9717 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9718 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9719 |
|
|
ps (24.00 Mhz).
|
| 9720 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 9721 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9722 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9723 |
|
|
(210.04 Mhz).
|
| 9724 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9725 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9726 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9727 |
|
|
ps (24.00 Mhz).
|
| 9728 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9729 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9730 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9731 |
|
|
(210.04 Mhz).
|
| 9732 |
|
|
|
| 9733 |
|
|
Analysis completed Sun Sep 24 17:16:18 2006
|
| 9734 |
|
|
--------------------------------------------------------------------------------
|
| 9735 |
|
|
|
| 9736 |
|
|
Generating Report ...
|
| 9737 |
|
|
|
| 9738 |
|
|
Number of warnings: 4
|
| 9739 |
|
|
Total time: 3 secs
|
| 9740 |
|
|
|
| 9741 |
|
|
|
| 9742 |
|
|
|
| 9743 |
|
|
|
| 9744 |
|
|
|
| 9745 |
|
|
|
| 9746 |
|
|
|
| 9747 |
|
|
Started process "Generate Programming File".
|
| 9748 |
|
|
|
| 9749 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 9750 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 9751 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 9752 |
|
|
Interactive Data Sheet.
|
| 9753 |
|
|
|
| 9754 |
|
|
|
| 9755 |
|
|
Project Navigator Auto-Make Log File
|
| 9756 |
|
|
-------------------------------------
|
| 9757 |
|
|
|
| 9758 |
|
|
|
| 9759 |
|
|
|
| 9760 |
|
|
|
| 9761 |
|
|
Started process "Map".
|
| 9762 |
|
|
|
| 9763 |
|
|
Using target part "3s200ft256-4".
|
| 9764 |
|
|
Mapping design into LUTs...
|
| 9765 |
|
|
Running directed packing...
|
| 9766 |
|
|
Running delay-based LUT packing...
|
| 9767 |
|
|
Running related packing...
|
| 9768 |
|
|
|
| 9769 |
|
|
Design Summary:
|
| 9770 |
|
|
Number of errors: 0
|
| 9771 |
|
|
Number of warnings: 2
|
| 9772 |
|
|
Logic Utilization:
|
| 9773 |
|
|
Number of Slice Flip Flops: 367 out of 3,840 9%
|
| 9774 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 9775 |
|
|
Logic Distribution:
|
| 9776 |
|
|
Number of occupied Slices: 694 out of 1,920 36%
|
| 9777 |
|
|
Number of Slices containing only related logic: 694 out of 694 100%
|
| 9778 |
|
|
Number of Slices containing unrelated logic: 0 out of 694 0%
|
| 9779 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 9780 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 9781 |
|
|
Number used as logic: 1,131
|
| 9782 |
|
|
Number used as a route-thru: 4
|
| 9783 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 9784 |
|
|
IOB Flip Flops: 26
|
| 9785 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 9786 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 9787 |
|
|
|
| 9788 |
|
|
Total equivalent gate count for design: 17,815
|
| 9789 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 9790 |
|
|
Peak Memory Usage: 114 MB
|
| 9791 |
|
|
|
| 9792 |
|
|
NOTES:
|
| 9793 |
|
|
|
| 9794 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 9795 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 9796 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 9797 |
|
|
the best timing performance.
|
| 9798 |
|
|
|
| 9799 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 9800 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 9801 |
|
|
related logic packing.
|
| 9802 |
|
|
|
| 9803 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 9804 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 9805 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 9806 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 9807 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 9808 |
|
|
of your design.
|
| 9809 |
|
|
|
| 9810 |
|
|
Mapping completed.
|
| 9811 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 9812 |
|
|
|
| 9813 |
|
|
|
| 9814 |
|
|
|
| 9815 |
|
|
|
| 9816 |
|
|
Started process "Place & Route".
|
| 9817 |
|
|
|
| 9818 |
|
|
|
| 9819 |
|
|
|
| 9820 |
|
|
|
| 9821 |
|
|
Constraints file: topbox.pcf.
|
| 9822 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 9823 |
|
|
C:/Xilinx71.
|
| 9824 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 9825 |
|
|
|
| 9826 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 9827 |
|
|
Celsius)
|
| 9828 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 9829 |
|
|
|
| 9830 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 9831 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9832 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9833 |
|
|
ps (24.00 Mhz).
|
| 9834 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 9835 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9836 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9837 |
|
|
(210.04 Mhz).
|
| 9838 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9839 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9840 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9841 |
|
|
ps (24.00 Mhz).
|
| 9842 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 9843 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9844 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9845 |
|
|
(210.04 Mhz).
|
| 9846 |
|
|
|
| 9847 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 9848 |
|
|
|
| 9849 |
|
|
|
| 9850 |
|
|
Device Utilization Summary:
|
| 9851 |
|
|
|
| 9852 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 9853 |
|
|
Number of DCMs 1 out of 4 25%
|
| 9854 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 9855 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 9856 |
|
|
|
| 9857 |
|
|
Number of Slices 694 out of 1920 36%
|
| 9858 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 9859 |
|
|
|
| 9860 |
|
|
|
| 9861 |
|
|
|
| 9862 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 9863 |
|
|
Placer effort level (-pl): Standard (set by user)
|
| 9864 |
|
|
Placer cost table entry (-t): 1
|
| 9865 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 9866 |
|
|
|
| 9867 |
|
|
Starting initial Timing Analysis. REAL time: 2 secs
|
| 9868 |
|
|
Finished initial Timing Analysis. REAL time: 2 secs
|
| 9869 |
|
|
|
| 9870 |
|
|
|
| 9871 |
|
|
Starting Placer
|
| 9872 |
|
|
|
| 9873 |
|
|
Phase 1.1
|
| 9874 |
|
|
Phase 1.1 (Checksum:98af6c) REAL time: 2 secs
|
| 9875 |
|
|
|
| 9876 |
|
|
Phase 2.31
|
| 9877 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs
|
| 9878 |
|
|
|
| 9879 |
|
|
Phase 3.2
|
| 9880 |
|
|
.
|
| 9881 |
|
|
|
| 9882 |
|
|
|
| 9883 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs
|
| 9884 |
|
|
|
| 9885 |
|
|
Phase 4.8
|
| 9886 |
|
|
................
|
| 9887 |
|
|
.....
|
| 9888 |
|
|
Phase 4.8 (Checksum:a5b7b7) REAL time: 5 secs
|
| 9889 |
|
|
|
| 9890 |
|
|
Phase 5.5
|
| 9891 |
|
|
Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs
|
| 9892 |
|
|
|
| 9893 |
|
|
Phase 6.18
|
| 9894 |
|
|
Phase 6.18 (Checksum:39386fa) REAL time: 7 secs
|
| 9895 |
|
|
|
| 9896 |
|
|
Phase 7.5
|
| 9897 |
|
|
Phase 7.5 (Checksum:42c1d79) REAL time: 7 secs
|
| 9898 |
|
|
|
| 9899 |
|
|
Writing design to file topbox.ncd
|
| 9900 |
|
|
|
| 9901 |
|
|
|
| 9902 |
|
|
Total REAL time to Placer completion: 7 secs
|
| 9903 |
|
|
Total CPU time to Placer completion: 7 secs
|
| 9904 |
|
|
|
| 9905 |
|
|
Starting Router
|
| 9906 |
|
|
|
| 9907 |
|
|
Phase 1: 4717 unrouted; REAL time: 7 secs
|
| 9908 |
|
|
|
| 9909 |
|
|
Phase 2: 4443 unrouted; REAL time: 7 secs
|
| 9910 |
|
|
|
| 9911 |
|
|
Phase 3: 2140 unrouted; REAL time: 8 secs
|
| 9912 |
|
|
|
| 9913 |
|
|
Phase 4: 2140 unrouted; (0) REAL time: 8 secs
|
| 9914 |
|
|
|
| 9915 |
|
|
Phase 5: 2140 unrouted; (0) REAL time: 8 secs
|
| 9916 |
|
|
|
| 9917 |
|
|
Phase 6: 2140 unrouted; (0) REAL time: 9 secs
|
| 9918 |
|
|
|
| 9919 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 10 secs
|
| 9920 |
|
|
|
| 9921 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 11 secs
|
| 9922 |
|
|
|
| 9923 |
|
|
|
| 9924 |
|
|
Total REAL time to Router completion: 11 secs
|
| 9925 |
|
|
Total CPU time to Router completion: 11 secs
|
| 9926 |
|
|
|
| 9927 |
|
|
Generating "PAR" statistics.
|
| 9928 |
|
|
|
| 9929 |
|
|
**************************
|
| 9930 |
|
|
Generating Clock Report
|
| 9931 |
|
|
**************************
|
| 9932 |
|
|
|
| 9933 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9934 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 9935 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9936 |
|
|
| clk | BUFGMUX3| No | 255 | 0.042 | 1.052 |
|
| 9937 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 9938 |
|
|
|
| 9939 |
|
|
Timing Score: 0
|
| 9940 |
|
|
|
| 9941 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 9942 |
|
|
This may be due to a setup or hold violation.
|
| 9943 |
|
|
|
| 9944 |
|
|
--------------------------------------------------------------------------------
|
| 9945 |
|
|
Constraint | Requested | Actual | Logic
|
| 9946 |
|
|
| | | Levels
|
| 9947 |
|
|
--------------------------------------------------------------------------------
|
| 9948 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 9949 |
|
|
HIGH 50% | | |
|
| 9950 |
|
|
--------------------------------------------------------------------------------
|
| 9951 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 30.474ns | 7
|
| 9952 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 9953 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 9954 |
|
|
--------------------------------------------------------------------------------
|
| 9955 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 37.488ns | 6
|
| 9956 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 9957 |
|
|
HIGH 50% | | |
|
| 9958 |
|
|
--------------------------------------------------------------------------------
|
| 9959 |
|
|
|
| 9960 |
|
|
|
| 9961 |
|
|
All constraints were met.
|
| 9962 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 9963 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 9964 |
|
|
Generating Pad Report.
|
| 9965 |
|
|
|
| 9966 |
|
|
All signals are completely routed.
|
| 9967 |
|
|
|
| 9968 |
|
|
Total REAL time to PAR completion: 12 secs
|
| 9969 |
|
|
Total CPU time to PAR completion: 12 secs
|
| 9970 |
|
|
|
| 9971 |
|
|
Peak Memory Usage: 96 MB
|
| 9972 |
|
|
|
| 9973 |
|
|
Placement: Completed - No errors found.
|
| 9974 |
|
|
Routing: Completed - No errors found.
|
| 9975 |
|
|
Timing: Completed - No errors found.
|
| 9976 |
|
|
|
| 9977 |
|
|
Number of error messages: 0
|
| 9978 |
|
|
Number of warning messages: 4
|
| 9979 |
|
|
Number of info messages: 0
|
| 9980 |
|
|
|
| 9981 |
|
|
Writing design to file topbox.ncd
|
| 9982 |
|
|
|
| 9983 |
|
|
|
| 9984 |
|
|
|
| 9985 |
|
|
PAR done!
|
| 9986 |
|
|
|
| 9987 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 9988 |
|
|
|
| 9989 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 9990 |
|
|
C:/Xilinx71.
|
| 9991 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 9992 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 9993 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9994 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 9995 |
|
|
ps (24.00 Mhz).
|
| 9996 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 9997 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 9998 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 9999 |
|
|
(210.04 Mhz).
|
| 10000 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10001 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10002 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 10003 |
|
|
ps (24.00 Mhz).
|
| 10004 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10005 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10006 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 10007 |
|
|
(210.04 Mhz).
|
| 10008 |
|
|
|
| 10009 |
|
|
Analysis completed Sun Sep 24 17:28:05 2006
|
| 10010 |
|
|
--------------------------------------------------------------------------------
|
| 10011 |
|
|
|
| 10012 |
|
|
Generating Report ...
|
| 10013 |
|
|
|
| 10014 |
|
|
Number of warnings: 4
|
| 10015 |
|
|
Total time: 2 secs
|
| 10016 |
|
|
|
| 10017 |
|
|
|
| 10018 |
|
|
|
| 10019 |
|
|
|
| 10020 |
|
|
|
| 10021 |
|
|
|
| 10022 |
|
|
|
| 10023 |
|
|
Started process "Generate Programming File".
|
| 10024 |
|
|
|
| 10025 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 10026 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 10027 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 10028 |
|
|
Interactive Data Sheet.
|
| 10029 |
|
|
|
| 10030 |
|
|
|
| 10031 |
|
|
Project Navigator Auto-Make Log File
|
| 10032 |
|
|
-------------------------------------
|
| 10033 |
|
|
|
| 10034 |
|
|
|
| 10035 |
|
|
|
| 10036 |
|
|
|
| 10037 |
|
|
Started process "Map".
|
| 10038 |
|
|
|
| 10039 |
|
|
Using target part "3s200ft256-4".
|
| 10040 |
|
|
Mapping design into LUTs...
|
| 10041 |
|
|
Running directed packing...
|
| 10042 |
|
|
Running delay-based LUT packing...
|
| 10043 |
|
|
Running timing-driven packing...
|
| 10044 |
|
|
|
| 10045 |
|
|
Phase 1.1
|
| 10046 |
|
|
Phase 1.1 (Checksum:98d16f) REAL time: 0 secs
|
| 10047 |
|
|
|
| 10048 |
|
|
Phase 2.31
|
| 10049 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs
|
| 10050 |
|
|
|
| 10051 |
|
|
Phase 3.2
|
| 10052 |
|
|
.
|
| 10053 |
|
|
|
| 10054 |
|
|
|
| 10055 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs
|
| 10056 |
|
|
|
| 10057 |
|
|
Phase 4.4
|
| 10058 |
|
|
..............
|
| 10059 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs
|
| 10060 |
|
|
|
| 10061 |
|
|
Phase 5.28
|
| 10062 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs
|
| 10063 |
|
|
|
| 10064 |
|
|
Phase 6.8
|
| 10065 |
|
|
.....................
|
| 10066 |
|
|
........
|
| 10067 |
|
|
.........................
|
| 10068 |
|
|
...............
|
| 10069 |
|
|
...............
|
| 10070 |
|
|
Phase 6.8 (Checksum:aa8209) REAL time: 9 secs
|
| 10071 |
|
|
|
| 10072 |
|
|
Phase 7.29
|
| 10073 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 9 secs
|
| 10074 |
|
|
|
| 10075 |
|
|
Phase 8.5
|
| 10076 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 9 secs
|
| 10077 |
|
|
|
| 10078 |
|
|
Phase 9.18
|
| 10079 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 18 secs
|
| 10080 |
|
|
|
| 10081 |
|
|
Phase 10.5
|
| 10082 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 18 secs
|
| 10083 |
|
|
|
| 10084 |
|
|
|
| 10085 |
|
|
Design Summary:
|
| 10086 |
|
|
Number of errors: 0
|
| 10087 |
|
|
Number of warnings: 11
|
| 10088 |
|
|
Logic Utilization:
|
| 10089 |
|
|
Number of Slice Flip Flops: 367 out of 3,840 9%
|
| 10090 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 10091 |
|
|
Logic Distribution:
|
| 10092 |
|
|
Number of occupied Slices: 691 out of 1,920 35%
|
| 10093 |
|
|
Number of Slices containing only related logic: 691 out of 691 100%
|
| 10094 |
|
|
Number of Slices containing unrelated logic: 0 out of 691 0%
|
| 10095 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 10096 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 10097 |
|
|
Number used as logic: 1,131
|
| 10098 |
|
|
Number used as a route-thru: 4
|
| 10099 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 10100 |
|
|
IOB Flip Flops: 26
|
| 10101 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 10102 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 10103 |
|
|
|
| 10104 |
|
|
Total equivalent gate count for design: 17,815
|
| 10105 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 10106 |
|
|
Peak Memory Usage: 133 MB
|
| 10107 |
|
|
|
| 10108 |
|
|
Mapping completed.
|
| 10109 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 10110 |
|
|
|
| 10111 |
|
|
|
| 10112 |
|
|
|
| 10113 |
|
|
|
| 10114 |
|
|
Started process "Place & Route".
|
| 10115 |
|
|
|
| 10116 |
|
|
|
| 10117 |
|
|
|
| 10118 |
|
|
|
| 10119 |
|
|
Constraints file: topbox.pcf.
|
| 10120 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 10121 |
|
|
C:/Xilinx71.
|
| 10122 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 10123 |
|
|
|
| 10124 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 10125 |
|
|
Celsius)
|
| 10126 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 10127 |
|
|
|
| 10128 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 10129 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10130 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 10131 |
|
|
ps (24.00 Mhz).
|
| 10132 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 10133 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10134 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 10135 |
|
|
(210.04 Mhz).
|
| 10136 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10137 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10138 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 10139 |
|
|
ps (24.00 Mhz).
|
| 10140 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10141 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10142 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 10143 |
|
|
(210.04 Mhz).
|
| 10144 |
|
|
|
| 10145 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 10146 |
|
|
|
| 10147 |
|
|
|
| 10148 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 10149 |
|
|
achieve better performance.
|
| 10150 |
|
|
|
| 10151 |
|
|
Device Utilization Summary:
|
| 10152 |
|
|
|
| 10153 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 10154 |
|
|
Number of DCMs 1 out of 4 25%
|
| 10155 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 10156 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 10157 |
|
|
|
| 10158 |
|
|
Number of Slices 691 out of 1920 35%
|
| 10159 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 10160 |
|
|
|
| 10161 |
|
|
|
| 10162 |
|
|
|
| 10163 |
|
|
Overall effort level (-ol): Standard (set by user)
|
| 10164 |
|
|
Router effort level (-rl): Standard (set by user)
|
| 10165 |
|
|
|
| 10166 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 10167 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 10168 |
|
|
|
| 10169 |
|
|
Starting Router
|
| 10170 |
|
|
|
| 10171 |
|
|
Phase 1: 4863 unrouted; REAL time: 4 secs
|
| 10172 |
|
|
|
| 10173 |
|
|
Phase 2: 4537 unrouted; REAL time: 4 secs
|
| 10174 |
|
|
|
| 10175 |
|
|
Phase 3: 2179 unrouted; REAL time: 5 secs
|
| 10176 |
|
|
|
| 10177 |
|
|
Phase 4: 2179 unrouted; (0) REAL time: 5 secs
|
| 10178 |
|
|
|
| 10179 |
|
|
Phase 5: 2179 unrouted; (0) REAL time: 5 secs
|
| 10180 |
|
|
|
| 10181 |
|
|
Phase 6: 2179 unrouted; (0) REAL time: 5 secs
|
| 10182 |
|
|
|
| 10183 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 8 secs
|
| 10184 |
|
|
|
| 10185 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 8 secs
|
| 10186 |
|
|
|
| 10187 |
|
|
|
| 10188 |
|
|
Total REAL time to Router completion: 9 secs
|
| 10189 |
|
|
Total CPU time to Router completion: 9 secs
|
| 10190 |
|
|
|
| 10191 |
|
|
Generating "PAR" statistics.
|
| 10192 |
|
|
|
| 10193 |
|
|
**************************
|
| 10194 |
|
|
Generating Clock Report
|
| 10195 |
|
|
**************************
|
| 10196 |
|
|
|
| 10197 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 10198 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 10199 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 10200 |
|
|
| clk | BUFGMUX2| No | 307 | 0.041 | 1.051 |
|
| 10201 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 10202 |
|
|
|
| 10203 |
|
|
Timing Score: 0
|
| 10204 |
|
|
|
| 10205 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 10206 |
|
|
This may be due to a setup or hold violation.
|
| 10207 |
|
|
|
| 10208 |
|
|
--------------------------------------------------------------------------------
|
| 10209 |
|
|
Constraint | Requested | Actual | Logic
|
| 10210 |
|
|
| | | Levels
|
| 10211 |
|
|
--------------------------------------------------------------------------------
|
| 10212 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 10213 |
|
|
HIGH 50% | | |
|
| 10214 |
|
|
--------------------------------------------------------------------------------
|
| 10215 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 36.056ns | 8
|
| 10216 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 10217 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 10218 |
|
|
--------------------------------------------------------------------------------
|
| 10219 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 39.230ns | 12
|
| 10220 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 10221 |
|
|
HIGH 50% | | |
|
| 10222 |
|
|
--------------------------------------------------------------------------------
|
| 10223 |
|
|
|
| 10224 |
|
|
|
| 10225 |
|
|
All constraints were met.
|
| 10226 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 10227 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 10228 |
|
|
Generating Pad Report.
|
| 10229 |
|
|
|
| 10230 |
|
|
All signals are completely routed.
|
| 10231 |
|
|
|
| 10232 |
|
|
Total REAL time to PAR completion: 10 secs
|
| 10233 |
|
|
Total CPU time to PAR completion: 10 secs
|
| 10234 |
|
|
|
| 10235 |
|
|
Peak Memory Usage: 93 MB
|
| 10236 |
|
|
|
| 10237 |
|
|
Placer: Not run.
|
| 10238 |
|
|
Routing: Completed - No errors found.
|
| 10239 |
|
|
Timing: Completed - No errors found.
|
| 10240 |
|
|
|
| 10241 |
|
|
Number of error messages: 0
|
| 10242 |
|
|
Number of warning messages: 4
|
| 10243 |
|
|
Number of info messages: 1
|
| 10244 |
|
|
|
| 10245 |
|
|
Writing design to file topbox.ncd
|
| 10246 |
|
|
|
| 10247 |
|
|
|
| 10248 |
|
|
|
| 10249 |
|
|
PAR done!
|
| 10250 |
|
|
|
| 10251 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 10252 |
|
|
|
| 10253 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 10254 |
|
|
C:/Xilinx71.
|
| 10255 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 10256 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 10257 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10258 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 10259 |
|
|
ps (24.00 Mhz).
|
| 10260 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 10261 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10262 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 10263 |
|
|
(210.04 Mhz).
|
| 10264 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10265 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10266 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 10267 |
|
|
ps (24.00 Mhz).
|
| 10268 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10269 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10270 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 10271 |
|
|
(210.04 Mhz).
|
| 10272 |
|
|
|
| 10273 |
|
|
Analysis completed Sun Sep 24 17:30:24 2006
|
| 10274 |
|
|
--------------------------------------------------------------------------------
|
| 10275 |
|
|
|
| 10276 |
|
|
Generating Report ...
|
| 10277 |
|
|
|
| 10278 |
|
|
Number of warnings: 4
|
| 10279 |
|
|
Total time: 2 secs
|
| 10280 |
|
|
|
| 10281 |
|
|
|
| 10282 |
|
|
|
| 10283 |
|
|
|
| 10284 |
|
|
|
| 10285 |
|
|
|
| 10286 |
|
|
|
| 10287 |
|
|
Started process "Generate Programming File".
|
| 10288 |
|
|
|
| 10289 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 10290 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 10291 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 10292 |
|
|
Interactive Data Sheet.
|
| 10293 |
|
|
|
| 10294 |
|
|
|
| 10295 |
|
|
Project Navigator Auto-Make Log File
|
| 10296 |
|
|
-------------------------------------
|
| 10297 |
|
|
|
| 10298 |
|
|
|
| 10299 |
|
|
|
| 10300 |
|
|
|
| 10301 |
|
|
Started process "Place & Route".
|
| 10302 |
|
|
|
| 10303 |
|
|
|
| 10304 |
|
|
|
| 10305 |
|
|
|
| 10306 |
|
|
Constraints file: topbox.pcf.
|
| 10307 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 10308 |
|
|
C:/Xilinx71.
|
| 10309 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 10310 |
|
|
|
| 10311 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 10312 |
|
|
Celsius)
|
| 10313 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 10314 |
|
|
|
| 10315 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 10316 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10317 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 10318 |
|
|
ps (24.00 Mhz).
|
| 10319 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 10320 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10321 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 10322 |
|
|
(210.04 Mhz).
|
| 10323 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10324 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10325 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 10326 |
|
|
ps (24.00 Mhz).
|
| 10327 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10328 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10329 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 10330 |
|
|
(210.04 Mhz).
|
| 10331 |
|
|
|
| 10332 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 10333 |
|
|
|
| 10334 |
|
|
|
| 10335 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 10336 |
|
|
achieve better performance.
|
| 10337 |
|
|
|
| 10338 |
|
|
Device Utilization Summary:
|
| 10339 |
|
|
|
| 10340 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 10341 |
|
|
Number of DCMs 1 out of 4 25%
|
| 10342 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 10343 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 10344 |
|
|
|
| 10345 |
|
|
Number of Slices 691 out of 1920 35%
|
| 10346 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 10347 |
|
|
|
| 10348 |
|
|
|
| 10349 |
|
|
|
| 10350 |
|
|
Overall effort level (-ol): High (set by user)
|
| 10351 |
|
|
Router effort level (-rl): High (set by user)
|
| 10352 |
|
|
|
| 10353 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 10354 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 10355 |
|
|
|
| 10356 |
|
|
Starting Router
|
| 10357 |
|
|
|
| 10358 |
|
|
Phase 1: 4863 unrouted; REAL time: 4 secs
|
| 10359 |
|
|
|
| 10360 |
|
|
Phase 2: 4537 unrouted; REAL time: 4 secs
|
| 10361 |
|
|
|
| 10362 |
|
|
Phase 3: 2179 unrouted; REAL time: 5 secs
|
| 10363 |
|
|
|
| 10364 |
|
|
Phase 4: 2179 unrouted; (0) REAL time: 5 secs
|
| 10365 |
|
|
|
| 10366 |
|
|
Phase 5: 2179 unrouted; (0) REAL time: 5 secs
|
| 10367 |
|
|
|
| 10368 |
|
|
Phase 6: 2179 unrouted; (0) REAL time: 5 secs
|
| 10369 |
|
|
|
| 10370 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 8 secs
|
| 10371 |
|
|
|
| 10372 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 9 secs
|
| 10373 |
|
|
|
| 10374 |
|
|
|
| 10375 |
|
|
Total REAL time to Router completion: 9 secs
|
| 10376 |
|
|
Total CPU time to Router completion: 9 secs
|
| 10377 |
|
|
|
| 10378 |
|
|
Generating "PAR" statistics.
|
| 10379 |
|
|
|
| 10380 |
|
|
**************************
|
| 10381 |
|
|
Generating Clock Report
|
| 10382 |
|
|
**************************
|
| 10383 |
|
|
|
| 10384 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 10385 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 10386 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 10387 |
|
|
| clk | BUFGMUX2| No | 307 | 0.041 | 1.051 |
|
| 10388 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 10389 |
|
|
|
| 10390 |
|
|
Timing Score: 0
|
| 10391 |
|
|
|
| 10392 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 10393 |
|
|
This may be due to a setup or hold violation.
|
| 10394 |
|
|
|
| 10395 |
|
|
--------------------------------------------------------------------------------
|
| 10396 |
|
|
Constraint | Requested | Actual | Logic
|
| 10397 |
|
|
| | | Levels
|
| 10398 |
|
|
--------------------------------------------------------------------------------
|
| 10399 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 10400 |
|
|
HIGH 50% | | |
|
| 10401 |
|
|
--------------------------------------------------------------------------------
|
| 10402 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 36.056ns | 8
|
| 10403 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 10404 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 10405 |
|
|
--------------------------------------------------------------------------------
|
| 10406 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 39.230ns | 12
|
| 10407 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 10408 |
|
|
HIGH 50% | | |
|
| 10409 |
|
|
--------------------------------------------------------------------------------
|
| 10410 |
|
|
|
| 10411 |
|
|
|
| 10412 |
|
|
All constraints were met.
|
| 10413 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 10414 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 10415 |
|
|
Generating Pad Report.
|
| 10416 |
|
|
|
| 10417 |
|
|
All signals are completely routed.
|
| 10418 |
|
|
|
| 10419 |
|
|
Total REAL time to PAR completion: 10 secs
|
| 10420 |
|
|
Total CPU time to PAR completion: 10 secs
|
| 10421 |
|
|
|
| 10422 |
|
|
Peak Memory Usage: 93 MB
|
| 10423 |
|
|
|
| 10424 |
|
|
Placer: Not run.
|
| 10425 |
|
|
Routing: Completed - No errors found.
|
| 10426 |
|
|
Timing: Completed - No errors found.
|
| 10427 |
|
|
|
| 10428 |
|
|
Number of error messages: 0
|
| 10429 |
|
|
Number of warning messages: 4
|
| 10430 |
|
|
Number of info messages: 1
|
| 10431 |
|
|
|
| 10432 |
|
|
Writing design to file topbox.ncd
|
| 10433 |
|
|
|
| 10434 |
|
|
|
| 10435 |
|
|
|
| 10436 |
|
|
PAR done!
|
| 10437 |
|
|
|
| 10438 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 10439 |
|
|
|
| 10440 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 10441 |
|
|
C:/Xilinx71.
|
| 10442 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 10443 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 10444 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10445 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 10446 |
|
|
ps (24.00 Mhz).
|
| 10447 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 10448 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10449 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 10450 |
|
|
(210.04 Mhz).
|
| 10451 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10452 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10453 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 10454 |
|
|
ps (24.00 Mhz).
|
| 10455 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 10456 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 10457 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 10458 |
|
|
(210.04 Mhz).
|
| 10459 |
|
|
|
| 10460 |
|
|
Analysis completed Sun Sep 24 18:50:32 2006
|
| 10461 |
|
|
--------------------------------------------------------------------------------
|
| 10462 |
|
|
|
| 10463 |
|
|
Generating Report ...
|
| 10464 |
|
|
|
| 10465 |
|
|
Number of warnings: 4
|
| 10466 |
|
|
Total time: 2 secs
|
| 10467 |
|
|
|
| 10468 |
|
|
|
| 10469 |
|
|
|
| 10470 |
|
|
|
| 10471 |
|
|
|
| 10472 |
|
|
|
| 10473 |
|
|
|
| 10474 |
|
|
Started process "Generate Programming File".
|
| 10475 |
|
|
|
| 10476 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 10477 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 10478 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 10479 |
|
|
Interactive Data Sheet.
|
| 10480 |
|
|
|
| 10481 |
|
|
|
| 10482 |
|
|
Project Navigator Auto-Make Log File
|
| 10483 |
|
|
-------------------------------------
|
| 10484 |
|
|
|
| 10485 |
|
|
|
| 10486 |
|
|
|
| 10487 |
|
|
|
| 10488 |
|
|
Started process "View HDL Source".
|
| 10489 |
|
|
|
| 10490 |
|
|
xaw2verilog: Completed successfully
|
| 10491 |
|
|
|
| 10492 |
|
|
|
| 10493 |
|
|
|
| 10494 |
|
|
|
| 10495 |
|
|
|
| 10496 |
|
|
|
| 10497 |
|
|
|
| 10498 |
|
|
|
| 10499 |
|
|
|
| 10500 |
|
|
|
| 10501 |
|
|
Started process "Synthesize".
|
| 10502 |
|
|
|
| 10503 |
|
|
|
| 10504 |
|
|
=========================================================================
|
| 10505 |
|
|
* HDL Compilation *
|
| 10506 |
|
|
=========================================================================
|
| 10507 |
|
|
Compiling verilog file "io.v"
|
| 10508 |
|
|
Module compiled
|
| 10509 |
|
|
Module compiled
|
| 10510 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 10511 |
|
|
Module compiled
|
| 10512 |
|
|
Compiling verilog file "misc.v"
|
| 10513 |
|
|
Module compiled
|
| 10514 |
|
|
Module compiled
|
| 10515 |
|
|
Module compiled
|
| 10516 |
|
|
Module compiled
|
| 10517 |
|
|
Module compiled
|
| 10518 |
|
|
Module compiled
|
| 10519 |
|
|
Compiling verilog file "alu.v"
|
| 10520 |
|
|
Module compiled
|
| 10521 |
|
|
Compiling verilog file "switchsync.v"
|
| 10522 |
|
|
Module compiled
|
| 10523 |
|
|
Compiling verilog file "jkff.v"
|
| 10524 |
|
|
Module compiled
|
| 10525 |
|
|
Compiling verilog file "control.v"
|
| 10526 |
|
|
Module compiled
|
| 10527 |
|
|
Module compiled
|
| 10528 |
|
|
Compiling verilog file "maindcm.v"
|
| 10529 |
|
|
Module compiled
|
| 10530 |
|
|
Compiling verilog file "idecode.v"
|
| 10531 |
|
|
Module compiled
|
| 10532 |
|
|
Compiling verilog file "top.v"
|
| 10533 |
|
|
Module compiled
|
| 10534 |
|
|
Compiling verilog file "rcvr.v"
|
| 10535 |
|
|
Module compiled
|
| 10536 |
|
|
Compiling verilog file "txmit.v"
|
| 10537 |
|
|
Module compiled
|
| 10538 |
|
|
Compiling verilog file "uart.v"
|
| 10539 |
|
|
Module compiled
|
| 10540 |
|
|
Compiling verilog file "topbox.v"
|
| 10541 |
|
|
Module compiled
|
| 10542 |
|
|
No errors in compilation
|
| 10543 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 10544 |
|
|
|
| 10545 |
|
|
|
| 10546 |
|
|
=========================================================================
|
| 10547 |
|
|
* HDL Analysis *
|
| 10548 |
|
|
=========================================================================
|
| 10549 |
|
|
Analyzing top module .
|
| 10550 |
|
|
Module is correct for synthesis.
|
| 10551 |
|
|
|
| 10552 |
|
|
Set property "resynthesize = true" for unit .
|
| 10553 |
|
|
Analyzing module .
|
| 10554 |
|
|
Module is correct for synthesis.
|
| 10555 |
|
|
|
| 10556 |
|
|
Analyzing module .
|
| 10557 |
|
|
pClockFrequency = 50
|
| 10558 |
|
|
pRefreshFrequency = 100
|
| 10559 |
|
|
pUpperLimit = 125000
|
| 10560 |
|
|
pDividerCounterBits = 24
|
| 10561 |
|
|
Module is correct for synthesis.
|
| 10562 |
|
|
|
| 10563 |
|
|
Analyzing module .
|
| 10564 |
|
|
pInitialValue = 0
|
| 10565 |
|
|
pTimerWidth = 19
|
| 10566 |
|
|
pInitialTimerValue = 500000
|
| 10567 |
|
|
Module is correct for synthesis.
|
| 10568 |
|
|
|
| 10569 |
|
|
Analyzing module .
|
| 10570 |
|
|
Module is correct for synthesis.
|
| 10571 |
|
|
|
| 10572 |
|
|
Analyzing module .
|
| 10573 |
|
|
SIZE = 16
|
| 10574 |
|
|
Module is correct for synthesis.
|
| 10575 |
|
|
|
| 10576 |
|
|
Analyzing module .
|
| 10577 |
|
|
Module is correct for synthesis.
|
| 10578 |
|
|
|
| 10579 |
|
|
Analyzing module .
|
| 10580 |
|
|
SIZE = 12
|
| 10581 |
|
|
Module is correct for synthesis.
|
| 10582 |
|
|
|
| 10583 |
|
|
Analyzing module .
|
| 10584 |
|
|
Module is correct for synthesis.
|
| 10585 |
|
|
|
| 10586 |
|
|
Analyzing module .
|
| 10587 |
|
|
VALUE = 0000000000000001
|
| 10588 |
|
|
Module is correct for synthesis.
|
| 10589 |
|
|
|
| 10590 |
|
|
Analyzing module .
|
| 10591 |
|
|
Module is correct for synthesis.
|
| 10592 |
|
|
|
| 10593 |
|
|
Analyzing module .
|
| 10594 |
|
|
VALUE = 1111111111111111
|
| 10595 |
|
|
Module is correct for synthesis.
|
| 10596 |
|
|
|
| 10597 |
|
|
Analyzing module .
|
| 10598 |
|
|
Module is correct for synthesis.
|
| 10599 |
|
|
|
| 10600 |
|
|
Analyzing module .
|
| 10601 |
|
|
VALUE = 0000000000000000
|
| 10602 |
|
|
Module is correct for synthesis.
|
| 10603 |
|
|
|
| 10604 |
|
|
Analyzing module .
|
| 10605 |
|
|
Module is correct for synthesis.
|
| 10606 |
|
|
|
| 10607 |
|
|
Analyzing module .
|
| 10608 |
|
|
Module is correct for synthesis.
|
| 10609 |
|
|
|
| 10610 |
|
|
Analyzing module .
|
| 10611 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 10612 |
|
|
Module is correct for synthesis.
|
| 10613 |
|
|
|
| 10614 |
|
|
Analyzing module .
|
| 10615 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 10616 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 10617 |
|
|
Module is correct for synthesis.
|
| 10618 |
|
|
|
| 10619 |
|
|
Analyzing module .
|
| 10620 |
|
|
Module is correct for synthesis.
|
| 10621 |
|
|
|
| 10622 |
|
|
Analyzing module .
|
| 10623 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10624 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10625 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10626 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10627 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10628 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10629 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10630 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10631 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10632 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10633 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10634 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10635 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10636 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 10637 |
|
|
Module is correct for synthesis.
|
| 10638 |
|
|
|
| 10639 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 10640 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 10641 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 10642 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 10643 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 10644 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 10645 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 10646 |
|
|
Set user-defined property "CLKFX_DIVIDE = 5" for instance in unit .
|
| 10647 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 4" for instance in unit .
|
| 10648 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 10649 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 10650 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 10651 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 10652 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 10653 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 10654 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 10655 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 10656 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 10657 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 10658 |
|
|
Analyzing module .
|
| 10659 |
|
|
Module is correct for synthesis.
|
| 10660 |
|
|
|
| 10661 |
|
|
Analyzing module .
|
| 10662 |
|
|
XTAL_CLK = 40000000
|
| 10663 |
|
|
BAUD = 9600
|
| 10664 |
|
|
CLK_DIV = 130
|
| 10665 |
|
|
CW = 8
|
| 10666 |
|
|
Module is correct for synthesis.
|
| 10667 |
|
|
|
| 10668 |
|
|
Analyzing module .
|
| 10669 |
|
|
Module is correct for synthesis.
|
| 10670 |
|
|
|
| 10671 |
|
|
Analyzing module .
|
| 10672 |
|
|
Module is correct for synthesis.
|
| 10673 |
|
|
|
| 10674 |
|
|
|
| 10675 |
|
|
=========================================================================
|
| 10676 |
|
|
* HDL Synthesis *
|
| 10677 |
|
|
=========================================================================
|
| 10678 |
|
|
|
| 10679 |
|
|
Synthesizing Unit .
|
| 10680 |
|
|
Related source file is "txmit.v".
|
| 10681 |
|
|
Found 1-bit register for signal .
|
| 10682 |
|
|
Found 1-bit register for signal .
|
| 10683 |
|
|
Found 1-bit register for signal .
|
| 10684 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 10685 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 10686 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 10687 |
|
|
Found 1-bit register for signal .
|
| 10688 |
|
|
Found 1-bit register for signal .
|
| 10689 |
|
|
Found 4-bit up counter for signal .
|
| 10690 |
|
|
Found 4-bit up counter for signal .
|
| 10691 |
|
|
Found 8-bit register for signal .
|
| 10692 |
|
|
Found 8-bit register for signal .
|
| 10693 |
|
|
Summary:
|
| 10694 |
|
|
inferred 2 Counter(s).
|
| 10695 |
|
|
inferred 21 D-type flip-flop(s).
|
| 10696 |
|
|
inferred 2 Comparator(s).
|
| 10697 |
|
|
inferred 1 Multiplexer(s).
|
| 10698 |
|
|
Unit synthesized.
|
| 10699 |
|
|
|
| 10700 |
|
|
|
| 10701 |
|
|
Synthesizing Unit .
|
| 10702 |
|
|
Related source file is "rcvr.v".
|
| 10703 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 10704 |
|
|
Found 1-bit register for signal .
|
| 10705 |
|
|
Found 1-bit register for signal .
|
| 10706 |
|
|
Found 1-bit register for signal .
|
| 10707 |
|
|
Found 8-bit tristate buffer for signal .
|
| 10708 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 10709 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 10710 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 10711 |
|
|
Found 1-bit register for signal .
|
| 10712 |
|
|
Found 1-bit register for signal .
|
| 10713 |
|
|
Found 4-bit register for signal .
|
| 10714 |
|
|
Found 4-bit up counter for signal .
|
| 10715 |
|
|
Found 8-bit register for signal .
|
| 10716 |
|
|
Found 7-bit register for signal >.
|
| 10717 |
|
|
Found 1-bit register for signal .
|
| 10718 |
|
|
Found 1-bit register for signal .
|
| 10719 |
|
|
Summary:
|
| 10720 |
|
|
inferred 1 Counter(s).
|
| 10721 |
|
|
inferred 26 D-type flip-flop(s).
|
| 10722 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 10723 |
|
|
inferred 1 Comparator(s).
|
| 10724 |
|
|
inferred 1 Multiplexer(s).
|
| 10725 |
|
|
inferred 8 Tristate(s).
|
| 10726 |
|
|
Unit synthesized.
|
| 10727 |
|
|
|
| 10728 |
|
|
|
| 10729 |
|
|
Synthesizing Unit .
|
| 10730 |
|
|
Related source file is "jkff.v".
|
| 10731 |
|
|
Found 1-bit register for signal .
|
| 10732 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 10733 |
|
|
Summary:
|
| 10734 |
|
|
inferred 1 D-type flip-flop(s).
|
| 10735 |
|
|
inferred 1 Multiplexer(s).
|
| 10736 |
|
|
Unit synthesized.
|
| 10737 |
|
|
|
| 10738 |
|
|
|
| 10739 |
|
|
Synthesizing Unit .
|
| 10740 |
|
|
Related source file is "switchsync.v".
|
| 10741 |
|
|
Found 1-bit register for signal .
|
| 10742 |
|
|
Found 1-bit register for signal .
|
| 10743 |
|
|
Summary:
|
| 10744 |
|
|
inferred 2 D-type flip-flop(s).
|
| 10745 |
|
|
Unit synthesized.
|
| 10746 |
|
|
|
| 10747 |
|
|
|
| 10748 |
|
|
Synthesizing Unit .
|
| 10749 |
|
|
Related source file is "maindcm.v".
|
| 10750 |
|
|
Unit synthesized.
|
| 10751 |
|
|
|
| 10752 |
|
|
|
| 10753 |
|
|
Synthesizing Unit .
|
| 10754 |
|
|
Related source file is "control.v".
|
| 10755 |
|
|
Found 1-bit register for signal .
|
| 10756 |
|
|
Found 1-bit register for signal .
|
| 10757 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 10758 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 10759 |
|
|
Found 3-bit up counter for signal .
|
| 10760 |
|
|
Summary:
|
| 10761 |
|
|
inferred 1 Counter(s).
|
| 10762 |
|
|
inferred 2 D-type flip-flop(s).
|
| 10763 |
|
|
inferred 2 Multiplexer(s).
|
| 10764 |
|
|
Unit synthesized.
|
| 10765 |
|
|
|
| 10766 |
|
|
|
| 10767 |
|
|
Synthesizing Unit .
|
| 10768 |
|
|
Related source file is "misc.v".
|
| 10769 |
|
|
Found 16-bit tristate buffer for signal .
|
| 10770 |
|
|
Summary:
|
| 10771 |
|
|
inferred 16 Tristate(s).
|
| 10772 |
|
|
Unit synthesized.
|
| 10773 |
|
|
|
| 10774 |
|
|
|
| 10775 |
|
|
Synthesizing Unit .
|
| 10776 |
|
|
Related source file is "misc.v".
|
| 10777 |
|
|
Found 16-bit tristate buffer for signal .
|
| 10778 |
|
|
Summary:
|
| 10779 |
|
|
inferred 16 Tristate(s).
|
| 10780 |
|
|
Unit synthesized.
|
| 10781 |
|
|
|
| 10782 |
|
|
|
| 10783 |
|
|
Synthesizing Unit .
|
| 10784 |
|
|
Related source file is "misc.v".
|
| 10785 |
|
|
Found 16-bit tristate buffer for signal .
|
| 10786 |
|
|
Summary:
|
| 10787 |
|
|
inferred 16 Tristate(s).
|
| 10788 |
|
|
Unit synthesized.
|
| 10789 |
|
|
|
| 10790 |
|
|
|
| 10791 |
|
|
Synthesizing Unit .
|
| 10792 |
|
|
Related source file is "misc.v".
|
| 10793 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 10794 |
|
|
Found 16-bit tristate buffer for signal .
|
| 10795 |
|
|
Found 12-bit register for signal .
|
| 10796 |
|
|
Summary:
|
| 10797 |
|
|
inferred 12 D-type flip-flop(s).
|
| 10798 |
|
|
inferred 16 Tristate(s).
|
| 10799 |
|
|
Unit synthesized.
|
| 10800 |
|
|
|
| 10801 |
|
|
|
| 10802 |
|
|
Synthesizing Unit .
|
| 10803 |
|
|
Related source file is "idecode.v".
|
| 10804 |
|
|
Unit synthesized.
|
| 10805 |
|
|
|
| 10806 |
|
|
|
| 10807 |
|
|
Synthesizing Unit .
|
| 10808 |
|
|
Related source file is "control.v".
|
| 10809 |
|
|
Unit synthesized.
|
| 10810 |
|
|
|
| 10811 |
|
|
|
| 10812 |
|
|
Synthesizing Unit .
|
| 10813 |
|
|
Related source file is "alu.v".
|
| 10814 |
|
|
Found 16-bit tristate buffer for signal .
|
| 10815 |
|
|
Found 17-bit subtractor for signal <$AUX_108>.
|
| 10816 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 10817 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 10818 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 10819 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 10820 |
|
|
Summary:
|
| 10821 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 10822 |
|
|
inferred 16 Tristate(s).
|
| 10823 |
|
|
Unit synthesized.
|
| 10824 |
|
|
|
| 10825 |
|
|
|
| 10826 |
|
|
Synthesizing Unit .
|
| 10827 |
|
|
Related source file is "misc.v".
|
| 10828 |
|
|
Unit synthesized.
|
| 10829 |
|
|
|
| 10830 |
|
|
|
| 10831 |
|
|
Synthesizing Unit .
|
| 10832 |
|
|
Related source file is "misc.v".
|
| 10833 |
|
|
Unit synthesized.
|
| 10834 |
|
|
|
| 10835 |
|
|
|
| 10836 |
|
|
Synthesizing Unit .
|
| 10837 |
|
|
Related source file is "misc.v".
|
| 10838 |
|
|
Unit synthesized.
|
| 10839 |
|
|
|
| 10840 |
|
|
|
| 10841 |
|
|
Synthesizing Unit .
|
| 10842 |
|
|
Related source file is "misc.v".
|
| 10843 |
|
|
Unit synthesized.
|
| 10844 |
|
|
|
| 10845 |
|
|
|
| 10846 |
|
|
Synthesizing Unit .
|
| 10847 |
|
|
Related source file is "misc.v".
|
| 10848 |
|
|
Found 16-bit tristate buffer for signal .
|
| 10849 |
|
|
Found 16-bit register for signal .
|
| 10850 |
|
|
Summary:
|
| 10851 |
|
|
inferred 16 D-type flip-flop(s).
|
| 10852 |
|
|
inferred 16 Tristate(s).
|
| 10853 |
|
|
Unit synthesized.
|
| 10854 |
|
|
|
| 10855 |
|
|
|
| 10856 |
|
|
Synthesizing Unit .
|
| 10857 |
|
|
Related source file is "io.v".
|
| 10858 |
|
|
Found 1-bit register for signal .
|
| 10859 |
|
|
Found 1-bit register for signal .
|
| 10860 |
|
|
Found 1-bit register for signal .
|
| 10861 |
|
|
Found 1-bit register for signal .
|
| 10862 |
|
|
Found 1-bit register for signal .
|
| 10863 |
|
|
Found 1-bit register for signal .
|
| 10864 |
|
|
Found 19-bit down counter for signal .
|
| 10865 |
|
|
Found 1-bit register for signal .
|
| 10866 |
|
|
Found 1-bit xor2 for signal .
|
| 10867 |
|
|
Summary:
|
| 10868 |
|
|
inferred 1 Counter(s).
|
| 10869 |
|
|
inferred 7 D-type flip-flop(s).
|
| 10870 |
|
|
Unit synthesized.
|
| 10871 |
|
|
|
| 10872 |
|
|
|
| 10873 |
|
|
Synthesizing Unit .
|
| 10874 |
|
|
Related source file is "io.v".
|
| 10875 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 10876 |
|
|
Found 1-bit register for signal .
|
| 10877 |
|
|
Found 1-bit register for signal .
|
| 10878 |
|
|
Found 1-bit register for signal .
|
| 10879 |
|
|
Found 1-bit register for signal .
|
| 10880 |
|
|
Found 1-bit register for signal .
|
| 10881 |
|
|
Found 1-bit register for signal .
|
| 10882 |
|
|
Found 1-bit register for signal .
|
| 10883 |
|
|
Found 1-bit register for signal .
|
| 10884 |
|
|
Found 1-bit register for signal .
|
| 10885 |
|
|
Found 1-bit register for signal .
|
| 10886 |
|
|
Found 1-bit register for signal .
|
| 10887 |
|
|
Found 1-bit register for signal .
|
| 10888 |
|
|
Found 24-bit up counter for signal .
|
| 10889 |
|
|
Found 1-of-4 decoder for signal .
|
| 10890 |
|
|
Found 2-bit down counter for signal .
|
| 10891 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 10892 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 10893 |
|
|
Summary:
|
| 10894 |
|
|
inferred 1 ROM(s).
|
| 10895 |
|
|
inferred 2 Counter(s).
|
| 10896 |
|
|
inferred 12 D-type flip-flop(s).
|
| 10897 |
|
|
inferred 9 Multiplexer(s).
|
| 10898 |
|
|
inferred 1 Decoder(s).
|
| 10899 |
|
|
Unit synthesized.
|
| 10900 |
|
|
|
| 10901 |
|
|
|
| 10902 |
|
|
Synthesizing Unit .
|
| 10903 |
|
|
Related source file is "uart.v".
|
| 10904 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 10905 |
|
|
Found 1-bit register for signal .
|
| 10906 |
|
|
Found 8-bit up counter for signal .
|
| 10907 |
|
|
Found 1-bit register for signal .
|
| 10908 |
|
|
Summary:
|
| 10909 |
|
|
inferred 1 Counter(s).
|
| 10910 |
|
|
inferred 2 D-type flip-flop(s).
|
| 10911 |
|
|
inferred 1 Multiplexer(s).
|
| 10912 |
|
|
Unit synthesized.
|
| 10913 |
|
|
|
| 10914 |
|
|
|
| 10915 |
|
|
Synthesizing Unit .
|
| 10916 |
|
|
Related source file is "top.v".
|
| 10917 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 10918 |
|
|
Found 16-bit tristate buffer for signal .
|
| 10919 |
|
|
Found 1-bit register for signal .
|
| 10920 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 10921 |
|
|
Found 16-bit tristate buffer for signal .
|
| 10922 |
|
|
Found 1-bit register for signal .
|
| 10923 |
|
|
Found 1-bit register for signal .
|
| 10924 |
|
|
Found 1-bit register for signal .
|
| 10925 |
|
|
Summary:
|
| 10926 |
|
|
inferred 4 D-type flip-flop(s).
|
| 10927 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 10928 |
|
|
inferred 96 Tristate(s).
|
| 10929 |
|
|
Unit synthesized.
|
| 10930 |
|
|
|
| 10931 |
|
|
|
| 10932 |
|
|
Synthesizing Unit .
|
| 10933 |
|
|
Related source file is "FrontPanel.v".
|
| 10934 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 10935 |
|
|
Found finite state machine for signal .
|
| 10936 |
|
|
-----------------------------------------------------------------------
|
| 10937 |
|
|
| States | 6 |
|
| 10938 |
|
|
| Transitions | 6 |
|
| 10939 |
|
|
| Inputs | 0 |
|
| 10940 |
|
|
| Outputs | 12 |
|
| 10941 |
|
|
| Clock | clockin (rising_edge) |
|
| 10942 |
|
|
| Clock enable | select (positive) |
|
| 10943 |
|
|
| Reset | clear (positive) |
|
| 10944 |
|
|
| Reset type | synchronous |
|
| 10945 |
|
|
| Reset State | 000001 |
|
| 10946 |
|
|
| Encoding | automatic |
|
| 10947 |
|
|
| Implementation | LUT |
|
| 10948 |
|
|
-----------------------------------------------------------------------
|
| 10949 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 10950 |
|
|
Found 4-bit register for signal .
|
| 10951 |
|
|
Found 16-bit register for signal .
|
| 10952 |
|
|
Summary:
|
| 10953 |
|
|
inferred 1 Finite State Machine(s).
|
| 10954 |
|
|
inferred 16 D-type flip-flop(s).
|
| 10955 |
|
|
inferred 16 Multiplexer(s).
|
| 10956 |
|
|
Unit synthesized.
|
| 10957 |
|
|
|
| 10958 |
|
|
|
| 10959 |
|
|
Synthesizing Unit .
|
| 10960 |
|
|
Related source file is "topbox.v".
|
| 10961 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 10962 |
|
|
Found 16-bit tristate buffer for signal .
|
| 10963 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 10964 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 10965 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 10966 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 10967 |
|
|
Found 4-bit register for signal .
|
| 10968 |
|
|
Found 1-bit register for signal .
|
| 10969 |
|
|
Found 1-bit register for signal .
|
| 10970 |
|
|
Found 16-bit register for signal .
|
| 10971 |
|
|
Summary:
|
| 10972 |
|
|
inferred 22 D-type flip-flop(s).
|
| 10973 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 10974 |
|
|
inferred 6 Multiplexer(s).
|
| 10975 |
|
|
inferred 48 Tristate(s).
|
| 10976 |
|
|
Unit synthesized.
|
| 10977 |
|
|
|
| 10978 |
|
|
|
| 10979 |
|
|
=========================================================================
|
| 10980 |
|
|
* Advanced HDL Synthesis *
|
| 10981 |
|
|
=========================================================================
|
| 10982 |
|
|
|
| 10983 |
|
|
Advanced RAM inference ...
|
| 10984 |
|
|
Advanced multiplier inference ...
|
| 10985 |
|
|
Advanced Registered AddSub inference ...
|
| 10986 |
|
|
Analyzing FSM for best encoding.
|
| 10987 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 10988 |
|
|
--------------------
|
| 10989 |
|
|
State | Encoding
|
| 10990 |
|
|
--------------------
|
| 10991 |
|
|
000001 | 100000
|
| 10992 |
|
|
000010 | 010000
|
| 10993 |
|
|
000100 | 001000
|
| 10994 |
|
|
001000 | 000100
|
| 10995 |
|
|
010000 | 000010
|
| 10996 |
|
|
100000 | 000001
|
| 10997 |
|
|
--------------------
|
| 10998 |
|
|
Dynamic shift register inference ...
|
| 10999 |
|
|
|
| 11000 |
|
|
=========================================================================
|
| 11001 |
|
|
HDL Synthesis Report
|
| 11002 |
|
|
|
| 11003 |
|
|
Macro Statistics
|
| 11004 |
|
|
# FSMs : 1
|
| 11005 |
|
|
# ROMs : 1
|
| 11006 |
|
|
16x7-bit ROM : 1
|
| 11007 |
|
|
# Adders/Subtractors : 5
|
| 11008 |
|
|
12-bit adder carry out : 1
|
| 11009 |
|
|
16-bit adder carry out : 1
|
| 11010 |
|
|
17-bit subtractor : 1
|
| 11011 |
|
|
4-bit adder : 2
|
| 11012 |
|
|
# Counters : 10
|
| 11013 |
|
|
19-bit down counter : 3
|
| 11014 |
|
|
2-bit down counter : 1
|
| 11015 |
|
|
24-bit up counter : 1
|
| 11016 |
|
|
3-bit up counter : 1
|
| 11017 |
|
|
4-bit up counter : 3
|
| 11018 |
|
|
8-bit up counter : 1
|
| 11019 |
|
|
# Registers : 138
|
| 11020 |
|
|
1-bit register : 125
|
| 11021 |
|
|
12-bit register : 4
|
| 11022 |
|
|
16-bit register : 4
|
| 11023 |
|
|
4-bit register : 3
|
| 11024 |
|
|
8-bit register : 2
|
| 11025 |
|
|
# Comparators : 3
|
| 11026 |
|
|
4-bit comparator greater : 2
|
| 11027 |
|
|
4-bit comparator less : 1
|
| 11028 |
|
|
# Multiplexers : 15
|
| 11029 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 11030 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 11031 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 11032 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 11033 |
|
|
# Decoders : 1
|
| 11034 |
|
|
1-of-4 decoder : 1
|
| 11035 |
|
|
# Tristates : 97
|
| 11036 |
|
|
1-bit tristate buffer : 80
|
| 11037 |
|
|
16-bit tristate buffer : 16
|
| 11038 |
|
|
8-bit tristate buffer : 1
|
| 11039 |
|
|
# Xors : 6
|
| 11040 |
|
|
1-bit xor2 : 5
|
| 11041 |
|
|
16-bit xor2 : 1
|
| 11042 |
|
|
|
| 11043 |
|
|
=========================================================================
|
| 11044 |
|
|
|
| 11045 |
|
|
=========================================================================
|
| 11046 |
|
|
* Low Level Synthesis *
|
| 11047 |
|
|
=========================================================================
|
| 11048 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 11049 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 11050 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 11051 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 11052 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 11053 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 11054 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 11055 |
|
|
|
| 11056 |
|
|
Optimizing unit ...
|
| 11057 |
|
|
|
| 11058 |
|
|
Optimizing unit ...
|
| 11059 |
|
|
|
| 11060 |
|
|
Optimizing unit ...
|
| 11061 |
|
|
|
| 11062 |
|
|
Optimizing unit ...
|
| 11063 |
|
|
|
| 11064 |
|
|
Optimizing unit ...
|
| 11065 |
|
|
|
| 11066 |
|
|
Optimizing unit ...
|
| 11067 |
|
|
|
| 11068 |
|
|
Optimizing unit ...
|
| 11069 |
|
|
|
| 11070 |
|
|
Optimizing unit ...
|
| 11071 |
|
|
|
| 11072 |
|
|
Optimizing unit ...
|
| 11073 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 11074 |
|
|
|
| 11075 |
|
|
Mapping all equations...
|
| 11076 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 11077 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 11078 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 11079 |
|
|
Building and optimizing final netlist ...
|
| 11080 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
|
| 11081 |
|
|
FlipFlop CPU/IR/regvalue_0 has been replicated 3 time(s)
|
| 11082 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
|
| 11083 |
|
|
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
|
| 11084 |
|
|
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
|
| 11085 |
|
|
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
|
| 11086 |
|
|
FlipFlop CPU/IR/regvalue_15 has been replicated 1 time(s)
|
| 11087 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
|
| 11088 |
|
|
FlipFlop CPU/IR/regvalue_4 has been replicated 1 time(s)
|
| 11089 |
|
|
FlipFlop CPU/IR/regvalue_6 has been replicated 1 time(s)
|
| 11090 |
|
|
FlipFlop CPU/ctl/sim/counter_0 has been replicated 4 time(s)
|
| 11091 |
|
|
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
|
| 11092 |
|
|
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
|
| 11093 |
|
|
FlipFlop loadnow has been replicated 2 time(s)
|
| 11094 |
|
|
|
| 11095 |
|
|
=========================================================================
|
| 11096 |
|
|
* Final Report *
|
| 11097 |
|
|
=========================================================================
|
| 11098 |
|
|
|
| 11099 |
|
|
Device utilization summary:
|
| 11100 |
|
|
---------------------------
|
| 11101 |
|
|
|
| 11102 |
|
|
Selected Device : 3s200ft256-4
|
| 11103 |
|
|
|
| 11104 |
|
|
Number of Slices: 611 out of 1920 31%
|
| 11105 |
|
|
Number of Slice Flip Flops: 393 out of 3840 10%
|
| 11106 |
|
|
Number of 4 input LUTs: 1081 out of 3840 28%
|
| 11107 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 11108 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 11109 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 11110 |
|
|
|
| 11111 |
|
|
|
| 11112 |
|
|
=========================================================================
|
| 11113 |
|
|
TIMING REPORT
|
| 11114 |
|
|
|
| 11115 |
|
|
|
| 11116 |
|
|
Clock Information:
|
| 11117 |
|
|
------------------
|
| 11118 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 11119 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 11120 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 11121 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 393 |
|
| 11122 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 11123 |
|
|
|
| 11124 |
|
|
Timing Summary:
|
| 11125 |
|
|
---------------
|
| 11126 |
|
|
Speed Grade: -4
|
| 11127 |
|
|
|
| 11128 |
|
|
Minimum period: 16.248ns (Maximum Frequency: 61.546MHz)
|
| 11129 |
|
|
Minimum input arrival time before clock: 10.576ns
|
| 11130 |
|
|
Maximum output required time after clock: 24.383ns
|
| 11131 |
|
|
Maximum combinational path delay: 14.555ns
|
| 11132 |
|
|
|
| 11133 |
|
|
=========================================================================
|
| 11134 |
|
|
|
| 11135 |
|
|
|
| 11136 |
|
|
|
| 11137 |
|
|
|
| 11138 |
|
|
Started process "Translate".
|
| 11139 |
|
|
|
| 11140 |
|
|
|
| 11141 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 11142 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 11143 |
|
|
|
| 11144 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 11145 |
|
|
|
| 11146 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 11147 |
|
|
|
| 11148 |
|
|
Checking timing specifications ...
|
| 11149 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 11150 |
|
|
TS_clkin*0.800000 HIGH 50.000000%
|
| 11151 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.800000 PHASE +
|
| 11152 |
|
|
12.500000 nS HIGH 50.000000%
|
| 11153 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 11154 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 11155 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 11156 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 11157 |
|
|
from this group.
|
| 11158 |
|
|
Checking expanded design ...
|
| 11159 |
|
|
|
| 11160 |
|
|
NGDBUILD Design Results Summary:
|
| 11161 |
|
|
Number of errors: 0
|
| 11162 |
|
|
Number of warnings: 1
|
| 11163 |
|
|
|
| 11164 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 11165 |
|
|
|
| 11166 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 11167 |
|
|
|
| 11168 |
|
|
NGDBUILD done.
|
| 11169 |
|
|
|
| 11170 |
|
|
|
| 11171 |
|
|
|
| 11172 |
|
|
|
| 11173 |
|
|
Started process "Map".
|
| 11174 |
|
|
|
| 11175 |
|
|
Using target part "3s200ft256-4".
|
| 11176 |
|
|
Mapping design into LUTs...
|
| 11177 |
|
|
Running directed packing...
|
| 11178 |
|
|
Running delay-based LUT packing...
|
| 11179 |
|
|
Running timing-driven packing...
|
| 11180 |
|
|
|
| 11181 |
|
|
Phase 1.1
|
| 11182 |
|
|
Phase 1.1 (Checksum:98d16f) REAL time: 1 secs
|
| 11183 |
|
|
|
| 11184 |
|
|
Phase 2.31
|
| 11185 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
|
| 11186 |
|
|
|
| 11187 |
|
|
Phase 3.2
|
| 11188 |
|
|
.
|
| 11189 |
|
|
|
| 11190 |
|
|
|
| 11191 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
|
| 11192 |
|
|
|
| 11193 |
|
|
Phase 4.4
|
| 11194 |
|
|
................................
|
| 11195 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 4 secs
|
| 11196 |
|
|
|
| 11197 |
|
|
Phase 5.28
|
| 11198 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 4 secs
|
| 11199 |
|
|
|
| 11200 |
|
|
Phase 6.8
|
| 11201 |
|
|
..................................
|
| 11202 |
|
|
.......
|
| 11203 |
|
|
.................................................
|
| 11204 |
|
|
....................................
|
| 11205 |
|
|
...............
|
| 11206 |
|
|
Phase 6.8 (Checksum:185cdc0) REAL time: 13 secs
|
| 11207 |
|
|
|
| 11208 |
|
|
Phase 7.29
|
| 11209 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 13 secs
|
| 11210 |
|
|
|
| 11211 |
|
|
Phase 8.5
|
| 11212 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 13 secs
|
| 11213 |
|
|
|
| 11214 |
|
|
Phase 9.18
|
| 11215 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 37 secs
|
| 11216 |
|
|
|
| 11217 |
|
|
Phase 10.5
|
| 11218 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 37 secs
|
| 11219 |
|
|
|
| 11220 |
|
|
|
| 11221 |
|
|
Design Summary:
|
| 11222 |
|
|
Number of errors: 0
|
| 11223 |
|
|
Number of warnings: 11
|
| 11224 |
|
|
Logic Utilization:
|
| 11225 |
|
|
Number of Slice Flip Flops: 367 out of 3,840 9%
|
| 11226 |
|
|
Number of 4 input LUTs: 1,128 out of 3,840 29%
|
| 11227 |
|
|
Logic Distribution:
|
| 11228 |
|
|
Number of occupied Slices: 634 out of 1,920 33%
|
| 11229 |
|
|
Number of Slices containing only related logic: 634 out of 634 100%
|
| 11230 |
|
|
Number of Slices containing unrelated logic: 0 out of 634 0%
|
| 11231 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 11232 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 11233 |
|
|
Number used as logic: 1,128
|
| 11234 |
|
|
Number used as a route-thru: 7
|
| 11235 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 11236 |
|
|
IOB Flip Flops: 26
|
| 11237 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 11238 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 11239 |
|
|
|
| 11240 |
|
|
Total equivalent gate count for design: 17,797
|
| 11241 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 11242 |
|
|
Peak Memory Usage: 134 MB
|
| 11243 |
|
|
|
| 11244 |
|
|
Mapping completed.
|
| 11245 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 11246 |
|
|
|
| 11247 |
|
|
|
| 11248 |
|
|
|
| 11249 |
|
|
|
| 11250 |
|
|
Started process "Place & Route".
|
| 11251 |
|
|
|
| 11252 |
|
|
|
| 11253 |
|
|
|
| 11254 |
|
|
|
| 11255 |
|
|
Constraints file: topbox.pcf.
|
| 11256 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 11257 |
|
|
C:/Xilinx71.
|
| 11258 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 11259 |
|
|
|
| 11260 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 11261 |
|
|
Celsius)
|
| 11262 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 11263 |
|
|
|
| 11264 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 11265 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
|
| 11266 |
|
|
(40.00 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 11267 |
|
|
ps (24.00 Mhz).
|
| 11268 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 11269 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
|
| 11270 |
|
|
(40.00 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 11271 |
|
|
(210.04 Mhz).
|
| 11272 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 11273 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
|
| 11274 |
|
|
(40.00 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 11275 |
|
|
ps (24.00 Mhz).
|
| 11276 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 11277 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
|
| 11278 |
|
|
(40.00 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 11279 |
|
|
(210.04 Mhz).
|
| 11280 |
|
|
|
| 11281 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 11282 |
|
|
|
| 11283 |
|
|
|
| 11284 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 11285 |
|
|
achieve better performance.
|
| 11286 |
|
|
|
| 11287 |
|
|
Device Utilization Summary:
|
| 11288 |
|
|
|
| 11289 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 11290 |
|
|
Number of DCMs 1 out of 4 25%
|
| 11291 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 11292 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 11293 |
|
|
|
| 11294 |
|
|
Number of Slices 634 out of 1920 33%
|
| 11295 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 11296 |
|
|
|
| 11297 |
|
|
|
| 11298 |
|
|
|
| 11299 |
|
|
Overall effort level (-ol): High (set by user)
|
| 11300 |
|
|
Router effort level (-rl): High (set by user)
|
| 11301 |
|
|
|
| 11302 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 11303 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 11304 |
|
|
|
| 11305 |
|
|
Starting Router
|
| 11306 |
|
|
|
| 11307 |
|
|
Phase 1: 4858 unrouted; REAL time: 4 secs
|
| 11308 |
|
|
|
| 11309 |
|
|
Phase 2: 4533 unrouted; REAL time: 4 secs
|
| 11310 |
|
|
|
| 11311 |
|
|
Phase 3: 2287 unrouted; REAL time: 5 secs
|
| 11312 |
|
|
|
| 11313 |
|
|
Phase 4: 2287 unrouted; (43949) REAL time: 5 secs
|
| 11314 |
|
|
|
| 11315 |
|
|
Phase 5: 2491 unrouted; (19206) REAL time: 6 secs
|
| 11316 |
|
|
|
| 11317 |
|
|
Phase 6: 2531 unrouted; (18488) REAL time: 7 secs
|
| 11318 |
|
|
|
| 11319 |
|
|
Phase 7: 0 unrouted; (54873) REAL time: 39 secs
|
| 11320 |
|
|
|
| 11321 |
|
|
Phase 8: 0 unrouted; (54873) REAL time: 40 secs
|
| 11322 |
|
|
|
| 11323 |
|
|
Phase 9: 0 unrouted; (47807) REAL time: 2 mins 12 secs
|
| 11324 |
|
|
|
| 11325 |
|
|
Phase 10: 0 unrouted; (47807) REAL time: 2 mins 53 secs
|
| 11326 |
|
|
|
| 11327 |
|
|
|
| 11328 |
|
|
Total REAL time to Router completion: 2 mins 54 secs
|
| 11329 |
|
|
Total CPU time to Router completion: 2 mins 53 secs
|
| 11330 |
|
|
|
| 11331 |
|
|
Generating "PAR" statistics.
|
| 11332 |
|
|
|
| 11333 |
|
|
**************************
|
| 11334 |
|
|
Generating Clock Report
|
| 11335 |
|
|
**************************
|
| 11336 |
|
|
|
| 11337 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 11338 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 11339 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 11340 |
|
|
| clk | BUFGMUX2| No | 305 | 0.041 | 1.051 |
|
| 11341 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 11342 |
|
|
|
| 11343 |
|
|
Timing Score: 47807
|
| 11344 |
|
|
|
| 11345 |
|
|
WARNING:Par:62 - Timing constraints have not been met.
|
| 11346 |
|
|
|
| 11347 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 11348 |
|
|
This may be due to a setup or hold violation.
|
| 11349 |
|
|
|
| 11350 |
|
|
--------------------------------------------------------------------------------
|
| 11351 |
|
|
Constraint | Requested | Actual | Logic
|
| 11352 |
|
|
| | | Levels
|
| 11353 |
|
|
--------------------------------------------------------------------------------
|
| 11354 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 50 MHz | N/A | N/A | N/A
|
| 11355 |
|
|
HIGH 50% | | |
|
| 11356 |
|
|
--------------------------------------------------------------------------------
|
| 11357 |
|
|
* TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 25.000ns | 26.994ns | 7
|
| 11358 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 11359 |
|
|
TS_clkin * 0.8 HIGH 50% | | |
|
| 11360 |
|
|
--------------------------------------------------------------------------------
|
| 11361 |
|
|
* TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 25.000ns | 29.060ns | 11
|
| 11362 |
|
|
_wclk" TS_clkin * 0.8 PHASE 12.5 ns | | |
|
| 11363 |
|
|
HIGH 50% | | |
|
| 11364 |
|
|
--------------------------------------------------------------------------------
|
| 11365 |
|
|
|
| 11366 |
|
|
|
| 11367 |
|
|
2 constraints not met.
|
| 11368 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 11369 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 11370 |
|
|
Generating Pad Report.
|
| 11371 |
|
|
|
| 11372 |
|
|
All signals are completely routed.
|
| 11373 |
|
|
|
| 11374 |
|
|
Total REAL time to PAR completion: 2 mins 55 secs
|
| 11375 |
|
|
Total CPU time to PAR completion: 2 mins 53 secs
|
| 11376 |
|
|
|
| 11377 |
|
|
Peak Memory Usage: 100 MB
|
| 11378 |
|
|
|
| 11379 |
|
|
Placer: Not run.
|
| 11380 |
|
|
Routing: Completed - No errors found.
|
| 11381 |
|
|
Timing: Completed - 82 errors found.
|
| 11382 |
|
|
|
| 11383 |
|
|
Number of error messages: 0
|
| 11384 |
|
|
Number of warning messages: 5
|
| 11385 |
|
|
Number of info messages: 1
|
| 11386 |
|
|
|
| 11387 |
|
|
Writing design to file topbox.ncd
|
| 11388 |
|
|
|
| 11389 |
|
|
|
| 11390 |
|
|
|
| 11391 |
|
|
PAR done!
|
| 11392 |
|
|
|
| 11393 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 11394 |
|
|
|
| 11395 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 11396 |
|
|
C:/Xilinx71.
|
| 11397 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 11398 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 11399 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
|
| 11400 |
|
|
(40.00 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 11401 |
|
|
ps (24.00 Mhz).
|
| 11402 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 11403 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
|
| 11404 |
|
|
(40.00 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 11405 |
|
|
(210.04 Mhz).
|
| 11406 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 11407 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
|
| 11408 |
|
|
(40.00 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 11409 |
|
|
ps (24.00 Mhz).
|
| 11410 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 11411 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
|
| 11412 |
|
|
(40.00 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 11413 |
|
|
(210.04 Mhz).
|
| 11414 |
|
|
|
| 11415 |
|
|
Analysis completed Sun Sep 24 22:15:06 2006
|
| 11416 |
|
|
--------------------------------------------------------------------------------
|
| 11417 |
|
|
|
| 11418 |
|
|
Generating Report ...
|
| 11419 |
|
|
|
| 11420 |
|
|
Number of warnings: 4
|
| 11421 |
|
|
Total time: 3 secs
|
| 11422 |
|
|
|
| 11423 |
|
|
|
| 11424 |
|
|
|
| 11425 |
|
|
|
| 11426 |
|
|
|
| 11427 |
|
|
|
| 11428 |
|
|
|
| 11429 |
|
|
Started process "Generate Programming File".
|
| 11430 |
|
|
|
| 11431 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 11432 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 11433 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 11434 |
|
|
Interactive Data Sheet.
|
| 11435 |
|
|
|
| 11436 |
|
|
|
| 11437 |
|
|
Project Navigator Auto-Make Log File
|
| 11438 |
|
|
-------------------------------------
|
| 11439 |
|
|
|
| 11440 |
|
|
|
| 11441 |
|
|
|
| 11442 |
|
|
|
| 11443 |
|
|
Started process "Translate".
|
| 11444 |
|
|
|
| 11445 |
|
|
|
| 11446 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 11447 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 11448 |
|
|
|
| 11449 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 11450 |
|
|
|
| 11451 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 11452 |
|
|
|
| 11453 |
|
|
Checking timing specifications ...
|
| 11454 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 11455 |
|
|
TS_clkin*0.800000 HIGH 50.000000%
|
| 11456 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.800000 PHASE +
|
| 11457 |
|
|
15.625000 nS HIGH 50.000000%
|
| 11458 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 11459 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 11460 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 11461 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 11462 |
|
|
from this group.
|
| 11463 |
|
|
Checking expanded design ...
|
| 11464 |
|
|
|
| 11465 |
|
|
NGDBUILD Design Results Summary:
|
| 11466 |
|
|
Number of errors: 0
|
| 11467 |
|
|
Number of warnings: 1
|
| 11468 |
|
|
|
| 11469 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 11470 |
|
|
|
| 11471 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 11472 |
|
|
|
| 11473 |
|
|
NGDBUILD done.
|
| 11474 |
|
|
|
| 11475 |
|
|
|
| 11476 |
|
|
|
| 11477 |
|
|
|
| 11478 |
|
|
Started process "Map".
|
| 11479 |
|
|
|
| 11480 |
|
|
Using target part "3s200ft256-4".
|
| 11481 |
|
|
Mapping design into LUTs...
|
| 11482 |
|
|
Running directed packing...
|
| 11483 |
|
|
Running delay-based LUT packing...
|
| 11484 |
|
|
Running timing-driven packing...
|
| 11485 |
|
|
|
| 11486 |
|
|
Phase 1.1
|
| 11487 |
|
|
Phase 1.1 (Checksum:98d16f) REAL time: 0 secs
|
| 11488 |
|
|
|
| 11489 |
|
|
Phase 2.31
|
| 11490 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs
|
| 11491 |
|
|
|
| 11492 |
|
|
Phase 3.2
|
| 11493 |
|
|
.
|
| 11494 |
|
|
|
| 11495 |
|
|
|
| 11496 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs
|
| 11497 |
|
|
|
| 11498 |
|
|
Phase 4.4
|
| 11499 |
|
|
................................
|
| 11500 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs
|
| 11501 |
|
|
|
| 11502 |
|
|
Phase 5.28
|
| 11503 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs
|
| 11504 |
|
|
|
| 11505 |
|
|
Phase 6.8
|
| 11506 |
|
|
........................
|
| 11507 |
|
|
......
|
| 11508 |
|
|
........................................
|
| 11509 |
|
|
...............
|
| 11510 |
|
|
...............
|
| 11511 |
|
|
Phase 6.8 (Checksum:c19e1b) REAL time: 10 secs
|
| 11512 |
|
|
|
| 11513 |
|
|
Phase 7.29
|
| 11514 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs
|
| 11515 |
|
|
|
| 11516 |
|
|
Phase 8.5
|
| 11517 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs
|
| 11518 |
|
|
|
| 11519 |
|
|
Phase 9.18
|
| 11520 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 23 secs
|
| 11521 |
|
|
|
| 11522 |
|
|
Phase 10.5
|
| 11523 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 23 secs
|
| 11524 |
|
|
|
| 11525 |
|
|
|
| 11526 |
|
|
Design Summary:
|
| 11527 |
|
|
Number of errors: 0
|
| 11528 |
|
|
Number of warnings: 11
|
| 11529 |
|
|
Logic Utilization:
|
| 11530 |
|
|
Number of Slice Flip Flops: 367 out of 3,840 9%
|
| 11531 |
|
|
Number of 4 input LUTs: 1,128 out of 3,840 29%
|
| 11532 |
|
|
Logic Distribution:
|
| 11533 |
|
|
Number of occupied Slices: 662 out of 1,920 34%
|
| 11534 |
|
|
Number of Slices containing only related logic: 662 out of 662 100%
|
| 11535 |
|
|
Number of Slices containing unrelated logic: 0 out of 662 0%
|
| 11536 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 11537 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 11538 |
|
|
Number used as logic: 1,128
|
| 11539 |
|
|
Number used as a route-thru: 7
|
| 11540 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 11541 |
|
|
IOB Flip Flops: 26
|
| 11542 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 11543 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 11544 |
|
|
|
| 11545 |
|
|
Total equivalent gate count for design: 17,797
|
| 11546 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 11547 |
|
|
Peak Memory Usage: 133 MB
|
| 11548 |
|
|
|
| 11549 |
|
|
Mapping completed.
|
| 11550 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 11551 |
|
|
|
| 11552 |
|
|
|
| 11553 |
|
|
|
| 11554 |
|
|
|
| 11555 |
|
|
Started process "Place & Route".
|
| 11556 |
|
|
|
| 11557 |
|
|
|
| 11558 |
|
|
|
| 11559 |
|
|
|
| 11560 |
|
|
Constraints file: topbox.pcf.
|
| 11561 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 11562 |
|
|
C:/Xilinx71.
|
| 11563 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 11564 |
|
|
|
| 11565 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 11566 |
|
|
Celsius)
|
| 11567 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 11568 |
|
|
|
| 11569 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 11570 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
|
| 11571 |
|
|
(32.00 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 11572 |
|
|
ps (24.00 Mhz).
|
| 11573 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 11574 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
|
| 11575 |
|
|
(32.00 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 11576 |
|
|
(210.04 Mhz).
|
| 11577 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 11578 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
|
| 11579 |
|
|
(32.00 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 11580 |
|
|
ps (24.00 Mhz).
|
| 11581 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 11582 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
|
| 11583 |
|
|
(32.00 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 11584 |
|
|
(210.04 Mhz).
|
| 11585 |
|
|
|
| 11586 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 11587 |
|
|
|
| 11588 |
|
|
|
| 11589 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 11590 |
|
|
achieve better performance.
|
| 11591 |
|
|
|
| 11592 |
|
|
Device Utilization Summary:
|
| 11593 |
|
|
|
| 11594 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 11595 |
|
|
Number of DCMs 1 out of 4 25%
|
| 11596 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 11597 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 11598 |
|
|
|
| 11599 |
|
|
Number of Slices 662 out of 1920 34%
|
| 11600 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 11601 |
|
|
|
| 11602 |
|
|
|
| 11603 |
|
|
|
| 11604 |
|
|
Overall effort level (-ol): High (set by user)
|
| 11605 |
|
|
Router effort level (-rl): High (set by user)
|
| 11606 |
|
|
|
| 11607 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 11608 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 11609 |
|
|
|
| 11610 |
|
|
Starting Router
|
| 11611 |
|
|
|
| 11612 |
|
|
Phase 1: 4870 unrouted; REAL time: 4 secs
|
| 11613 |
|
|
|
| 11614 |
|
|
Phase 2: 4541 unrouted; REAL time: 4 secs
|
| 11615 |
|
|
|
| 11616 |
|
|
Phase 3: 2229 unrouted; REAL time: 5 secs
|
| 11617 |
|
|
|
| 11618 |
|
|
Phase 4: 2229 unrouted; (0) REAL time: 5 secs
|
| 11619 |
|
|
|
| 11620 |
|
|
Phase 5: 2229 unrouted; (0) REAL time: 5 secs
|
| 11621 |
|
|
|
| 11622 |
|
|
Phase 6: 2229 unrouted; (0) REAL time: 5 secs
|
| 11623 |
|
|
|
| 11624 |
|
|
Phase 7: 0 unrouted; (1830) REAL time: 19 secs
|
| 11625 |
|
|
|
| 11626 |
|
|
Phase 8: 0 unrouted; (1830) REAL time: 20 secs
|
| 11627 |
|
|
|
| 11628 |
|
|
Phase 9: 0 unrouted; (0) REAL time: 22 secs
|
| 11629 |
|
|
|
| 11630 |
|
|
Phase 10: 0 unrouted; (0) REAL time: 22 secs
|
| 11631 |
|
|
|
| 11632 |
|
|
|
| 11633 |
|
|
Total REAL time to Router completion: 22 secs
|
| 11634 |
|
|
Total CPU time to Router completion: 22 secs
|
| 11635 |
|
|
|
| 11636 |
|
|
Generating "PAR" statistics.
|
| 11637 |
|
|
|
| 11638 |
|
|
**************************
|
| 11639 |
|
|
Generating Clock Report
|
| 11640 |
|
|
**************************
|
| 11641 |
|
|
|
| 11642 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 11643 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 11644 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 11645 |
|
|
| clk | BUFGMUX2| No | 310 | 0.041 | 1.051 |
|
| 11646 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 11647 |
|
|
|
| 11648 |
|
|
Timing Score: 0
|
| 11649 |
|
|
|
| 11650 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 11651 |
|
|
This may be due to a setup or hold violation.
|
| 11652 |
|
|
|
| 11653 |
|
|
--------------------------------------------------------------------------------
|
| 11654 |
|
|
Constraint | Requested | Actual | Logic
|
| 11655 |
|
|
| | | Levels
|
| 11656 |
|
|
--------------------------------------------------------------------------------
|
| 11657 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 40 MHz | N/A | N/A | N/A
|
| 11658 |
|
|
HIGH 50% | | |
|
| 11659 |
|
|
--------------------------------------------------------------------------------
|
| 11660 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 31.250ns | 31.234ns | 8
|
| 11661 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 11662 |
|
|
TS_clkin * 0.8 HIGH 50% | | |
|
| 11663 |
|
|
--------------------------------------------------------------------------------
|
| 11664 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 31.250ns | 31.236ns | 10
|
| 11665 |
|
|
_wclk" TS_clkin * 0.8 PHASE 15.625 ns | | |
|
| 11666 |
|
|
HIGH 50% | | |
|
| 11667 |
|
|
--------------------------------------------------------------------------------
|
| 11668 |
|
|
|
| 11669 |
|
|
|
| 11670 |
|
|
All constraints were met.
|
| 11671 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 11672 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 11673 |
|
|
Generating Pad Report.
|
| 11674 |
|
|
|
| 11675 |
|
|
All signals are completely routed.
|
| 11676 |
|
|
|
| 11677 |
|
|
Total REAL time to PAR completion: 23 secs
|
| 11678 |
|
|
Total CPU time to PAR completion: 23 secs
|
| 11679 |
|
|
|
| 11680 |
|
|
Peak Memory Usage: 99 MB
|
| 11681 |
|
|
|
| 11682 |
|
|
Placer: Not run.
|
| 11683 |
|
|
Routing: Completed - No errors found.
|
| 11684 |
|
|
Timing: Completed - No errors found.
|
| 11685 |
|
|
|
| 11686 |
|
|
Number of error messages: 0
|
| 11687 |
|
|
Number of warning messages: 4
|
| 11688 |
|
|
Number of info messages: 1
|
| 11689 |
|
|
|
| 11690 |
|
|
Writing design to file topbox.ncd
|
| 11691 |
|
|
|
| 11692 |
|
|
|
| 11693 |
|
|
|
| 11694 |
|
|
PAR done!
|
| 11695 |
|
|
|
| 11696 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 11697 |
|
|
|
| 11698 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 11699 |
|
|
C:/Xilinx71.
|
| 11700 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 11701 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 11702 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
|
| 11703 |
|
|
(32.00 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 11704 |
|
|
ps (24.00 Mhz).
|
| 11705 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 11706 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
|
| 11707 |
|
|
(32.00 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 11708 |
|
|
(210.04 Mhz).
|
| 11709 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 11710 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
|
| 11711 |
|
|
(32.00 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 11712 |
|
|
ps (24.00 Mhz).
|
| 11713 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 11714 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
|
| 11715 |
|
|
(32.00 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 11716 |
|
|
(210.04 Mhz).
|
| 11717 |
|
|
|
| 11718 |
|
|
Analysis completed Sun Sep 24 22:18:33 2006
|
| 11719 |
|
|
--------------------------------------------------------------------------------
|
| 11720 |
|
|
|
| 11721 |
|
|
Generating Report ...
|
| 11722 |
|
|
|
| 11723 |
|
|
Number of warnings: 4
|
| 11724 |
|
|
Total time: 2 secs
|
| 11725 |
|
|
|
| 11726 |
|
|
|
| 11727 |
|
|
|
| 11728 |
|
|
|
| 11729 |
|
|
|
| 11730 |
|
|
|
| 11731 |
|
|
|
| 11732 |
|
|
Started process "Generate Programming File".
|
| 11733 |
|
|
|
| 11734 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 11735 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 11736 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 11737 |
|
|
Interactive Data Sheet.
|
| 11738 |
|
|
|
| 11739 |
|
|
|
| 11740 |
|
|
Project Navigator Auto-Make Log File
|
| 11741 |
|
|
-------------------------------------
|
| 11742 |
|
|
|
| 11743 |
|
|
|
| 11744 |
|
|
|
| 11745 |
|
|
|
| 11746 |
|
|
Started process "View HDL Source".
|
| 11747 |
|
|
|
| 11748 |
|
|
xaw2verilog: Completed successfully
|
| 11749 |
|
|
|
| 11750 |
|
|
|
| 11751 |
|
|
|
| 11752 |
|
|
|
| 11753 |
|
|
|
| 11754 |
|
|
|
| 11755 |
|
|
|
| 11756 |
|
|
|
| 11757 |
|
|
|
| 11758 |
|
|
|
| 11759 |
|
|
Started process "Synthesize".
|
| 11760 |
|
|
|
| 11761 |
|
|
|
| 11762 |
|
|
=========================================================================
|
| 11763 |
|
|
* HDL Compilation *
|
| 11764 |
|
|
=========================================================================
|
| 11765 |
|
|
Compiling verilog file "io.v"
|
| 11766 |
|
|
Module compiled
|
| 11767 |
|
|
Module compiled
|
| 11768 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 11769 |
|
|
Module compiled
|
| 11770 |
|
|
Compiling verilog file "misc.v"
|
| 11771 |
|
|
Module compiled
|
| 11772 |
|
|
Module compiled
|
| 11773 |
|
|
Module compiled
|
| 11774 |
|
|
Module compiled
|
| 11775 |
|
|
Module compiled
|
| 11776 |
|
|
Module compiled
|
| 11777 |
|
|
Compiling verilog file "alu.v"
|
| 11778 |
|
|
Module compiled
|
| 11779 |
|
|
Compiling verilog file "switchsync.v"
|
| 11780 |
|
|
Module compiled
|
| 11781 |
|
|
Compiling verilog file "jkff.v"
|
| 11782 |
|
|
Module compiled
|
| 11783 |
|
|
Compiling verilog file "control.v"
|
| 11784 |
|
|
Module compiled
|
| 11785 |
|
|
Module compiled
|
| 11786 |
|
|
Compiling verilog file "maindcm.v"
|
| 11787 |
|
|
Module compiled
|
| 11788 |
|
|
Compiling verilog file "idecode.v"
|
| 11789 |
|
|
Module compiled
|
| 11790 |
|
|
Compiling verilog file "top.v"
|
| 11791 |
|
|
Module compiled
|
| 11792 |
|
|
Compiling verilog file "rcvr.v"
|
| 11793 |
|
|
Module compiled
|
| 11794 |
|
|
Compiling verilog file "txmit.v"
|
| 11795 |
|
|
Module compiled
|
| 11796 |
|
|
Compiling verilog file "uart.v"
|
| 11797 |
|
|
Module compiled
|
| 11798 |
|
|
Compiling verilog file "topbox.v"
|
| 11799 |
|
|
Module compiled
|
| 11800 |
|
|
No errors in compilation
|
| 11801 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 11802 |
|
|
|
| 11803 |
|
|
|
| 11804 |
|
|
=========================================================================
|
| 11805 |
|
|
* HDL Analysis *
|
| 11806 |
|
|
=========================================================================
|
| 11807 |
|
|
Analyzing top module .
|
| 11808 |
|
|
Module is correct for synthesis.
|
| 11809 |
|
|
|
| 11810 |
|
|
Set property "resynthesize = true" for unit .
|
| 11811 |
|
|
Analyzing module .
|
| 11812 |
|
|
Module is correct for synthesis.
|
| 11813 |
|
|
|
| 11814 |
|
|
Analyzing module .
|
| 11815 |
|
|
pClockFrequency = 50
|
| 11816 |
|
|
pRefreshFrequency = 100
|
| 11817 |
|
|
pUpperLimit = 125000
|
| 11818 |
|
|
pDividerCounterBits = 24
|
| 11819 |
|
|
Module is correct for synthesis.
|
| 11820 |
|
|
|
| 11821 |
|
|
Analyzing module .
|
| 11822 |
|
|
pInitialValue = 0
|
| 11823 |
|
|
pTimerWidth = 19
|
| 11824 |
|
|
pInitialTimerValue = 500000
|
| 11825 |
|
|
Module is correct for synthesis.
|
| 11826 |
|
|
|
| 11827 |
|
|
Analyzing module .
|
| 11828 |
|
|
Module is correct for synthesis.
|
| 11829 |
|
|
|
| 11830 |
|
|
Analyzing module .
|
| 11831 |
|
|
SIZE = 16
|
| 11832 |
|
|
Module is correct for synthesis.
|
| 11833 |
|
|
|
| 11834 |
|
|
Analyzing module .
|
| 11835 |
|
|
Module is correct for synthesis.
|
| 11836 |
|
|
|
| 11837 |
|
|
Analyzing module .
|
| 11838 |
|
|
SIZE = 12
|
| 11839 |
|
|
Module is correct for synthesis.
|
| 11840 |
|
|
|
| 11841 |
|
|
Analyzing module .
|
| 11842 |
|
|
Module is correct for synthesis.
|
| 11843 |
|
|
|
| 11844 |
|
|
Analyzing module .
|
| 11845 |
|
|
VALUE = 0000000000000001
|
| 11846 |
|
|
Module is correct for synthesis.
|
| 11847 |
|
|
|
| 11848 |
|
|
Analyzing module .
|
| 11849 |
|
|
Module is correct for synthesis.
|
| 11850 |
|
|
|
| 11851 |
|
|
Analyzing module .
|
| 11852 |
|
|
VALUE = 1111111111111111
|
| 11853 |
|
|
Module is correct for synthesis.
|
| 11854 |
|
|
|
| 11855 |
|
|
Analyzing module .
|
| 11856 |
|
|
Module is correct for synthesis.
|
| 11857 |
|
|
|
| 11858 |
|
|
Analyzing module .
|
| 11859 |
|
|
VALUE = 0000000000000000
|
| 11860 |
|
|
Module is correct for synthesis.
|
| 11861 |
|
|
|
| 11862 |
|
|
Analyzing module .
|
| 11863 |
|
|
Module is correct for synthesis.
|
| 11864 |
|
|
|
| 11865 |
|
|
Analyzing module .
|
| 11866 |
|
|
Module is correct for synthesis.
|
| 11867 |
|
|
|
| 11868 |
|
|
Analyzing module .
|
| 11869 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 11870 |
|
|
Module is correct for synthesis.
|
| 11871 |
|
|
|
| 11872 |
|
|
Analyzing module .
|
| 11873 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 11874 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 11875 |
|
|
Module is correct for synthesis.
|
| 11876 |
|
|
|
| 11877 |
|
|
Analyzing module .
|
| 11878 |
|
|
Module is correct for synthesis.
|
| 11879 |
|
|
|
| 11880 |
|
|
Analyzing module .
|
| 11881 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11882 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11883 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11884 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11885 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11886 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11887 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11888 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11889 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11890 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11891 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11892 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11893 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11894 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 11895 |
|
|
Module is correct for synthesis.
|
| 11896 |
|
|
|
| 11897 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 11898 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 11899 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 11900 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 11901 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 11902 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 11903 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 11904 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 11905 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 11906 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 11907 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 11908 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 11909 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 11910 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 11911 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 11912 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 11913 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 11914 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 11915 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 11916 |
|
|
Analyzing module .
|
| 11917 |
|
|
Module is correct for synthesis.
|
| 11918 |
|
|
|
| 11919 |
|
|
Analyzing module .
|
| 11920 |
|
|
XTAL_CLK = 35000000
|
| 11921 |
|
|
BAUD = 9600
|
| 11922 |
|
|
CLK_DIV = 113
|
| 11923 |
|
|
CW = 8
|
| 11924 |
|
|
Module is correct for synthesis.
|
| 11925 |
|
|
|
| 11926 |
|
|
Analyzing module .
|
| 11927 |
|
|
Module is correct for synthesis.
|
| 11928 |
|
|
|
| 11929 |
|
|
Analyzing module .
|
| 11930 |
|
|
Module is correct for synthesis.
|
| 11931 |
|
|
|
| 11932 |
|
|
|
| 11933 |
|
|
=========================================================================
|
| 11934 |
|
|
* HDL Synthesis *
|
| 11935 |
|
|
=========================================================================
|
| 11936 |
|
|
|
| 11937 |
|
|
Synthesizing Unit .
|
| 11938 |
|
|
Related source file is "txmit.v".
|
| 11939 |
|
|
Found 1-bit register for signal .
|
| 11940 |
|
|
Found 1-bit register for signal .
|
| 11941 |
|
|
Found 1-bit register for signal .
|
| 11942 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 11943 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 11944 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 11945 |
|
|
Found 1-bit register for signal .
|
| 11946 |
|
|
Found 1-bit register for signal .
|
| 11947 |
|
|
Found 4-bit up counter for signal .
|
| 11948 |
|
|
Found 4-bit up counter for signal .
|
| 11949 |
|
|
Found 8-bit register for signal .
|
| 11950 |
|
|
Found 8-bit register for signal .
|
| 11951 |
|
|
Summary:
|
| 11952 |
|
|
inferred 2 Counter(s).
|
| 11953 |
|
|
inferred 21 D-type flip-flop(s).
|
| 11954 |
|
|
inferred 2 Comparator(s).
|
| 11955 |
|
|
inferred 1 Multiplexer(s).
|
| 11956 |
|
|
Unit synthesized.
|
| 11957 |
|
|
|
| 11958 |
|
|
|
| 11959 |
|
|
Synthesizing Unit .
|
| 11960 |
|
|
Related source file is "rcvr.v".
|
| 11961 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 11962 |
|
|
Found 1-bit register for signal .
|
| 11963 |
|
|
Found 1-bit register for signal .
|
| 11964 |
|
|
Found 1-bit register for signal .
|
| 11965 |
|
|
Found 8-bit tristate buffer for signal .
|
| 11966 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 11967 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 11968 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 11969 |
|
|
Found 1-bit register for signal .
|
| 11970 |
|
|
Found 1-bit register for signal .
|
| 11971 |
|
|
Found 4-bit register for signal .
|
| 11972 |
|
|
Found 4-bit up counter for signal .
|
| 11973 |
|
|
Found 8-bit register for signal .
|
| 11974 |
|
|
Found 7-bit register for signal >.
|
| 11975 |
|
|
Found 1-bit register for signal .
|
| 11976 |
|
|
Found 1-bit register for signal .
|
| 11977 |
|
|
Summary:
|
| 11978 |
|
|
inferred 1 Counter(s).
|
| 11979 |
|
|
inferred 26 D-type flip-flop(s).
|
| 11980 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 11981 |
|
|
inferred 1 Comparator(s).
|
| 11982 |
|
|
inferred 1 Multiplexer(s).
|
| 11983 |
|
|
inferred 8 Tristate(s).
|
| 11984 |
|
|
Unit synthesized.
|
| 11985 |
|
|
|
| 11986 |
|
|
|
| 11987 |
|
|
Synthesizing Unit .
|
| 11988 |
|
|
Related source file is "jkff.v".
|
| 11989 |
|
|
Found 1-bit register for signal .
|
| 11990 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 11991 |
|
|
Summary:
|
| 11992 |
|
|
inferred 1 D-type flip-flop(s).
|
| 11993 |
|
|
inferred 1 Multiplexer(s).
|
| 11994 |
|
|
Unit synthesized.
|
| 11995 |
|
|
|
| 11996 |
|
|
|
| 11997 |
|
|
Synthesizing Unit .
|
| 11998 |
|
|
Related source file is "switchsync.v".
|
| 11999 |
|
|
Found 1-bit register for signal .
|
| 12000 |
|
|
Found 1-bit register for signal .
|
| 12001 |
|
|
Summary:
|
| 12002 |
|
|
inferred 2 D-type flip-flop(s).
|
| 12003 |
|
|
Unit synthesized.
|
| 12004 |
|
|
|
| 12005 |
|
|
|
| 12006 |
|
|
Synthesizing Unit .
|
| 12007 |
|
|
Related source file is "maindcm.v".
|
| 12008 |
|
|
Unit synthesized.
|
| 12009 |
|
|
|
| 12010 |
|
|
|
| 12011 |
|
|
Synthesizing Unit .
|
| 12012 |
|
|
Related source file is "control.v".
|
| 12013 |
|
|
Found 1-bit register for signal .
|
| 12014 |
|
|
Found 1-bit register for signal .
|
| 12015 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 12016 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 12017 |
|
|
Found 3-bit up counter for signal .
|
| 12018 |
|
|
Summary:
|
| 12019 |
|
|
inferred 1 Counter(s).
|
| 12020 |
|
|
inferred 2 D-type flip-flop(s).
|
| 12021 |
|
|
inferred 2 Multiplexer(s).
|
| 12022 |
|
|
Unit synthesized.
|
| 12023 |
|
|
|
| 12024 |
|
|
|
| 12025 |
|
|
Synthesizing Unit .
|
| 12026 |
|
|
Related source file is "misc.v".
|
| 12027 |
|
|
Found 16-bit tristate buffer for signal .
|
| 12028 |
|
|
Summary:
|
| 12029 |
|
|
inferred 16 Tristate(s).
|
| 12030 |
|
|
Unit synthesized.
|
| 12031 |
|
|
|
| 12032 |
|
|
|
| 12033 |
|
|
Synthesizing Unit .
|
| 12034 |
|
|
Related source file is "misc.v".
|
| 12035 |
|
|
Found 16-bit tristate buffer for signal .
|
| 12036 |
|
|
Summary:
|
| 12037 |
|
|
inferred 16 Tristate(s).
|
| 12038 |
|
|
Unit synthesized.
|
| 12039 |
|
|
|
| 12040 |
|
|
|
| 12041 |
|
|
Synthesizing Unit .
|
| 12042 |
|
|
Related source file is "misc.v".
|
| 12043 |
|
|
Found 16-bit tristate buffer for signal .
|
| 12044 |
|
|
Summary:
|
| 12045 |
|
|
inferred 16 Tristate(s).
|
| 12046 |
|
|
Unit synthesized.
|
| 12047 |
|
|
|
| 12048 |
|
|
|
| 12049 |
|
|
Synthesizing Unit .
|
| 12050 |
|
|
Related source file is "misc.v".
|
| 12051 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 12052 |
|
|
Found 16-bit tristate buffer for signal .
|
| 12053 |
|
|
Found 12-bit register for signal .
|
| 12054 |
|
|
Summary:
|
| 12055 |
|
|
inferred 12 D-type flip-flop(s).
|
| 12056 |
|
|
inferred 16 Tristate(s).
|
| 12057 |
|
|
Unit synthesized.
|
| 12058 |
|
|
|
| 12059 |
|
|
|
| 12060 |
|
|
Synthesizing Unit .
|
| 12061 |
|
|
Related source file is "idecode.v".
|
| 12062 |
|
|
Unit synthesized.
|
| 12063 |
|
|
|
| 12064 |
|
|
|
| 12065 |
|
|
Synthesizing Unit .
|
| 12066 |
|
|
Related source file is "control.v".
|
| 12067 |
|
|
Unit synthesized.
|
| 12068 |
|
|
|
| 12069 |
|
|
|
| 12070 |
|
|
Synthesizing Unit .
|
| 12071 |
|
|
Related source file is "alu.v".
|
| 12072 |
|
|
Found 16-bit tristate buffer for signal .
|
| 12073 |
|
|
Found 17-bit subtractor for signal <$AUX_108>.
|
| 12074 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 12075 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 12076 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 12077 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 12078 |
|
|
Summary:
|
| 12079 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 12080 |
|
|
inferred 16 Tristate(s).
|
| 12081 |
|
|
Unit synthesized.
|
| 12082 |
|
|
|
| 12083 |
|
|
|
| 12084 |
|
|
Synthesizing Unit .
|
| 12085 |
|
|
Related source file is "misc.v".
|
| 12086 |
|
|
Unit synthesized.
|
| 12087 |
|
|
|
| 12088 |
|
|
|
| 12089 |
|
|
Synthesizing Unit .
|
| 12090 |
|
|
Related source file is "misc.v".
|
| 12091 |
|
|
Unit synthesized.
|
| 12092 |
|
|
|
| 12093 |
|
|
|
| 12094 |
|
|
Synthesizing Unit .
|
| 12095 |
|
|
Related source file is "misc.v".
|
| 12096 |
|
|
Unit synthesized.
|
| 12097 |
|
|
|
| 12098 |
|
|
|
| 12099 |
|
|
Synthesizing Unit .
|
| 12100 |
|
|
Related source file is "misc.v".
|
| 12101 |
|
|
Unit synthesized.
|
| 12102 |
|
|
|
| 12103 |
|
|
|
| 12104 |
|
|
Synthesizing Unit .
|
| 12105 |
|
|
Related source file is "misc.v".
|
| 12106 |
|
|
Found 16-bit tristate buffer for signal .
|
| 12107 |
|
|
Found 16-bit register for signal .
|
| 12108 |
|
|
Summary:
|
| 12109 |
|
|
inferred 16 D-type flip-flop(s).
|
| 12110 |
|
|
inferred 16 Tristate(s).
|
| 12111 |
|
|
Unit synthesized.
|
| 12112 |
|
|
|
| 12113 |
|
|
|
| 12114 |
|
|
Synthesizing Unit .
|
| 12115 |
|
|
Related source file is "io.v".
|
| 12116 |
|
|
Found 1-bit register for signal .
|
| 12117 |
|
|
Found 1-bit register for signal .
|
| 12118 |
|
|
Found 1-bit register for signal .
|
| 12119 |
|
|
Found 1-bit register for signal .
|
| 12120 |
|
|
Found 1-bit register for signal .
|
| 12121 |
|
|
Found 1-bit register for signal .
|
| 12122 |
|
|
Found 19-bit down counter for signal .
|
| 12123 |
|
|
Found 1-bit register for signal .
|
| 12124 |
|
|
Found 1-bit xor2 for signal .
|
| 12125 |
|
|
Summary:
|
| 12126 |
|
|
inferred 1 Counter(s).
|
| 12127 |
|
|
inferred 7 D-type flip-flop(s).
|
| 12128 |
|
|
Unit synthesized.
|
| 12129 |
|
|
|
| 12130 |
|
|
|
| 12131 |
|
|
Synthesizing Unit .
|
| 12132 |
|
|
Related source file is "io.v".
|
| 12133 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 12134 |
|
|
Found 1-bit register for signal .
|
| 12135 |
|
|
Found 1-bit register for signal .
|
| 12136 |
|
|
Found 1-bit register for signal .
|
| 12137 |
|
|
Found 1-bit register for signal .
|
| 12138 |
|
|
Found 1-bit register for signal .
|
| 12139 |
|
|
Found 1-bit register for signal .
|
| 12140 |
|
|
Found 1-bit register for signal .
|
| 12141 |
|
|
Found 1-bit register for signal .
|
| 12142 |
|
|
Found 1-bit register for signal .
|
| 12143 |
|
|
Found 1-bit register for signal .
|
| 12144 |
|
|
Found 1-bit register for signal .
|
| 12145 |
|
|
Found 1-bit register for signal .
|
| 12146 |
|
|
Found 24-bit up counter for signal .
|
| 12147 |
|
|
Found 1-of-4 decoder for signal .
|
| 12148 |
|
|
Found 2-bit down counter for signal .
|
| 12149 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 12150 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 12151 |
|
|
Summary:
|
| 12152 |
|
|
inferred 1 ROM(s).
|
| 12153 |
|
|
inferred 2 Counter(s).
|
| 12154 |
|
|
inferred 12 D-type flip-flop(s).
|
| 12155 |
|
|
inferred 9 Multiplexer(s).
|
| 12156 |
|
|
inferred 1 Decoder(s).
|
| 12157 |
|
|
Unit synthesized.
|
| 12158 |
|
|
|
| 12159 |
|
|
|
| 12160 |
|
|
Synthesizing Unit .
|
| 12161 |
|
|
Related source file is "uart.v".
|
| 12162 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 12163 |
|
|
Found 1-bit register for signal .
|
| 12164 |
|
|
Found 8-bit up counter for signal .
|
| 12165 |
|
|
Found 1-bit register for signal .
|
| 12166 |
|
|
Summary:
|
| 12167 |
|
|
inferred 1 Counter(s).
|
| 12168 |
|
|
inferred 2 D-type flip-flop(s).
|
| 12169 |
|
|
inferred 1 Multiplexer(s).
|
| 12170 |
|
|
Unit synthesized.
|
| 12171 |
|
|
|
| 12172 |
|
|
|
| 12173 |
|
|
Synthesizing Unit .
|
| 12174 |
|
|
Related source file is "top.v".
|
| 12175 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 12176 |
|
|
Found 16-bit tristate buffer for signal .
|
| 12177 |
|
|
Found 1-bit register for signal .
|
| 12178 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 12179 |
|
|
Found 16-bit tristate buffer for signal .
|
| 12180 |
|
|
Found 1-bit register for signal .
|
| 12181 |
|
|
Found 1-bit register for signal .
|
| 12182 |
|
|
Found 1-bit register for signal .
|
| 12183 |
|
|
Summary:
|
| 12184 |
|
|
inferred 4 D-type flip-flop(s).
|
| 12185 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 12186 |
|
|
inferred 96 Tristate(s).
|
| 12187 |
|
|
Unit synthesized.
|
| 12188 |
|
|
|
| 12189 |
|
|
|
| 12190 |
|
|
Synthesizing Unit .
|
| 12191 |
|
|
Related source file is "FrontPanel.v".
|
| 12192 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 12193 |
|
|
Found finite state machine for signal .
|
| 12194 |
|
|
-----------------------------------------------------------------------
|
| 12195 |
|
|
| States | 6 |
|
| 12196 |
|
|
| Transitions | 6 |
|
| 12197 |
|
|
| Inputs | 0 |
|
| 12198 |
|
|
| Outputs | 12 |
|
| 12199 |
|
|
| Clock | clockin (rising_edge) |
|
| 12200 |
|
|
| Clock enable | select (positive) |
|
| 12201 |
|
|
| Reset | clear (positive) |
|
| 12202 |
|
|
| Reset type | synchronous |
|
| 12203 |
|
|
| Reset State | 000001 |
|
| 12204 |
|
|
| Encoding | automatic |
|
| 12205 |
|
|
| Implementation | LUT |
|
| 12206 |
|
|
-----------------------------------------------------------------------
|
| 12207 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 12208 |
|
|
Found 4-bit register for signal .
|
| 12209 |
|
|
Found 16-bit register for signal .
|
| 12210 |
|
|
Summary:
|
| 12211 |
|
|
inferred 1 Finite State Machine(s).
|
| 12212 |
|
|
inferred 16 D-type flip-flop(s).
|
| 12213 |
|
|
inferred 16 Multiplexer(s).
|
| 12214 |
|
|
Unit synthesized.
|
| 12215 |
|
|
|
| 12216 |
|
|
|
| 12217 |
|
|
Synthesizing Unit .
|
| 12218 |
|
|
Related source file is "topbox.v".
|
| 12219 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 12220 |
|
|
Found 16-bit tristate buffer for signal .
|
| 12221 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 12222 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 12223 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 12224 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 12225 |
|
|
Found 4-bit register for signal .
|
| 12226 |
|
|
Found 1-bit register for signal .
|
| 12227 |
|
|
Found 1-bit register for signal .
|
| 12228 |
|
|
Found 16-bit register for signal .
|
| 12229 |
|
|
Summary:
|
| 12230 |
|
|
inferred 22 D-type flip-flop(s).
|
| 12231 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 12232 |
|
|
inferred 6 Multiplexer(s).
|
| 12233 |
|
|
inferred 48 Tristate(s).
|
| 12234 |
|
|
Unit synthesized.
|
| 12235 |
|
|
|
| 12236 |
|
|
|
| 12237 |
|
|
=========================================================================
|
| 12238 |
|
|
* Advanced HDL Synthesis *
|
| 12239 |
|
|
=========================================================================
|
| 12240 |
|
|
|
| 12241 |
|
|
Advanced RAM inference ...
|
| 12242 |
|
|
Advanced multiplier inference ...
|
| 12243 |
|
|
Advanced Registered AddSub inference ...
|
| 12244 |
|
|
Analyzing FSM for best encoding.
|
| 12245 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 12246 |
|
|
--------------------
|
| 12247 |
|
|
State | Encoding
|
| 12248 |
|
|
--------------------
|
| 12249 |
|
|
000001 | 100000
|
| 12250 |
|
|
000010 | 010000
|
| 12251 |
|
|
000100 | 001000
|
| 12252 |
|
|
001000 | 000100
|
| 12253 |
|
|
010000 | 000010
|
| 12254 |
|
|
100000 | 000001
|
| 12255 |
|
|
--------------------
|
| 12256 |
|
|
Dynamic shift register inference ...
|
| 12257 |
|
|
|
| 12258 |
|
|
=========================================================================
|
| 12259 |
|
|
HDL Synthesis Report
|
| 12260 |
|
|
|
| 12261 |
|
|
Macro Statistics
|
| 12262 |
|
|
# FSMs : 1
|
| 12263 |
|
|
# ROMs : 1
|
| 12264 |
|
|
16x7-bit ROM : 1
|
| 12265 |
|
|
# Adders/Subtractors : 5
|
| 12266 |
|
|
12-bit adder carry out : 1
|
| 12267 |
|
|
16-bit adder carry out : 1
|
| 12268 |
|
|
17-bit subtractor : 1
|
| 12269 |
|
|
4-bit adder : 2
|
| 12270 |
|
|
# Counters : 10
|
| 12271 |
|
|
19-bit down counter : 3
|
| 12272 |
|
|
2-bit down counter : 1
|
| 12273 |
|
|
24-bit up counter : 1
|
| 12274 |
|
|
3-bit up counter : 1
|
| 12275 |
|
|
4-bit up counter : 3
|
| 12276 |
|
|
8-bit up counter : 1
|
| 12277 |
|
|
# Registers : 138
|
| 12278 |
|
|
1-bit register : 125
|
| 12279 |
|
|
12-bit register : 4
|
| 12280 |
|
|
16-bit register : 4
|
| 12281 |
|
|
4-bit register : 3
|
| 12282 |
|
|
8-bit register : 2
|
| 12283 |
|
|
# Comparators : 3
|
| 12284 |
|
|
4-bit comparator greater : 2
|
| 12285 |
|
|
4-bit comparator less : 1
|
| 12286 |
|
|
# Multiplexers : 15
|
| 12287 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 12288 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 12289 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 12290 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 12291 |
|
|
# Decoders : 1
|
| 12292 |
|
|
1-of-4 decoder : 1
|
| 12293 |
|
|
# Tristates : 97
|
| 12294 |
|
|
1-bit tristate buffer : 80
|
| 12295 |
|
|
16-bit tristate buffer : 16
|
| 12296 |
|
|
8-bit tristate buffer : 1
|
| 12297 |
|
|
# Xors : 6
|
| 12298 |
|
|
1-bit xor2 : 5
|
| 12299 |
|
|
16-bit xor2 : 1
|
| 12300 |
|
|
|
| 12301 |
|
|
=========================================================================
|
| 12302 |
|
|
|
| 12303 |
|
|
=========================================================================
|
| 12304 |
|
|
* Low Level Synthesis *
|
| 12305 |
|
|
=========================================================================
|
| 12306 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 12307 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 12308 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 12309 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 12310 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 12311 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 12312 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 12313 |
|
|
|
| 12314 |
|
|
Optimizing unit ...
|
| 12315 |
|
|
|
| 12316 |
|
|
Optimizing unit ...
|
| 12317 |
|
|
|
| 12318 |
|
|
Optimizing unit ...
|
| 12319 |
|
|
|
| 12320 |
|
|
Optimizing unit ...
|
| 12321 |
|
|
|
| 12322 |
|
|
Optimizing unit ...
|
| 12323 |
|
|
|
| 12324 |
|
|
Optimizing unit ...
|
| 12325 |
|
|
|
| 12326 |
|
|
Optimizing unit ...
|
| 12327 |
|
|
|
| 12328 |
|
|
Optimizing unit ...
|
| 12329 |
|
|
|
| 12330 |
|
|
Optimizing unit ...
|
| 12331 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 12332 |
|
|
|
| 12333 |
|
|
Mapping all equations...
|
| 12334 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 12335 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 12336 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 12337 |
|
|
Building and optimizing final netlist ...
|
| 12338 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
|
| 12339 |
|
|
FlipFlop CPU/IR/regvalue_0 has been replicated 3 time(s)
|
| 12340 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
|
| 12341 |
|
|
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
|
| 12342 |
|
|
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
|
| 12343 |
|
|
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
|
| 12344 |
|
|
FlipFlop CPU/IR/regvalue_15 has been replicated 1 time(s)
|
| 12345 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
|
| 12346 |
|
|
FlipFlop CPU/IR/regvalue_4 has been replicated 1 time(s)
|
| 12347 |
|
|
FlipFlop CPU/IR/regvalue_6 has been replicated 1 time(s)
|
| 12348 |
|
|
FlipFlop CPU/ctl/sim/counter_0 has been replicated 4 time(s)
|
| 12349 |
|
|
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
|
| 12350 |
|
|
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
|
| 12351 |
|
|
FlipFlop loadnow has been replicated 2 time(s)
|
| 12352 |
|
|
|
| 12353 |
|
|
=========================================================================
|
| 12354 |
|
|
* Final Report *
|
| 12355 |
|
|
=========================================================================
|
| 12356 |
|
|
|
| 12357 |
|
|
Device utilization summary:
|
| 12358 |
|
|
---------------------------
|
| 12359 |
|
|
|
| 12360 |
|
|
Selected Device : 3s200ft256-4
|
| 12361 |
|
|
|
| 12362 |
|
|
Number of Slices: 611 out of 1920 31%
|
| 12363 |
|
|
Number of Slice Flip Flops: 393 out of 3840 10%
|
| 12364 |
|
|
Number of 4 input LUTs: 1081 out of 3840 28%
|
| 12365 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 12366 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 12367 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 12368 |
|
|
|
| 12369 |
|
|
|
| 12370 |
|
|
=========================================================================
|
| 12371 |
|
|
TIMING REPORT
|
| 12372 |
|
|
|
| 12373 |
|
|
|
| 12374 |
|
|
Clock Information:
|
| 12375 |
|
|
------------------
|
| 12376 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 12377 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 12378 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 12379 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 393 |
|
| 12380 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 12381 |
|
|
|
| 12382 |
|
|
Timing Summary:
|
| 12383 |
|
|
---------------
|
| 12384 |
|
|
Speed Grade: -4
|
| 12385 |
|
|
|
| 12386 |
|
|
Minimum period: 14.217ns (Maximum Frequency: 70.338MHz)
|
| 12387 |
|
|
Minimum input arrival time before clock: 10.576ns
|
| 12388 |
|
|
Maximum output required time after clock: 24.383ns
|
| 12389 |
|
|
Maximum combinational path delay: 14.555ns
|
| 12390 |
|
|
|
| 12391 |
|
|
=========================================================================
|
| 12392 |
|
|
|
| 12393 |
|
|
|
| 12394 |
|
|
|
| 12395 |
|
|
|
| 12396 |
|
|
Started process "Translate".
|
| 12397 |
|
|
|
| 12398 |
|
|
|
| 12399 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 12400 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 12401 |
|
|
|
| 12402 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 12403 |
|
|
|
| 12404 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 12405 |
|
|
|
| 12406 |
|
|
Checking timing specifications ...
|
| 12407 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 12408 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 12409 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 12410 |
|
|
20.408000 nS HIGH 50.000000%
|
| 12411 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 12412 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 12413 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 12414 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 12415 |
|
|
from this group.
|
| 12416 |
|
|
Checking expanded design ...
|
| 12417 |
|
|
|
| 12418 |
|
|
NGDBUILD Design Results Summary:
|
| 12419 |
|
|
Number of errors: 0
|
| 12420 |
|
|
Number of warnings: 1
|
| 12421 |
|
|
|
| 12422 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 12423 |
|
|
|
| 12424 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 12425 |
|
|
|
| 12426 |
|
|
NGDBUILD done.
|
| 12427 |
|
|
|
| 12428 |
|
|
|
| 12429 |
|
|
|
| 12430 |
|
|
|
| 12431 |
|
|
Started process "Map".
|
| 12432 |
|
|
|
| 12433 |
|
|
Using target part "3s200ft256-4".
|
| 12434 |
|
|
Mapping design into LUTs...
|
| 12435 |
|
|
Running directed packing...
|
| 12436 |
|
|
Running delay-based LUT packing...
|
| 12437 |
|
|
Running timing-driven packing...
|
| 12438 |
|
|
|
| 12439 |
|
|
Phase 1.1
|
| 12440 |
|
|
Phase 1.1 (Checksum:98d16f) REAL time: 0 secs
|
| 12441 |
|
|
|
| 12442 |
|
|
Phase 2.31
|
| 12443 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs
|
| 12444 |
|
|
|
| 12445 |
|
|
Phase 3.2
|
| 12446 |
|
|
.
|
| 12447 |
|
|
|
| 12448 |
|
|
|
| 12449 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs
|
| 12450 |
|
|
|
| 12451 |
|
|
Phase 4.4
|
| 12452 |
|
|
..............
|
| 12453 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs
|
| 12454 |
|
|
|
| 12455 |
|
|
Phase 5.28
|
| 12456 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs
|
| 12457 |
|
|
|
| 12458 |
|
|
Phase 6.8
|
| 12459 |
|
|
.....................
|
| 12460 |
|
|
........
|
| 12461 |
|
|
.........................
|
| 12462 |
|
|
...............
|
| 12463 |
|
|
...............
|
| 12464 |
|
|
Phase 6.8 (Checksum:aa8209) REAL time: 9 secs
|
| 12465 |
|
|
|
| 12466 |
|
|
Phase 7.29
|
| 12467 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 9 secs
|
| 12468 |
|
|
|
| 12469 |
|
|
Phase 8.5
|
| 12470 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 9 secs
|
| 12471 |
|
|
|
| 12472 |
|
|
Phase 9.18
|
| 12473 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 18 secs
|
| 12474 |
|
|
|
| 12475 |
|
|
Phase 10.5
|
| 12476 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 18 secs
|
| 12477 |
|
|
|
| 12478 |
|
|
|
| 12479 |
|
|
Design Summary:
|
| 12480 |
|
|
Number of errors: 0
|
| 12481 |
|
|
Number of warnings: 11
|
| 12482 |
|
|
Logic Utilization:
|
| 12483 |
|
|
Number of Slice Flip Flops: 367 out of 3,840 9%
|
| 12484 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 12485 |
|
|
Logic Distribution:
|
| 12486 |
|
|
Number of occupied Slices: 691 out of 1,920 35%
|
| 12487 |
|
|
Number of Slices containing only related logic: 691 out of 691 100%
|
| 12488 |
|
|
Number of Slices containing unrelated logic: 0 out of 691 0%
|
| 12489 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 12490 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 12491 |
|
|
Number used as logic: 1,131
|
| 12492 |
|
|
Number used as a route-thru: 4
|
| 12493 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 12494 |
|
|
IOB Flip Flops: 26
|
| 12495 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 12496 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 12497 |
|
|
|
| 12498 |
|
|
Total equivalent gate count for design: 17,815
|
| 12499 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 12500 |
|
|
Peak Memory Usage: 133 MB
|
| 12501 |
|
|
|
| 12502 |
|
|
Mapping completed.
|
| 12503 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 12504 |
|
|
|
| 12505 |
|
|
|
| 12506 |
|
|
|
| 12507 |
|
|
|
| 12508 |
|
|
Started process "Place & Route".
|
| 12509 |
|
|
|
| 12510 |
|
|
|
| 12511 |
|
|
|
| 12512 |
|
|
|
| 12513 |
|
|
Constraints file: topbox.pcf.
|
| 12514 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 12515 |
|
|
C:/Xilinx71.
|
| 12516 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 12517 |
|
|
|
| 12518 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 12519 |
|
|
Celsius)
|
| 12520 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 12521 |
|
|
|
| 12522 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 12523 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 12524 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 12525 |
|
|
ps (24.00 Mhz).
|
| 12526 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 12527 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 12528 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 12529 |
|
|
(210.04 Mhz).
|
| 12530 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 12531 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 12532 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 12533 |
|
|
ps (24.00 Mhz).
|
| 12534 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 12535 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 12536 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 12537 |
|
|
(210.04 Mhz).
|
| 12538 |
|
|
|
| 12539 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 12540 |
|
|
|
| 12541 |
|
|
|
| 12542 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 12543 |
|
|
achieve better performance.
|
| 12544 |
|
|
|
| 12545 |
|
|
Device Utilization Summary:
|
| 12546 |
|
|
|
| 12547 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 12548 |
|
|
Number of DCMs 1 out of 4 25%
|
| 12549 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 12550 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 12551 |
|
|
|
| 12552 |
|
|
Number of Slices 691 out of 1920 35%
|
| 12553 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 12554 |
|
|
|
| 12555 |
|
|
|
| 12556 |
|
|
|
| 12557 |
|
|
Overall effort level (-ol): High (set by user)
|
| 12558 |
|
|
Router effort level (-rl): High (set by user)
|
| 12559 |
|
|
|
| 12560 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 12561 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 12562 |
|
|
|
| 12563 |
|
|
Starting Router
|
| 12564 |
|
|
|
| 12565 |
|
|
Phase 1: 4863 unrouted; REAL time: 4 secs
|
| 12566 |
|
|
|
| 12567 |
|
|
Phase 2: 4537 unrouted; REAL time: 4 secs
|
| 12568 |
|
|
|
| 12569 |
|
|
Phase 3: 2179 unrouted; REAL time: 5 secs
|
| 12570 |
|
|
|
| 12571 |
|
|
Phase 4: 2179 unrouted; (0) REAL time: 5 secs
|
| 12572 |
|
|
|
| 12573 |
|
|
Phase 5: 2179 unrouted; (0) REAL time: 5 secs
|
| 12574 |
|
|
|
| 12575 |
|
|
Phase 6: 2179 unrouted; (0) REAL time: 5 secs
|
| 12576 |
|
|
|
| 12577 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 8 secs
|
| 12578 |
|
|
|
| 12579 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 9 secs
|
| 12580 |
|
|
|
| 12581 |
|
|
|
| 12582 |
|
|
Total REAL time to Router completion: 9 secs
|
| 12583 |
|
|
Total CPU time to Router completion: 9 secs
|
| 12584 |
|
|
|
| 12585 |
|
|
Generating "PAR" statistics.
|
| 12586 |
|
|
|
| 12587 |
|
|
**************************
|
| 12588 |
|
|
Generating Clock Report
|
| 12589 |
|
|
**************************
|
| 12590 |
|
|
|
| 12591 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 12592 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 12593 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 12594 |
|
|
| clk | BUFGMUX2| No | 307 | 0.041 | 1.051 |
|
| 12595 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 12596 |
|
|
|
| 12597 |
|
|
Timing Score: 0
|
| 12598 |
|
|
|
| 12599 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 12600 |
|
|
This may be due to a setup or hold violation.
|
| 12601 |
|
|
|
| 12602 |
|
|
--------------------------------------------------------------------------------
|
| 12603 |
|
|
Constraint | Requested | Actual | Logic
|
| 12604 |
|
|
| | | Levels
|
| 12605 |
|
|
--------------------------------------------------------------------------------
|
| 12606 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 12607 |
|
|
HIGH 50% | | |
|
| 12608 |
|
|
--------------------------------------------------------------------------------
|
| 12609 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 36.056ns | 8
|
| 12610 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 12611 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 12612 |
|
|
--------------------------------------------------------------------------------
|
| 12613 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 39.230ns | 12
|
| 12614 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 12615 |
|
|
HIGH 50% | | |
|
| 12616 |
|
|
--------------------------------------------------------------------------------
|
| 12617 |
|
|
|
| 12618 |
|
|
|
| 12619 |
|
|
All constraints were met.
|
| 12620 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 12621 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 12622 |
|
|
Generating Pad Report.
|
| 12623 |
|
|
|
| 12624 |
|
|
All signals are completely routed.
|
| 12625 |
|
|
|
| 12626 |
|
|
Total REAL time to PAR completion: 10 secs
|
| 12627 |
|
|
Total CPU time to PAR completion: 10 secs
|
| 12628 |
|
|
|
| 12629 |
|
|
Peak Memory Usage: 93 MB
|
| 12630 |
|
|
|
| 12631 |
|
|
Placer: Not run.
|
| 12632 |
|
|
Routing: Completed - No errors found.
|
| 12633 |
|
|
Timing: Completed - No errors found.
|
| 12634 |
|
|
|
| 12635 |
|
|
Number of error messages: 0
|
| 12636 |
|
|
Number of warning messages: 4
|
| 12637 |
|
|
Number of info messages: 1
|
| 12638 |
|
|
|
| 12639 |
|
|
Writing design to file topbox.ncd
|
| 12640 |
|
|
|
| 12641 |
|
|
|
| 12642 |
|
|
|
| 12643 |
|
|
PAR done!
|
| 12644 |
|
|
|
| 12645 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 12646 |
|
|
|
| 12647 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 12648 |
|
|
C:/Xilinx71.
|
| 12649 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 12650 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 12651 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 12652 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 12653 |
|
|
ps (24.00 Mhz).
|
| 12654 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 12655 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 12656 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 12657 |
|
|
(210.04 Mhz).
|
| 12658 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 12659 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 12660 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 12661 |
|
|
ps (24.00 Mhz).
|
| 12662 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 12663 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 12664 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 12665 |
|
|
(210.04 Mhz).
|
| 12666 |
|
|
|
| 12667 |
|
|
Analysis completed Sun Sep 24 22:22:30 2006
|
| 12668 |
|
|
--------------------------------------------------------------------------------
|
| 12669 |
|
|
|
| 12670 |
|
|
Generating Report ...
|
| 12671 |
|
|
|
| 12672 |
|
|
Number of warnings: 4
|
| 12673 |
|
|
Total time: 2 secs
|
| 12674 |
|
|
|
| 12675 |
|
|
|
| 12676 |
|
|
|
| 12677 |
|
|
|
| 12678 |
|
|
|
| 12679 |
|
|
|
| 12680 |
|
|
|
| 12681 |
|
|
Started process "Generate Programming File".
|
| 12682 |
|
|
|
| 12683 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 12684 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 12685 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 12686 |
|
|
Interactive Data Sheet.
|
| 12687 |
|
|
|
| 12688 |
|
|
|
| 12689 |
|
|
Project Navigator Auto-Make Log File
|
| 12690 |
|
|
-------------------------------------
|
| 12691 |
|
|
|
| 12692 |
|
|
|
| 12693 |
|
|
|
| 12694 |
|
|
|
| 12695 |
|
|
|
| 12696 |
|
|
|
| 12697 |
|
|
|
| 12698 |
|
|
|
| 12699 |
|
|
|
| 12700 |
|
|
|
| 12701 |
|
|
Started process "Synthesize".
|
| 12702 |
|
|
|
| 12703 |
|
|
|
| 12704 |
|
|
=========================================================================
|
| 12705 |
|
|
* HDL Compilation *
|
| 12706 |
|
|
=========================================================================
|
| 12707 |
|
|
Compiling verilog file "io.v"
|
| 12708 |
|
|
Module compiled
|
| 12709 |
|
|
Module compiled
|
| 12710 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 12711 |
|
|
Module compiled
|
| 12712 |
|
|
Compiling verilog file "misc.v"
|
| 12713 |
|
|
Module compiled
|
| 12714 |
|
|
Module compiled
|
| 12715 |
|
|
Module compiled
|
| 12716 |
|
|
Module compiled
|
| 12717 |
|
|
Module compiled
|
| 12718 |
|
|
Module compiled
|
| 12719 |
|
|
Compiling verilog file "alu.v"
|
| 12720 |
|
|
Module compiled
|
| 12721 |
|
|
Compiling verilog file "switchsync.v"
|
| 12722 |
|
|
Module compiled
|
| 12723 |
|
|
Compiling verilog file "jkff.v"
|
| 12724 |
|
|
Module compiled
|
| 12725 |
|
|
Compiling verilog file "control.v"
|
| 12726 |
|
|
Module compiled
|
| 12727 |
|
|
Module compiled
|
| 12728 |
|
|
Compiling verilog file "maindcm.v"
|
| 12729 |
|
|
Module compiled
|
| 12730 |
|
|
Compiling verilog file "idecode.v"
|
| 12731 |
|
|
Module compiled
|
| 12732 |
|
|
Compiling verilog file "top.v"
|
| 12733 |
|
|
ERROR:HDLCompilers:26 - "top.v" line 75 unexpected token: 'writeflag'
|
| 12734 |
|
|
ERROR:HDLCompilers:28 - "top.v" line 100 'writeflag' has not been declared
|
| 12735 |
|
|
ERROR:HDLCompilers:28 - "top.v" line 107 'writeflag' has not been declared
|
| 12736 |
|
|
ERROR:HDLCompilers:28 - "top.v" line 114 'writeflag' has not been declared
|
| 12737 |
|
|
ERROR:HDLCompilers:28 - "top.v" line 115 'writecf' has not been declared
|
| 12738 |
|
|
ERROR:HDLCompilers:28 - "top.v" line 230 'writecf' has not been declared
|
| 12739 |
|
|
ERROR:HDLCompilers:28 - "top.v" line 333 'writeflag' has not been declared
|
| 12740 |
|
|
Module compiled
|
| 12741 |
|
|
Compiling verilog file "rcvr.v"
|
| 12742 |
|
|
Module compiled
|
| 12743 |
|
|
Compiling verilog file "txmit.v"
|
| 12744 |
|
|
Module compiled
|
| 12745 |
|
|
Compiling verilog file "uart.v"
|
| 12746 |
|
|
Module compiled
|
| 12747 |
|
|
Compiling verilog file "topbox.v"
|
| 12748 |
|
|
Module compiled
|
| 12749 |
|
|
Analysis of file <"topbox.prj"> failed.
|
| 12750 |
|
|
-->
|
| 12751 |
|
|
|
| 12752 |
|
|
Total memory usage is 75092 kilobytes
|
| 12753 |
|
|
|
| 12754 |
|
|
Number of errors : 7 ( 0 filtered)
|
| 12755 |
|
|
Number of warnings : 0 ( 0 filtered)
|
| 12756 |
|
|
Number of infos : 0 ( 0 filtered)
|
| 12757 |
|
|
|
| 12758 |
|
|
ERROR: XST failed
|
| 12759 |
|
|
Process "Synthesize" did not complete.
|
| 12760 |
|
|
|
| 12761 |
|
|
|
| 12762 |
|
|
Project Navigator Auto-Make Log File
|
| 12763 |
|
|
-------------------------------------
|
| 12764 |
|
|
|
| 12765 |
|
|
|
| 12766 |
|
|
|
| 12767 |
|
|
|
| 12768 |
|
|
|
| 12769 |
|
|
|
| 12770 |
|
|
|
| 12771 |
|
|
|
| 12772 |
|
|
|
| 12773 |
|
|
|
| 12774 |
|
|
Started process "Synthesize".
|
| 12775 |
|
|
|
| 12776 |
|
|
|
| 12777 |
|
|
=========================================================================
|
| 12778 |
|
|
* HDL Compilation *
|
| 12779 |
|
|
=========================================================================
|
| 12780 |
|
|
Compiling verilog file "io.v"
|
| 12781 |
|
|
Module compiled
|
| 12782 |
|
|
Module compiled
|
| 12783 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 12784 |
|
|
Module compiled
|
| 12785 |
|
|
Compiling verilog file "misc.v"
|
| 12786 |
|
|
Module compiled
|
| 12787 |
|
|
Module compiled
|
| 12788 |
|
|
Module compiled
|
| 12789 |
|
|
Module compiled
|
| 12790 |
|
|
Module compiled
|
| 12791 |
|
|
Module compiled
|
| 12792 |
|
|
Compiling verilog file "alu.v"
|
| 12793 |
|
|
Module compiled
|
| 12794 |
|
|
Compiling verilog file "switchsync.v"
|
| 12795 |
|
|
Module compiled
|
| 12796 |
|
|
Compiling verilog file "jkff.v"
|
| 12797 |
|
|
Module compiled
|
| 12798 |
|
|
Compiling verilog file "control.v"
|
| 12799 |
|
|
Module compiled
|
| 12800 |
|
|
Module compiled
|
| 12801 |
|
|
Compiling verilog file "maindcm.v"
|
| 12802 |
|
|
Module compiled
|
| 12803 |
|
|
Compiling verilog file "idecode.v"
|
| 12804 |
|
|
Module compiled
|
| 12805 |
|
|
Compiling verilog file "top.v"
|
| 12806 |
|
|
Module compiled
|
| 12807 |
|
|
Compiling verilog file "rcvr.v"
|
| 12808 |
|
|
Module compiled
|
| 12809 |
|
|
Compiling verilog file "txmit.v"
|
| 12810 |
|
|
Module compiled
|
| 12811 |
|
|
Compiling verilog file "uart.v"
|
| 12812 |
|
|
Module compiled
|
| 12813 |
|
|
Compiling verilog file "topbox.v"
|
| 12814 |
|
|
Module compiled
|
| 12815 |
|
|
No errors in compilation
|
| 12816 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 12817 |
|
|
|
| 12818 |
|
|
|
| 12819 |
|
|
=========================================================================
|
| 12820 |
|
|
* HDL Analysis *
|
| 12821 |
|
|
=========================================================================
|
| 12822 |
|
|
Analyzing top module .
|
| 12823 |
|
|
Module is correct for synthesis.
|
| 12824 |
|
|
|
| 12825 |
|
|
Set property "resynthesize = true" for unit .
|
| 12826 |
|
|
Analyzing module .
|
| 12827 |
|
|
Module is correct for synthesis.
|
| 12828 |
|
|
|
| 12829 |
|
|
Analyzing module .
|
| 12830 |
|
|
pClockFrequency = 50
|
| 12831 |
|
|
pRefreshFrequency = 100
|
| 12832 |
|
|
pUpperLimit = 125000
|
| 12833 |
|
|
pDividerCounterBits = 24
|
| 12834 |
|
|
Module is correct for synthesis.
|
| 12835 |
|
|
|
| 12836 |
|
|
Analyzing module .
|
| 12837 |
|
|
pInitialValue = 0
|
| 12838 |
|
|
pTimerWidth = 19
|
| 12839 |
|
|
pInitialTimerValue = 500000
|
| 12840 |
|
|
Module is correct for synthesis.
|
| 12841 |
|
|
|
| 12842 |
|
|
Analyzing module .
|
| 12843 |
|
|
Module is correct for synthesis.
|
| 12844 |
|
|
|
| 12845 |
|
|
Analyzing module .
|
| 12846 |
|
|
SIZE = 16
|
| 12847 |
|
|
Module is correct for synthesis.
|
| 12848 |
|
|
|
| 12849 |
|
|
Analyzing module .
|
| 12850 |
|
|
Module is correct for synthesis.
|
| 12851 |
|
|
|
| 12852 |
|
|
Analyzing module .
|
| 12853 |
|
|
SIZE = 12
|
| 12854 |
|
|
Module is correct for synthesis.
|
| 12855 |
|
|
|
| 12856 |
|
|
Analyzing module .
|
| 12857 |
|
|
Module is correct for synthesis.
|
| 12858 |
|
|
|
| 12859 |
|
|
Analyzing module .
|
| 12860 |
|
|
VALUE = 0000000000000001
|
| 12861 |
|
|
Module is correct for synthesis.
|
| 12862 |
|
|
|
| 12863 |
|
|
Analyzing module .
|
| 12864 |
|
|
Module is correct for synthesis.
|
| 12865 |
|
|
|
| 12866 |
|
|
Analyzing module .
|
| 12867 |
|
|
VALUE = 1111111111111111
|
| 12868 |
|
|
Module is correct for synthesis.
|
| 12869 |
|
|
|
| 12870 |
|
|
Analyzing module .
|
| 12871 |
|
|
Module is correct for synthesis.
|
| 12872 |
|
|
|
| 12873 |
|
|
Analyzing module .
|
| 12874 |
|
|
VALUE = 0000000000000000
|
| 12875 |
|
|
Module is correct for synthesis.
|
| 12876 |
|
|
|
| 12877 |
|
|
Analyzing module .
|
| 12878 |
|
|
Module is correct for synthesis.
|
| 12879 |
|
|
|
| 12880 |
|
|
Analyzing module .
|
| 12881 |
|
|
Module is correct for synthesis.
|
| 12882 |
|
|
|
| 12883 |
|
|
Analyzing module .
|
| 12884 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 12885 |
|
|
Module is correct for synthesis.
|
| 12886 |
|
|
|
| 12887 |
|
|
Analyzing module .
|
| 12888 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 12889 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 12890 |
|
|
Module is correct for synthesis.
|
| 12891 |
|
|
|
| 12892 |
|
|
Analyzing module .
|
| 12893 |
|
|
Module is correct for synthesis.
|
| 12894 |
|
|
|
| 12895 |
|
|
Analyzing module .
|
| 12896 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12897 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12898 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12899 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12900 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12901 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12902 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12903 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12904 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12905 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12906 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12907 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12908 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12909 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 12910 |
|
|
Module is correct for synthesis.
|
| 12911 |
|
|
|
| 12912 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 12913 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 12914 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 12915 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 12916 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 12917 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 12918 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 12919 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 12920 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 12921 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 12922 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 12923 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 12924 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 12925 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 12926 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 12927 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 12928 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 12929 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 12930 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 12931 |
|
|
Analyzing module .
|
| 12932 |
|
|
Module is correct for synthesis.
|
| 12933 |
|
|
|
| 12934 |
|
|
Analyzing module .
|
| 12935 |
|
|
XTAL_CLK = 35000000
|
| 12936 |
|
|
BAUD = 9600
|
| 12937 |
|
|
CLK_DIV = 113
|
| 12938 |
|
|
CW = 8
|
| 12939 |
|
|
Module is correct for synthesis.
|
| 12940 |
|
|
|
| 12941 |
|
|
Analyzing module .
|
| 12942 |
|
|
Module is correct for synthesis.
|
| 12943 |
|
|
|
| 12944 |
|
|
Analyzing module .
|
| 12945 |
|
|
Module is correct for synthesis.
|
| 12946 |
|
|
|
| 12947 |
|
|
|
| 12948 |
|
|
=========================================================================
|
| 12949 |
|
|
* HDL Synthesis *
|
| 12950 |
|
|
=========================================================================
|
| 12951 |
|
|
|
| 12952 |
|
|
Synthesizing Unit .
|
| 12953 |
|
|
Related source file is "txmit.v".
|
| 12954 |
|
|
Found 1-bit register for signal .
|
| 12955 |
|
|
Found 1-bit register for signal .
|
| 12956 |
|
|
Found 1-bit register for signal .
|
| 12957 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 12958 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 12959 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 12960 |
|
|
Found 1-bit register for signal .
|
| 12961 |
|
|
Found 1-bit register for signal .
|
| 12962 |
|
|
Found 4-bit up counter for signal .
|
| 12963 |
|
|
Found 4-bit up counter for signal .
|
| 12964 |
|
|
Found 8-bit register for signal .
|
| 12965 |
|
|
Found 8-bit register for signal .
|
| 12966 |
|
|
Summary:
|
| 12967 |
|
|
inferred 2 Counter(s).
|
| 12968 |
|
|
inferred 21 D-type flip-flop(s).
|
| 12969 |
|
|
inferred 2 Comparator(s).
|
| 12970 |
|
|
inferred 1 Multiplexer(s).
|
| 12971 |
|
|
Unit synthesized.
|
| 12972 |
|
|
|
| 12973 |
|
|
|
| 12974 |
|
|
Synthesizing Unit .
|
| 12975 |
|
|
Related source file is "rcvr.v".
|
| 12976 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 12977 |
|
|
Found 1-bit register for signal .
|
| 12978 |
|
|
Found 1-bit register for signal .
|
| 12979 |
|
|
Found 1-bit register for signal .
|
| 12980 |
|
|
Found 8-bit tristate buffer for signal .
|
| 12981 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 12982 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 12983 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 12984 |
|
|
Found 1-bit register for signal .
|
| 12985 |
|
|
Found 1-bit register for signal .
|
| 12986 |
|
|
Found 4-bit register for signal .
|
| 12987 |
|
|
Found 4-bit up counter for signal .
|
| 12988 |
|
|
Found 8-bit register for signal .
|
| 12989 |
|
|
Found 7-bit register for signal >.
|
| 12990 |
|
|
Found 1-bit register for signal .
|
| 12991 |
|
|
Found 1-bit register for signal .
|
| 12992 |
|
|
Summary:
|
| 12993 |
|
|
inferred 1 Counter(s).
|
| 12994 |
|
|
inferred 26 D-type flip-flop(s).
|
| 12995 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 12996 |
|
|
inferred 1 Comparator(s).
|
| 12997 |
|
|
inferred 1 Multiplexer(s).
|
| 12998 |
|
|
inferred 8 Tristate(s).
|
| 12999 |
|
|
Unit synthesized.
|
| 13000 |
|
|
|
| 13001 |
|
|
|
| 13002 |
|
|
Synthesizing Unit .
|
| 13003 |
|
|
Related source file is "jkff.v".
|
| 13004 |
|
|
Found 1-bit register for signal .
|
| 13005 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 13006 |
|
|
Summary:
|
| 13007 |
|
|
inferred 1 D-type flip-flop(s).
|
| 13008 |
|
|
inferred 1 Multiplexer(s).
|
| 13009 |
|
|
Unit synthesized.
|
| 13010 |
|
|
|
| 13011 |
|
|
|
| 13012 |
|
|
Synthesizing Unit .
|
| 13013 |
|
|
Related source file is "switchsync.v".
|
| 13014 |
|
|
Found 1-bit register for signal .
|
| 13015 |
|
|
Found 1-bit register for signal .
|
| 13016 |
|
|
Summary:
|
| 13017 |
|
|
inferred 2 D-type flip-flop(s).
|
| 13018 |
|
|
Unit synthesized.
|
| 13019 |
|
|
|
| 13020 |
|
|
|
| 13021 |
|
|
Synthesizing Unit .
|
| 13022 |
|
|
Related source file is "maindcm.v".
|
| 13023 |
|
|
Unit synthesized.
|
| 13024 |
|
|
|
| 13025 |
|
|
|
| 13026 |
|
|
Synthesizing Unit .
|
| 13027 |
|
|
Related source file is "control.v".
|
| 13028 |
|
|
Found 1-bit register for signal .
|
| 13029 |
|
|
Found 1-bit register for signal .
|
| 13030 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 13031 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 13032 |
|
|
Found 3-bit up counter for signal .
|
| 13033 |
|
|
Summary:
|
| 13034 |
|
|
inferred 1 Counter(s).
|
| 13035 |
|
|
inferred 2 D-type flip-flop(s).
|
| 13036 |
|
|
inferred 2 Multiplexer(s).
|
| 13037 |
|
|
Unit synthesized.
|
| 13038 |
|
|
|
| 13039 |
|
|
|
| 13040 |
|
|
Synthesizing Unit .
|
| 13041 |
|
|
Related source file is "misc.v".
|
| 13042 |
|
|
Found 16-bit tristate buffer for signal .
|
| 13043 |
|
|
Summary:
|
| 13044 |
|
|
inferred 16 Tristate(s).
|
| 13045 |
|
|
Unit synthesized.
|
| 13046 |
|
|
|
| 13047 |
|
|
|
| 13048 |
|
|
Synthesizing Unit .
|
| 13049 |
|
|
Related source file is "misc.v".
|
| 13050 |
|
|
Found 16-bit tristate buffer for signal .
|
| 13051 |
|
|
Summary:
|
| 13052 |
|
|
inferred 16 Tristate(s).
|
| 13053 |
|
|
Unit synthesized.
|
| 13054 |
|
|
|
| 13055 |
|
|
|
| 13056 |
|
|
Synthesizing Unit .
|
| 13057 |
|
|
Related source file is "misc.v".
|
| 13058 |
|
|
Found 16-bit tristate buffer for signal .
|
| 13059 |
|
|
Summary:
|
| 13060 |
|
|
inferred 16 Tristate(s).
|
| 13061 |
|
|
Unit synthesized.
|
| 13062 |
|
|
|
| 13063 |
|
|
|
| 13064 |
|
|
Synthesizing Unit .
|
| 13065 |
|
|
Related source file is "misc.v".
|
| 13066 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 13067 |
|
|
Found 16-bit tristate buffer for signal .
|
| 13068 |
|
|
Found 12-bit register for signal .
|
| 13069 |
|
|
Summary:
|
| 13070 |
|
|
inferred 12 D-type flip-flop(s).
|
| 13071 |
|
|
inferred 16 Tristate(s).
|
| 13072 |
|
|
Unit synthesized.
|
| 13073 |
|
|
|
| 13074 |
|
|
|
| 13075 |
|
|
Synthesizing Unit .
|
| 13076 |
|
|
Related source file is "idecode.v".
|
| 13077 |
|
|
Unit synthesized.
|
| 13078 |
|
|
|
| 13079 |
|
|
|
| 13080 |
|
|
Synthesizing Unit .
|
| 13081 |
|
|
Related source file is "control.v".
|
| 13082 |
|
|
Unit synthesized.
|
| 13083 |
|
|
|
| 13084 |
|
|
|
| 13085 |
|
|
Synthesizing Unit .
|
| 13086 |
|
|
Related source file is "alu.v".
|
| 13087 |
|
|
Found 16-bit tristate buffer for signal .
|
| 13088 |
|
|
Found 17-bit subtractor for signal <$AUX_108>.
|
| 13089 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 13090 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 13091 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 13092 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 13093 |
|
|
Summary:
|
| 13094 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 13095 |
|
|
inferred 16 Tristate(s).
|
| 13096 |
|
|
Unit synthesized.
|
| 13097 |
|
|
|
| 13098 |
|
|
|
| 13099 |
|
|
Synthesizing Unit .
|
| 13100 |
|
|
Related source file is "misc.v".
|
| 13101 |
|
|
Unit synthesized.
|
| 13102 |
|
|
|
| 13103 |
|
|
|
| 13104 |
|
|
Synthesizing Unit .
|
| 13105 |
|
|
Related source file is "misc.v".
|
| 13106 |
|
|
Unit synthesized.
|
| 13107 |
|
|
|
| 13108 |
|
|
|
| 13109 |
|
|
Synthesizing Unit .
|
| 13110 |
|
|
Related source file is "misc.v".
|
| 13111 |
|
|
Unit synthesized.
|
| 13112 |
|
|
|
| 13113 |
|
|
|
| 13114 |
|
|
Synthesizing Unit .
|
| 13115 |
|
|
Related source file is "misc.v".
|
| 13116 |
|
|
Unit synthesized.
|
| 13117 |
|
|
|
| 13118 |
|
|
|
| 13119 |
|
|
Synthesizing Unit .
|
| 13120 |
|
|
Related source file is "misc.v".
|
| 13121 |
|
|
Found 16-bit tristate buffer for signal .
|
| 13122 |
|
|
Found 16-bit register for signal .
|
| 13123 |
|
|
Summary:
|
| 13124 |
|
|
inferred 16 D-type flip-flop(s).
|
| 13125 |
|
|
inferred 16 Tristate(s).
|
| 13126 |
|
|
Unit synthesized.
|
| 13127 |
|
|
|
| 13128 |
|
|
|
| 13129 |
|
|
Synthesizing Unit .
|
| 13130 |
|
|
Related source file is "io.v".
|
| 13131 |
|
|
Found 1-bit register for signal .
|
| 13132 |
|
|
Found 1-bit register for signal .
|
| 13133 |
|
|
Found 1-bit register for signal .
|
| 13134 |
|
|
Found 1-bit register for signal .
|
| 13135 |
|
|
Found 1-bit register for signal .
|
| 13136 |
|
|
Found 1-bit register for signal .
|
| 13137 |
|
|
Found 19-bit down counter for signal .
|
| 13138 |
|
|
Found 1-bit register for signal .
|
| 13139 |
|
|
Found 1-bit xor2 for signal .
|
| 13140 |
|
|
Summary:
|
| 13141 |
|
|
inferred 1 Counter(s).
|
| 13142 |
|
|
inferred 7 D-type flip-flop(s).
|
| 13143 |
|
|
Unit synthesized.
|
| 13144 |
|
|
|
| 13145 |
|
|
|
| 13146 |
|
|
Synthesizing Unit .
|
| 13147 |
|
|
Related source file is "io.v".
|
| 13148 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 13149 |
|
|
Found 1-bit register for signal .
|
| 13150 |
|
|
Found 1-bit register for signal .
|
| 13151 |
|
|
Found 1-bit register for signal .
|
| 13152 |
|
|
Found 1-bit register for signal .
|
| 13153 |
|
|
Found 1-bit register for signal .
|
| 13154 |
|
|
Found 1-bit register for signal .
|
| 13155 |
|
|
Found 1-bit register for signal .
|
| 13156 |
|
|
Found 1-bit register for signal .
|
| 13157 |
|
|
Found 1-bit register for signal .
|
| 13158 |
|
|
Found 1-bit register for signal .
|
| 13159 |
|
|
Found 1-bit register for signal .
|
| 13160 |
|
|
Found 1-bit register for signal .
|
| 13161 |
|
|
Found 24-bit up counter for signal .
|
| 13162 |
|
|
Found 1-of-4 decoder for signal .
|
| 13163 |
|
|
Found 2-bit down counter for signal .
|
| 13164 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 13165 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 13166 |
|
|
Summary:
|
| 13167 |
|
|
inferred 1 ROM(s).
|
| 13168 |
|
|
inferred 2 Counter(s).
|
| 13169 |
|
|
inferred 12 D-type flip-flop(s).
|
| 13170 |
|
|
inferred 9 Multiplexer(s).
|
| 13171 |
|
|
inferred 1 Decoder(s).
|
| 13172 |
|
|
Unit synthesized.
|
| 13173 |
|
|
|
| 13174 |
|
|
|
| 13175 |
|
|
Synthesizing Unit .
|
| 13176 |
|
|
Related source file is "uart.v".
|
| 13177 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 13178 |
|
|
Found 1-bit register for signal .
|
| 13179 |
|
|
Found 8-bit up counter for signal .
|
| 13180 |
|
|
Found 1-bit register for signal .
|
| 13181 |
|
|
Summary:
|
| 13182 |
|
|
inferred 1 Counter(s).
|
| 13183 |
|
|
inferred 2 D-type flip-flop(s).
|
| 13184 |
|
|
inferred 1 Multiplexer(s).
|
| 13185 |
|
|
Unit synthesized.
|
| 13186 |
|
|
|
| 13187 |
|
|
|
| 13188 |
|
|
Synthesizing Unit .
|
| 13189 |
|
|
Related source file is "top.v".
|
| 13190 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 13191 |
|
|
Found 16-bit tristate buffer for signal .
|
| 13192 |
|
|
Found 1-bit register for signal .
|
| 13193 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 13194 |
|
|
Found 16-bit tristate buffer for signal .
|
| 13195 |
|
|
Found 1-bit register for signal .
|
| 13196 |
|
|
Found 1-bit register for signal .
|
| 13197 |
|
|
Found 1-bit register for signal .
|
| 13198 |
|
|
Summary:
|
| 13199 |
|
|
inferred 4 D-type flip-flop(s).
|
| 13200 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 13201 |
|
|
inferred 96 Tristate(s).
|
| 13202 |
|
|
Unit synthesized.
|
| 13203 |
|
|
|
| 13204 |
|
|
|
| 13205 |
|
|
Synthesizing Unit .
|
| 13206 |
|
|
Related source file is "FrontPanel.v".
|
| 13207 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 13208 |
|
|
Found finite state machine for signal .
|
| 13209 |
|
|
-----------------------------------------------------------------------
|
| 13210 |
|
|
| States | 6 |
|
| 13211 |
|
|
| Transitions | 6 |
|
| 13212 |
|
|
| Inputs | 0 |
|
| 13213 |
|
|
| Outputs | 12 |
|
| 13214 |
|
|
| Clock | clockin (rising_edge) |
|
| 13215 |
|
|
| Clock enable | select (positive) |
|
| 13216 |
|
|
| Reset | clear (positive) |
|
| 13217 |
|
|
| Reset type | synchronous |
|
| 13218 |
|
|
| Reset State | 000001 |
|
| 13219 |
|
|
| Encoding | automatic |
|
| 13220 |
|
|
| Implementation | LUT |
|
| 13221 |
|
|
-----------------------------------------------------------------------
|
| 13222 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 13223 |
|
|
Found 4-bit register for signal .
|
| 13224 |
|
|
Found 16-bit register for signal .
|
| 13225 |
|
|
Summary:
|
| 13226 |
|
|
inferred 1 Finite State Machine(s).
|
| 13227 |
|
|
inferred 16 D-type flip-flop(s).
|
| 13228 |
|
|
inferred 16 Multiplexer(s).
|
| 13229 |
|
|
Unit synthesized.
|
| 13230 |
|
|
|
| 13231 |
|
|
|
| 13232 |
|
|
Synthesizing Unit .
|
| 13233 |
|
|
Related source file is "topbox.v".
|
| 13234 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 13235 |
|
|
Found 16-bit tristate buffer for signal .
|
| 13236 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 13237 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 13238 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 13239 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 13240 |
|
|
Found 4-bit register for signal .
|
| 13241 |
|
|
Found 1-bit register for signal .
|
| 13242 |
|
|
Found 1-bit register for signal .
|
| 13243 |
|
|
Found 16-bit register for signal .
|
| 13244 |
|
|
Summary:
|
| 13245 |
|
|
inferred 22 D-type flip-flop(s).
|
| 13246 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 13247 |
|
|
inferred 6 Multiplexer(s).
|
| 13248 |
|
|
inferred 48 Tristate(s).
|
| 13249 |
|
|
Unit synthesized.
|
| 13250 |
|
|
|
| 13251 |
|
|
|
| 13252 |
|
|
=========================================================================
|
| 13253 |
|
|
* Advanced HDL Synthesis *
|
| 13254 |
|
|
=========================================================================
|
| 13255 |
|
|
|
| 13256 |
|
|
Advanced RAM inference ...
|
| 13257 |
|
|
Advanced multiplier inference ...
|
| 13258 |
|
|
Advanced Registered AddSub inference ...
|
| 13259 |
|
|
Analyzing FSM for best encoding.
|
| 13260 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 13261 |
|
|
--------------------
|
| 13262 |
|
|
State | Encoding
|
| 13263 |
|
|
--------------------
|
| 13264 |
|
|
000001 | 100000
|
| 13265 |
|
|
000010 | 010000
|
| 13266 |
|
|
000100 | 001000
|
| 13267 |
|
|
001000 | 000100
|
| 13268 |
|
|
010000 | 000010
|
| 13269 |
|
|
100000 | 000001
|
| 13270 |
|
|
--------------------
|
| 13271 |
|
|
Dynamic shift register inference ...
|
| 13272 |
|
|
|
| 13273 |
|
|
=========================================================================
|
| 13274 |
|
|
HDL Synthesis Report
|
| 13275 |
|
|
|
| 13276 |
|
|
Macro Statistics
|
| 13277 |
|
|
# FSMs : 1
|
| 13278 |
|
|
# ROMs : 1
|
| 13279 |
|
|
16x7-bit ROM : 1
|
| 13280 |
|
|
# Adders/Subtractors : 5
|
| 13281 |
|
|
12-bit adder carry out : 1
|
| 13282 |
|
|
16-bit adder carry out : 1
|
| 13283 |
|
|
17-bit subtractor : 1
|
| 13284 |
|
|
4-bit adder : 2
|
| 13285 |
|
|
# Counters : 10
|
| 13286 |
|
|
19-bit down counter : 3
|
| 13287 |
|
|
2-bit down counter : 1
|
| 13288 |
|
|
24-bit up counter : 1
|
| 13289 |
|
|
3-bit up counter : 1
|
| 13290 |
|
|
4-bit up counter : 3
|
| 13291 |
|
|
8-bit up counter : 1
|
| 13292 |
|
|
# Registers : 138
|
| 13293 |
|
|
1-bit register : 125
|
| 13294 |
|
|
12-bit register : 4
|
| 13295 |
|
|
16-bit register : 4
|
| 13296 |
|
|
4-bit register : 3
|
| 13297 |
|
|
8-bit register : 2
|
| 13298 |
|
|
# Comparators : 3
|
| 13299 |
|
|
4-bit comparator greater : 2
|
| 13300 |
|
|
4-bit comparator less : 1
|
| 13301 |
|
|
# Multiplexers : 15
|
| 13302 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 13303 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 13304 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 13305 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 13306 |
|
|
# Decoders : 1
|
| 13307 |
|
|
1-of-4 decoder : 1
|
| 13308 |
|
|
# Tristates : 97
|
| 13309 |
|
|
1-bit tristate buffer : 80
|
| 13310 |
|
|
16-bit tristate buffer : 16
|
| 13311 |
|
|
8-bit tristate buffer : 1
|
| 13312 |
|
|
# Xors : 6
|
| 13313 |
|
|
1-bit xor2 : 5
|
| 13314 |
|
|
16-bit xor2 : 1
|
| 13315 |
|
|
|
| 13316 |
|
|
=========================================================================
|
| 13317 |
|
|
|
| 13318 |
|
|
=========================================================================
|
| 13319 |
|
|
* Low Level Synthesis *
|
| 13320 |
|
|
=========================================================================
|
| 13321 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 13322 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 13323 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 13324 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 13325 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 13326 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 13327 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 13328 |
|
|
|
| 13329 |
|
|
Optimizing unit ...
|
| 13330 |
|
|
|
| 13331 |
|
|
Optimizing unit ...
|
| 13332 |
|
|
|
| 13333 |
|
|
Optimizing unit ...
|
| 13334 |
|
|
|
| 13335 |
|
|
Optimizing unit ...
|
| 13336 |
|
|
|
| 13337 |
|
|
Optimizing unit ...
|
| 13338 |
|
|
|
| 13339 |
|
|
Optimizing unit ...
|
| 13340 |
|
|
|
| 13341 |
|
|
Optimizing unit ...
|
| 13342 |
|
|
|
| 13343 |
|
|
Optimizing unit ...
|
| 13344 |
|
|
|
| 13345 |
|
|
Optimizing unit ...
|
| 13346 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 13347 |
|
|
|
| 13348 |
|
|
Mapping all equations...
|
| 13349 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 13350 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 13351 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 13352 |
|
|
Building and optimizing final netlist ...
|
| 13353 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
|
| 13354 |
|
|
Forward register balancing over CPU/decoder/opdec78 of flipflops :
|
| 13355 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 13356 |
|
|
Forward register balancing over CPU/decoder/opxor1 of flipflops :
|
| 13357 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
|
| 13358 |
|
|
Forward register balancing over CPU/decoder/opand1 of flipflops :
|
| 13359 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 13360 |
|
|
Forward register balancing over CPU/decoder/opior1 of flipflops :
|
| 13361 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
|
| 13362 |
|
|
Forward register balancing over CPU/decoder/oplda1 of flipflops :
|
| 13363 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
|
| 13364 |
|
|
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
|
| 13365 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 13366 |
|
|
Forward register balancing over Ker571 of flipflops :
|
| 13367 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 13368 |
|
|
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
|
| 13369 |
|
|
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 13370 |
|
|
Forward register balancing over Ker2101 of flipflops :
|
| 13371 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 13372 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
|
| 13373 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
|
| 13374 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
|
| 13375 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 13376 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV35_SW0_SW0 of flipflops :
|
| 13377 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
|
| 13378 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV35_SW0_SW1 of flipflops :
|
| 13379 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 13380 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
|
| 13381 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
|
| 13382 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV23 of flipflops :
|
| 13383 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 13384 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
|
| 13385 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 13386 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
|
| 13387 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 13388 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
|
| 13389 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
|
| 13390 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
|
| 13391 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
|
| 13392 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
|
| 13393 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 13394 |
|
|
Forward register balancing over CPU/decoder/opframe121 of flipflops :
|
| 13395 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_4.
|
| 13396 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
|
| 13397 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 13398 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
|
| 13399 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 13400 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
|
| 13401 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 13402 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
|
| 13403 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 13404 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
|
| 13405 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 13406 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV8_SW0_SW0 of flipflops :
|
| 13407 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
|
| 13408 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
|
| 13409 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 13410 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
|
| 13411 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4.
|
| 13412 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
|
| 13413 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 13414 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW5 of flipflops :
|
| 13415 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 13416 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
|
| 13417 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
|
| 13418 |
|
|
Forward register balancing over Ker2161_SW0 of flipflops :
|
| 13419 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 13420 |
|
|
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
|
| 13421 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 13422 |
|
|
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
|
| 13423 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 13424 |
|
|
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
|
| 13425 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 13426 |
|
|
Forward register balancing over CPU/decoder/opframe14 of flipflops :
|
| 13427 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_2.
|
| 13428 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
|
| 13429 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 13430 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
|
| 13431 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 13432 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
|
| 13433 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 13434 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
|
| 13435 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 13436 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
|
| 13437 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
|
| 13438 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
|
| 13439 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 13440 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
|
| 13441 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 13442 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW4 of flipflops :
|
| 13443 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 13444 |
|
|
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
|
| 13445 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
|
| 13446 |
|
|
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
|
| 13447 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 13448 |
|
|
Forward register balancing over Ker161_SW0 of flipflops :
|
| 13449 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_6.
|
| 13450 |
|
|
Forward register balancing over CPU/decoder/opdec74 of flipflops :
|
| 13451 |
|
|
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
|
| 13452 |
|
|
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
|
| 13453 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 13454 |
|
|
Forward register balancing over Ker2131_SW1_SW0 of flipflops :
|
| 13455 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 13456 |
|
|
Forward register balancing over CPU/msend9 of flipflops :
|
| 13457 |
|
|
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
|
| 13458 |
|
|
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
|
| 13459 |
|
|
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
|
| 13460 |
|
|
Forward register balancing over CPU/decoder/opadd1 of flipflops :
|
| 13461 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 13462 |
|
|
Forward register balancing over CPU/decoder/opdec41 of flipflops :
|
| 13463 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW0_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
|
| 13464 |
|
|
Forward register balancing over CPU/decoder/opinc41 of flipflops :
|
| 13465 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW4_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
|
| 13466 |
|
|
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
|
| 13467 |
|
|
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 13468 |
|
|
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
|
| 13469 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 13470 |
|
|
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
|
| 13471 |
|
|
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 13472 |
|
|
Forward register balancing over Ker201_SW0 of flipflops :
|
| 13473 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
|
| 13474 |
|
|
Forward register balancing over CPU/decoder/opdec714 of flipflops :
|
| 13475 |
|
|
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
|
| 13476 |
|
|
Register equivalent to has been removed
|
| 13477 |
|
|
Register equivalent to has been removed
|
| 13478 |
|
|
Register equivalent to has been removed
|
| 13479 |
|
|
Register equivalent to has been removed
|
| 13480 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
|
| 13481 |
|
|
FlipFlop CPU/ctl/sim/F1_FRB has been replicated 3 time(s)
|
| 13482 |
|
|
FlipFlop CPU/ctl/sim/counter_0 has been replicated 3 time(s)
|
| 13483 |
|
|
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
|
| 13484 |
|
|
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
|
| 13485 |
|
|
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
|
| 13486 |
|
|
FlipFlop loadnow has been replicated 2 time(s)
|
| 13487 |
|
|
|
| 13488 |
|
|
=========================================================================
|
| 13489 |
|
|
* Final Report *
|
| 13490 |
|
|
=========================================================================
|
| 13491 |
|
|
|
| 13492 |
|
|
Device utilization summary:
|
| 13493 |
|
|
---------------------------
|
| 13494 |
|
|
|
| 13495 |
|
|
Selected Device : 3s200ft256-4
|
| 13496 |
|
|
|
| 13497 |
|
|
Number of Slices: 615 out of 1920 32%
|
| 13498 |
|
|
Number of Slice Flip Flops: 436 out of 3840 11%
|
| 13499 |
|
|
Number of 4 input LUTs: 1084 out of 3840 28%
|
| 13500 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 13501 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 13502 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 13503 |
|
|
|
| 13504 |
|
|
|
| 13505 |
|
|
=========================================================================
|
| 13506 |
|
|
TIMING REPORT
|
| 13507 |
|
|
|
| 13508 |
|
|
|
| 13509 |
|
|
Clock Information:
|
| 13510 |
|
|
------------------
|
| 13511 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 13512 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 13513 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 13514 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 436 |
|
| 13515 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 13516 |
|
|
|
| 13517 |
|
|
Timing Summary:
|
| 13518 |
|
|
---------------
|
| 13519 |
|
|
Speed Grade: -4
|
| 13520 |
|
|
|
| 13521 |
|
|
Minimum period: 13.600ns (Maximum Frequency: 73.531MHz)
|
| 13522 |
|
|
Minimum input arrival time before clock: 11.144ns
|
| 13523 |
|
|
Maximum output required time after clock: 23.245ns
|
| 13524 |
|
|
Maximum combinational path delay: 15.352ns
|
| 13525 |
|
|
|
| 13526 |
|
|
=========================================================================
|
| 13527 |
|
|
|
| 13528 |
|
|
|
| 13529 |
|
|
|
| 13530 |
|
|
|
| 13531 |
|
|
Started process "Translate".
|
| 13532 |
|
|
|
| 13533 |
|
|
|
| 13534 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 13535 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 13536 |
|
|
|
| 13537 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 13538 |
|
|
|
| 13539 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 13540 |
|
|
|
| 13541 |
|
|
Checking timing specifications ...
|
| 13542 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 13543 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 13544 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 13545 |
|
|
20.408000 nS HIGH 50.000000%
|
| 13546 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 13547 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 13548 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 13549 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 13550 |
|
|
from this group.
|
| 13551 |
|
|
Checking expanded design ...
|
| 13552 |
|
|
|
| 13553 |
|
|
NGDBUILD Design Results Summary:
|
| 13554 |
|
|
Number of errors: 0
|
| 13555 |
|
|
Number of warnings: 1
|
| 13556 |
|
|
|
| 13557 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 13558 |
|
|
|
| 13559 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 13560 |
|
|
|
| 13561 |
|
|
NGDBUILD done.
|
| 13562 |
|
|
|
| 13563 |
|
|
|
| 13564 |
|
|
|
| 13565 |
|
|
|
| 13566 |
|
|
Started process "Map".
|
| 13567 |
|
|
|
| 13568 |
|
|
Using target part "3s200ft256-4".
|
| 13569 |
|
|
Mapping design into LUTs...
|
| 13570 |
|
|
Running directed packing...
|
| 13571 |
|
|
Running delay-based LUT packing...
|
| 13572 |
|
|
Running timing-driven packing...
|
| 13573 |
|
|
|
| 13574 |
|
|
Phase 1.1
|
| 13575 |
|
|
Phase 1.1 (Checksum:98d6b6) REAL time: 1 secs
|
| 13576 |
|
|
|
| 13577 |
|
|
Phase 2.31
|
| 13578 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
|
| 13579 |
|
|
|
| 13580 |
|
|
Phase 3.2
|
| 13581 |
|
|
.
|
| 13582 |
|
|
|
| 13583 |
|
|
|
| 13584 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
|
| 13585 |
|
|
|
| 13586 |
|
|
Phase 4.4
|
| 13587 |
|
|
...............
|
| 13588 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 4 secs
|
| 13589 |
|
|
|
| 13590 |
|
|
Phase 5.28
|
| 13591 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 4 secs
|
| 13592 |
|
|
|
| 13593 |
|
|
Phase 6.8
|
| 13594 |
|
|
.......................
|
| 13595 |
|
|
.......
|
| 13596 |
|
|
................................
|
| 13597 |
|
|
...............
|
| 13598 |
|
|
...............
|
| 13599 |
|
|
Phase 6.8 (Checksum:aab26f) REAL time: 10 secs
|
| 13600 |
|
|
|
| 13601 |
|
|
Phase 7.29
|
| 13602 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs
|
| 13603 |
|
|
|
| 13604 |
|
|
Phase 8.5
|
| 13605 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs
|
| 13606 |
|
|
|
| 13607 |
|
|
Phase 9.18
|
| 13608 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 19 secs
|
| 13609 |
|
|
|
| 13610 |
|
|
Phase 10.5
|
| 13611 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 19 secs
|
| 13612 |
|
|
|
| 13613 |
|
|
|
| 13614 |
|
|
Design Summary:
|
| 13615 |
|
|
Number of errors: 0
|
| 13616 |
|
|
Number of warnings: 11
|
| 13617 |
|
|
Logic Utilization:
|
| 13618 |
|
|
Number of Slice Flip Flops: 410 out of 3,840 10%
|
| 13619 |
|
|
Number of 4 input LUTs: 1,134 out of 3,840 29%
|
| 13620 |
|
|
Logic Distribution:
|
| 13621 |
|
|
Number of occupied Slices: 677 out of 1,920 35%
|
| 13622 |
|
|
Number of Slices containing only related logic: 677 out of 677 100%
|
| 13623 |
|
|
Number of Slices containing unrelated logic: 0 out of 677 0%
|
| 13624 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 13625 |
|
|
Total Number 4 input LUTs: 1,138 out of 3,840 29%
|
| 13626 |
|
|
Number used as logic: 1,134
|
| 13627 |
|
|
Number used as a route-thru: 4
|
| 13628 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 13629 |
|
|
IOB Flip Flops: 26
|
| 13630 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 13631 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 13632 |
|
|
|
| 13633 |
|
|
Total equivalent gate count for design: 18,168
|
| 13634 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 13635 |
|
|
Peak Memory Usage: 134 MB
|
| 13636 |
|
|
|
| 13637 |
|
|
Mapping completed.
|
| 13638 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 13639 |
|
|
|
| 13640 |
|
|
|
| 13641 |
|
|
|
| 13642 |
|
|
|
| 13643 |
|
|
Started process "Place & Route".
|
| 13644 |
|
|
|
| 13645 |
|
|
|
| 13646 |
|
|
|
| 13647 |
|
|
|
| 13648 |
|
|
Constraints file: topbox.pcf.
|
| 13649 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 13650 |
|
|
C:/Xilinx71.
|
| 13651 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 13652 |
|
|
|
| 13653 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 13654 |
|
|
Celsius)
|
| 13655 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 13656 |
|
|
|
| 13657 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 13658 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 13659 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 13660 |
|
|
ps (24.00 Mhz).
|
| 13661 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 13662 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 13663 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 13664 |
|
|
(210.04 Mhz).
|
| 13665 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 13666 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 13667 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 13668 |
|
|
ps (24.00 Mhz).
|
| 13669 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 13670 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 13671 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 13672 |
|
|
(210.04 Mhz).
|
| 13673 |
|
|
|
| 13674 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 13675 |
|
|
|
| 13676 |
|
|
|
| 13677 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 13678 |
|
|
achieve better performance.
|
| 13679 |
|
|
|
| 13680 |
|
|
Device Utilization Summary:
|
| 13681 |
|
|
|
| 13682 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 13683 |
|
|
Number of DCMs 1 out of 4 25%
|
| 13684 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 13685 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 13686 |
|
|
|
| 13687 |
|
|
Number of Slices 677 out of 1920 35%
|
| 13688 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 13689 |
|
|
|
| 13690 |
|
|
|
| 13691 |
|
|
|
| 13692 |
|
|
Overall effort level (-ol): High (set by user)
|
| 13693 |
|
|
Router effort level (-rl): High (set by user)
|
| 13694 |
|
|
|
| 13695 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 13696 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 13697 |
|
|
|
| 13698 |
|
|
Starting Router
|
| 13699 |
|
|
|
| 13700 |
|
|
Phase 1: 4894 unrouted; REAL time: 4 secs
|
| 13701 |
|
|
|
| 13702 |
|
|
Phase 2: 4536 unrouted; REAL time: 4 secs
|
| 13703 |
|
|
|
| 13704 |
|
|
Phase 3: 2116 unrouted; REAL time: 5 secs
|
| 13705 |
|
|
|
| 13706 |
|
|
Phase 4: 2116 unrouted; (0) REAL time: 5 secs
|
| 13707 |
|
|
|
| 13708 |
|
|
Phase 5: 2116 unrouted; (0) REAL time: 6 secs
|
| 13709 |
|
|
|
| 13710 |
|
|
Phase 6: 2116 unrouted; (0) REAL time: 6 secs
|
| 13711 |
|
|
|
| 13712 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 9 secs
|
| 13713 |
|
|
|
| 13714 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 10 secs
|
| 13715 |
|
|
|
| 13716 |
|
|
|
| 13717 |
|
|
Total REAL time to Router completion: 10 secs
|
| 13718 |
|
|
Total CPU time to Router completion: 10 secs
|
| 13719 |
|
|
|
| 13720 |
|
|
Generating "PAR" statistics.
|
| 13721 |
|
|
|
| 13722 |
|
|
**************************
|
| 13723 |
|
|
Generating Clock Report
|
| 13724 |
|
|
**************************
|
| 13725 |
|
|
|
| 13726 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 13727 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 13728 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 13729 |
|
|
| clk | BUFGMUX2| No | 338 | 0.041 | 1.051 |
|
| 13730 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 13731 |
|
|
|
| 13732 |
|
|
Timing Score: 0
|
| 13733 |
|
|
|
| 13734 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 13735 |
|
|
This may be due to a setup or hold violation.
|
| 13736 |
|
|
|
| 13737 |
|
|
--------------------------------------------------------------------------------
|
| 13738 |
|
|
Constraint | Requested | Actual | Logic
|
| 13739 |
|
|
| | | Levels
|
| 13740 |
|
|
--------------------------------------------------------------------------------
|
| 13741 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 13742 |
|
|
HIGH 50% | | |
|
| 13743 |
|
|
--------------------------------------------------------------------------------
|
| 13744 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 28.312ns | 6
|
| 13745 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 13746 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 13747 |
|
|
--------------------------------------------------------------------------------
|
| 13748 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 40.798ns | 9
|
| 13749 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 13750 |
|
|
HIGH 50% | | |
|
| 13751 |
|
|
--------------------------------------------------------------------------------
|
| 13752 |
|
|
|
| 13753 |
|
|
|
| 13754 |
|
|
All constraints were met.
|
| 13755 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 13756 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 13757 |
|
|
Generating Pad Report.
|
| 13758 |
|
|
|
| 13759 |
|
|
All signals are completely routed.
|
| 13760 |
|
|
|
| 13761 |
|
|
Total REAL time to PAR completion: 11 secs
|
| 13762 |
|
|
Total CPU time to PAR completion: 11 secs
|
| 13763 |
|
|
|
| 13764 |
|
|
Peak Memory Usage: 93 MB
|
| 13765 |
|
|
|
| 13766 |
|
|
Placer: Not run.
|
| 13767 |
|
|
Routing: Completed - No errors found.
|
| 13768 |
|
|
Timing: Completed - No errors found.
|
| 13769 |
|
|
|
| 13770 |
|
|
Number of error messages: 0
|
| 13771 |
|
|
Number of warning messages: 4
|
| 13772 |
|
|
Number of info messages: 1
|
| 13773 |
|
|
|
| 13774 |
|
|
Writing design to file topbox.ncd
|
| 13775 |
|
|
|
| 13776 |
|
|
|
| 13777 |
|
|
|
| 13778 |
|
|
PAR done!
|
| 13779 |
|
|
|
| 13780 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 13781 |
|
|
|
| 13782 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 13783 |
|
|
C:/Xilinx71.
|
| 13784 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 13785 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 13786 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 13787 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 13788 |
|
|
ps (24.00 Mhz).
|
| 13789 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 13790 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 13791 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 13792 |
|
|
(210.04 Mhz).
|
| 13793 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 13794 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 13795 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 13796 |
|
|
ps (24.00 Mhz).
|
| 13797 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 13798 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 13799 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 13800 |
|
|
(210.04 Mhz).
|
| 13801 |
|
|
|
| 13802 |
|
|
Analysis completed Fri Sep 29 19:25:05 2006
|
| 13803 |
|
|
--------------------------------------------------------------------------------
|
| 13804 |
|
|
|
| 13805 |
|
|
Generating Report ...
|
| 13806 |
|
|
|
| 13807 |
|
|
Number of warnings: 4
|
| 13808 |
|
|
Total time: 3 secs
|
| 13809 |
|
|
|
| 13810 |
|
|
|
| 13811 |
|
|
|
| 13812 |
|
|
|
| 13813 |
|
|
|
| 13814 |
|
|
|
| 13815 |
|
|
|
| 13816 |
|
|
Started process "Generate Programming File".
|
| 13817 |
|
|
|
| 13818 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 13819 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 13820 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 13821 |
|
|
Interactive Data Sheet.
|
| 13822 |
|
|
|
| 13823 |
|
|
|
| 13824 |
|
|
Project Navigator Auto-Make Log File
|
| 13825 |
|
|
-------------------------------------
|
| 13826 |
|
|
|
| 13827 |
|
|
|
| 13828 |
|
|
|
| 13829 |
|
|
|
| 13830 |
|
|
|
| 13831 |
|
|
|
| 13832 |
|
|
|
| 13833 |
|
|
|
| 13834 |
|
|
|
| 13835 |
|
|
|
| 13836 |
|
|
Started process "Synthesize".
|
| 13837 |
|
|
|
| 13838 |
|
|
|
| 13839 |
|
|
=========================================================================
|
| 13840 |
|
|
* HDL Compilation *
|
| 13841 |
|
|
=========================================================================
|
| 13842 |
|
|
Compiling verilog file "io.v"
|
| 13843 |
|
|
Module compiled
|
| 13844 |
|
|
Module compiled
|
| 13845 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 13846 |
|
|
Module compiled
|
| 13847 |
|
|
Compiling verilog file "misc.v"
|
| 13848 |
|
|
Module compiled
|
| 13849 |
|
|
Module compiled
|
| 13850 |
|
|
Module compiled
|
| 13851 |
|
|
Module compiled
|
| 13852 |
|
|
Module compiled
|
| 13853 |
|
|
Module compiled
|
| 13854 |
|
|
Compiling verilog file "alu.v"
|
| 13855 |
|
|
Module compiled
|
| 13856 |
|
|
Compiling verilog file "switchsync.v"
|
| 13857 |
|
|
Module compiled
|
| 13858 |
|
|
Compiling verilog file "jkff.v"
|
| 13859 |
|
|
Module compiled
|
| 13860 |
|
|
Compiling verilog file "control.v"
|
| 13861 |
|
|
Module compiled
|
| 13862 |
|
|
Module compiled
|
| 13863 |
|
|
Compiling verilog file "maindcm.v"
|
| 13864 |
|
|
Module compiled
|
| 13865 |
|
|
Compiling verilog file "idecode.v"
|
| 13866 |
|
|
Module compiled
|
| 13867 |
|
|
Compiling verilog file "top.v"
|
| 13868 |
|
|
Module compiled
|
| 13869 |
|
|
Compiling verilog file "rcvr.v"
|
| 13870 |
|
|
Module compiled
|
| 13871 |
|
|
Compiling verilog file "txmit.v"
|
| 13872 |
|
|
Module compiled
|
| 13873 |
|
|
Compiling verilog file "uart.v"
|
| 13874 |
|
|
Module compiled
|
| 13875 |
|
|
Compiling verilog file "topbox.v"
|
| 13876 |
|
|
Module compiled
|
| 13877 |
|
|
No errors in compilation
|
| 13878 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 13879 |
|
|
|
| 13880 |
|
|
|
| 13881 |
|
|
=========================================================================
|
| 13882 |
|
|
* HDL Analysis *
|
| 13883 |
|
|
=========================================================================
|
| 13884 |
|
|
Analyzing top module .
|
| 13885 |
|
|
Module is correct for synthesis.
|
| 13886 |
|
|
|
| 13887 |
|
|
Set property "resynthesize = true" for unit .
|
| 13888 |
|
|
Analyzing module .
|
| 13889 |
|
|
Module is correct for synthesis.
|
| 13890 |
|
|
|
| 13891 |
|
|
Analyzing module .
|
| 13892 |
|
|
pClockFrequency = 50
|
| 13893 |
|
|
pRefreshFrequency = 100
|
| 13894 |
|
|
pUpperLimit = 125000
|
| 13895 |
|
|
pDividerCounterBits = 24
|
| 13896 |
|
|
Module is correct for synthesis.
|
| 13897 |
|
|
|
| 13898 |
|
|
Analyzing module .
|
| 13899 |
|
|
pInitialValue = 0
|
| 13900 |
|
|
pTimerWidth = 19
|
| 13901 |
|
|
pInitialTimerValue = 500000
|
| 13902 |
|
|
Module is correct for synthesis.
|
| 13903 |
|
|
|
| 13904 |
|
|
Analyzing module .
|
| 13905 |
|
|
Module is correct for synthesis.
|
| 13906 |
|
|
|
| 13907 |
|
|
Analyzing module .
|
| 13908 |
|
|
SIZE = 16
|
| 13909 |
|
|
Module is correct for synthesis.
|
| 13910 |
|
|
|
| 13911 |
|
|
Analyzing module .
|
| 13912 |
|
|
Module is correct for synthesis.
|
| 13913 |
|
|
|
| 13914 |
|
|
Analyzing module .
|
| 13915 |
|
|
SIZE = 12
|
| 13916 |
|
|
Module is correct for synthesis.
|
| 13917 |
|
|
|
| 13918 |
|
|
Analyzing module .
|
| 13919 |
|
|
Module is correct for synthesis.
|
| 13920 |
|
|
|
| 13921 |
|
|
Analyzing module .
|
| 13922 |
|
|
VALUE = 0000000000000001
|
| 13923 |
|
|
Module is correct for synthesis.
|
| 13924 |
|
|
|
| 13925 |
|
|
Analyzing module .
|
| 13926 |
|
|
Module is correct for synthesis.
|
| 13927 |
|
|
|
| 13928 |
|
|
Analyzing module .
|
| 13929 |
|
|
VALUE = 1111111111111111
|
| 13930 |
|
|
Module is correct for synthesis.
|
| 13931 |
|
|
|
| 13932 |
|
|
Analyzing module .
|
| 13933 |
|
|
Module is correct for synthesis.
|
| 13934 |
|
|
|
| 13935 |
|
|
Analyzing module .
|
| 13936 |
|
|
VALUE = 0000000000000000
|
| 13937 |
|
|
Module is correct for synthesis.
|
| 13938 |
|
|
|
| 13939 |
|
|
Analyzing module .
|
| 13940 |
|
|
Module is correct for synthesis.
|
| 13941 |
|
|
|
| 13942 |
|
|
Analyzing module .
|
| 13943 |
|
|
Module is correct for synthesis.
|
| 13944 |
|
|
|
| 13945 |
|
|
Analyzing module .
|
| 13946 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 13947 |
|
|
Module is correct for synthesis.
|
| 13948 |
|
|
|
| 13949 |
|
|
Analyzing module .
|
| 13950 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 13951 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 13952 |
|
|
Module is correct for synthesis.
|
| 13953 |
|
|
|
| 13954 |
|
|
Analyzing module .
|
| 13955 |
|
|
Module is correct for synthesis.
|
| 13956 |
|
|
|
| 13957 |
|
|
Analyzing module .
|
| 13958 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13959 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13960 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13961 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13962 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13963 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13964 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13965 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13966 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13967 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13968 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13969 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13970 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13971 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 13972 |
|
|
Module is correct for synthesis.
|
| 13973 |
|
|
|
| 13974 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 13975 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 13976 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 13977 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 13978 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 13979 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 13980 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 13981 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 13982 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 13983 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 13984 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 13985 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 13986 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 13987 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 13988 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 13989 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 13990 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 13991 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 13992 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 13993 |
|
|
Analyzing module .
|
| 13994 |
|
|
Module is correct for synthesis.
|
| 13995 |
|
|
|
| 13996 |
|
|
Analyzing module .
|
| 13997 |
|
|
XTAL_CLK = 35000000
|
| 13998 |
|
|
BAUD = 9600
|
| 13999 |
|
|
CLK_DIV = 113
|
| 14000 |
|
|
CW = 8
|
| 14001 |
|
|
Module is correct for synthesis.
|
| 14002 |
|
|
|
| 14003 |
|
|
Analyzing module .
|
| 14004 |
|
|
Module is correct for synthesis.
|
| 14005 |
|
|
|
| 14006 |
|
|
Analyzing module .
|
| 14007 |
|
|
Module is correct for synthesis.
|
| 14008 |
|
|
|
| 14009 |
|
|
|
| 14010 |
|
|
=========================================================================
|
| 14011 |
|
|
* HDL Synthesis *
|
| 14012 |
|
|
=========================================================================
|
| 14013 |
|
|
|
| 14014 |
|
|
Synthesizing Unit .
|
| 14015 |
|
|
Related source file is "txmit.v".
|
| 14016 |
|
|
Found 1-bit register for signal .
|
| 14017 |
|
|
Found 1-bit register for signal .
|
| 14018 |
|
|
Found 1-bit register for signal .
|
| 14019 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 14020 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 14021 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 14022 |
|
|
Found 1-bit register for signal .
|
| 14023 |
|
|
Found 1-bit register for signal .
|
| 14024 |
|
|
Found 4-bit up counter for signal .
|
| 14025 |
|
|
Found 4-bit up counter for signal .
|
| 14026 |
|
|
Found 8-bit register for signal .
|
| 14027 |
|
|
Found 8-bit register for signal .
|
| 14028 |
|
|
Summary:
|
| 14029 |
|
|
inferred 2 Counter(s).
|
| 14030 |
|
|
inferred 21 D-type flip-flop(s).
|
| 14031 |
|
|
inferred 2 Comparator(s).
|
| 14032 |
|
|
inferred 1 Multiplexer(s).
|
| 14033 |
|
|
Unit synthesized.
|
| 14034 |
|
|
|
| 14035 |
|
|
|
| 14036 |
|
|
Synthesizing Unit .
|
| 14037 |
|
|
Related source file is "rcvr.v".
|
| 14038 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 14039 |
|
|
Found 1-bit register for signal .
|
| 14040 |
|
|
Found 1-bit register for signal .
|
| 14041 |
|
|
Found 1-bit register for signal .
|
| 14042 |
|
|
Found 8-bit tristate buffer for signal .
|
| 14043 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 14044 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 14045 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 14046 |
|
|
Found 1-bit register for signal .
|
| 14047 |
|
|
Found 1-bit register for signal .
|
| 14048 |
|
|
Found 4-bit register for signal .
|
| 14049 |
|
|
Found 4-bit up counter for signal .
|
| 14050 |
|
|
Found 8-bit register for signal .
|
| 14051 |
|
|
Found 7-bit register for signal >.
|
| 14052 |
|
|
Found 1-bit register for signal .
|
| 14053 |
|
|
Found 1-bit register for signal .
|
| 14054 |
|
|
Summary:
|
| 14055 |
|
|
inferred 1 Counter(s).
|
| 14056 |
|
|
inferred 26 D-type flip-flop(s).
|
| 14057 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 14058 |
|
|
inferred 1 Comparator(s).
|
| 14059 |
|
|
inferred 1 Multiplexer(s).
|
| 14060 |
|
|
inferred 8 Tristate(s).
|
| 14061 |
|
|
Unit synthesized.
|
| 14062 |
|
|
|
| 14063 |
|
|
|
| 14064 |
|
|
Synthesizing Unit .
|
| 14065 |
|
|
Related source file is "jkff.v".
|
| 14066 |
|
|
Found 1-bit register for signal .
|
| 14067 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 14068 |
|
|
Summary:
|
| 14069 |
|
|
inferred 1 D-type flip-flop(s).
|
| 14070 |
|
|
inferred 1 Multiplexer(s).
|
| 14071 |
|
|
Unit synthesized.
|
| 14072 |
|
|
|
| 14073 |
|
|
|
| 14074 |
|
|
Synthesizing Unit .
|
| 14075 |
|
|
Related source file is "switchsync.v".
|
| 14076 |
|
|
Found 1-bit register for signal .
|
| 14077 |
|
|
Found 1-bit register for signal .
|
| 14078 |
|
|
Summary:
|
| 14079 |
|
|
inferred 2 D-type flip-flop(s).
|
| 14080 |
|
|
Unit synthesized.
|
| 14081 |
|
|
|
| 14082 |
|
|
|
| 14083 |
|
|
Synthesizing Unit .
|
| 14084 |
|
|
Related source file is "maindcm.v".
|
| 14085 |
|
|
Unit synthesized.
|
| 14086 |
|
|
|
| 14087 |
|
|
|
| 14088 |
|
|
Synthesizing Unit .
|
| 14089 |
|
|
Related source file is "control.v".
|
| 14090 |
|
|
Found 1-bit register for signal .
|
| 14091 |
|
|
Found 1-bit register for signal .
|
| 14092 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 14093 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 14094 |
|
|
Found 3-bit up counter for signal .
|
| 14095 |
|
|
Summary:
|
| 14096 |
|
|
inferred 1 Counter(s).
|
| 14097 |
|
|
inferred 2 D-type flip-flop(s).
|
| 14098 |
|
|
inferred 2 Multiplexer(s).
|
| 14099 |
|
|
Unit synthesized.
|
| 14100 |
|
|
|
| 14101 |
|
|
|
| 14102 |
|
|
Synthesizing Unit .
|
| 14103 |
|
|
Related source file is "misc.v".
|
| 14104 |
|
|
Found 16-bit tristate buffer for signal .
|
| 14105 |
|
|
Summary:
|
| 14106 |
|
|
inferred 16 Tristate(s).
|
| 14107 |
|
|
Unit synthesized.
|
| 14108 |
|
|
|
| 14109 |
|
|
|
| 14110 |
|
|
Synthesizing Unit .
|
| 14111 |
|
|
Related source file is "misc.v".
|
| 14112 |
|
|
Found 16-bit tristate buffer for signal .
|
| 14113 |
|
|
Summary:
|
| 14114 |
|
|
inferred 16 Tristate(s).
|
| 14115 |
|
|
Unit synthesized.
|
| 14116 |
|
|
|
| 14117 |
|
|
|
| 14118 |
|
|
Synthesizing Unit .
|
| 14119 |
|
|
Related source file is "misc.v".
|
| 14120 |
|
|
Found 16-bit tristate buffer for signal .
|
| 14121 |
|
|
Summary:
|
| 14122 |
|
|
inferred 16 Tristate(s).
|
| 14123 |
|
|
Unit synthesized.
|
| 14124 |
|
|
|
| 14125 |
|
|
|
| 14126 |
|
|
Synthesizing Unit .
|
| 14127 |
|
|
Related source file is "misc.v".
|
| 14128 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 14129 |
|
|
Found 16-bit tristate buffer for signal .
|
| 14130 |
|
|
Found 12-bit register for signal .
|
| 14131 |
|
|
Summary:
|
| 14132 |
|
|
inferred 12 D-type flip-flop(s).
|
| 14133 |
|
|
inferred 16 Tristate(s).
|
| 14134 |
|
|
Unit synthesized.
|
| 14135 |
|
|
|
| 14136 |
|
|
|
| 14137 |
|
|
Synthesizing Unit .
|
| 14138 |
|
|
Related source file is "idecode.v".
|
| 14139 |
|
|
Unit synthesized.
|
| 14140 |
|
|
|
| 14141 |
|
|
|
| 14142 |
|
|
Synthesizing Unit .
|
| 14143 |
|
|
Related source file is "control.v".
|
| 14144 |
|
|
Unit synthesized.
|
| 14145 |
|
|
|
| 14146 |
|
|
|
| 14147 |
|
|
Synthesizing Unit .
|
| 14148 |
|
|
Related source file is "alu.v".
|
| 14149 |
|
|
Found 16-bit tristate buffer for signal .
|
| 14150 |
|
|
Found 17-bit subtractor for signal <$AUX_109>.
|
| 14151 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 14152 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 14153 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 14154 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 14155 |
|
|
Summary:
|
| 14156 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 14157 |
|
|
inferred 16 Tristate(s).
|
| 14158 |
|
|
Unit synthesized.
|
| 14159 |
|
|
|
| 14160 |
|
|
|
| 14161 |
|
|
Synthesizing Unit .
|
| 14162 |
|
|
Related source file is "misc.v".
|
| 14163 |
|
|
Unit synthesized.
|
| 14164 |
|
|
|
| 14165 |
|
|
|
| 14166 |
|
|
Synthesizing Unit .
|
| 14167 |
|
|
Related source file is "misc.v".
|
| 14168 |
|
|
Unit synthesized.
|
| 14169 |
|
|
|
| 14170 |
|
|
|
| 14171 |
|
|
Synthesizing Unit .
|
| 14172 |
|
|
Related source file is "misc.v".
|
| 14173 |
|
|
Unit synthesized.
|
| 14174 |
|
|
|
| 14175 |
|
|
|
| 14176 |
|
|
Synthesizing Unit .
|
| 14177 |
|
|
Related source file is "misc.v".
|
| 14178 |
|
|
Unit synthesized.
|
| 14179 |
|
|
|
| 14180 |
|
|
|
| 14181 |
|
|
Synthesizing Unit .
|
| 14182 |
|
|
Related source file is "misc.v".
|
| 14183 |
|
|
Found 16-bit tristate buffer for signal .
|
| 14184 |
|
|
Found 16-bit register for signal .
|
| 14185 |
|
|
Summary:
|
| 14186 |
|
|
inferred 16 D-type flip-flop(s).
|
| 14187 |
|
|
inferred 16 Tristate(s).
|
| 14188 |
|
|
Unit synthesized.
|
| 14189 |
|
|
|
| 14190 |
|
|
|
| 14191 |
|
|
Synthesizing Unit .
|
| 14192 |
|
|
Related source file is "io.v".
|
| 14193 |
|
|
Found 1-bit register for signal .
|
| 14194 |
|
|
Found 1-bit register for signal .
|
| 14195 |
|
|
Found 1-bit register for signal .
|
| 14196 |
|
|
Found 1-bit register for signal .
|
| 14197 |
|
|
Found 1-bit register for signal .
|
| 14198 |
|
|
Found 1-bit register for signal .
|
| 14199 |
|
|
Found 19-bit down counter for signal .
|
| 14200 |
|
|
Found 1-bit register for signal .
|
| 14201 |
|
|
Found 1-bit xor2 for signal .
|
| 14202 |
|
|
Summary:
|
| 14203 |
|
|
inferred 1 Counter(s).
|
| 14204 |
|
|
inferred 7 D-type flip-flop(s).
|
| 14205 |
|
|
Unit synthesized.
|
| 14206 |
|
|
|
| 14207 |
|
|
|
| 14208 |
|
|
Synthesizing Unit .
|
| 14209 |
|
|
Related source file is "io.v".
|
| 14210 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 14211 |
|
|
Found 1-bit register for signal .
|
| 14212 |
|
|
Found 1-bit register for signal .
|
| 14213 |
|
|
Found 1-bit register for signal .
|
| 14214 |
|
|
Found 1-bit register for signal .
|
| 14215 |
|
|
Found 1-bit register for signal .
|
| 14216 |
|
|
Found 1-bit register for signal .
|
| 14217 |
|
|
Found 1-bit register for signal .
|
| 14218 |
|
|
Found 1-bit register for signal .
|
| 14219 |
|
|
Found 1-bit register for signal .
|
| 14220 |
|
|
Found 1-bit register for signal .
|
| 14221 |
|
|
Found 1-bit register for signal .
|
| 14222 |
|
|
Found 1-bit register for signal .
|
| 14223 |
|
|
Found 24-bit up counter for signal .
|
| 14224 |
|
|
Found 1-of-4 decoder for signal .
|
| 14225 |
|
|
Found 2-bit down counter for signal .
|
| 14226 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 14227 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 14228 |
|
|
Summary:
|
| 14229 |
|
|
inferred 1 ROM(s).
|
| 14230 |
|
|
inferred 2 Counter(s).
|
| 14231 |
|
|
inferred 12 D-type flip-flop(s).
|
| 14232 |
|
|
inferred 9 Multiplexer(s).
|
| 14233 |
|
|
inferred 1 Decoder(s).
|
| 14234 |
|
|
Unit synthesized.
|
| 14235 |
|
|
|
| 14236 |
|
|
|
| 14237 |
|
|
Synthesizing Unit .
|
| 14238 |
|
|
Related source file is "uart.v".
|
| 14239 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 14240 |
|
|
Found 1-bit register for signal .
|
| 14241 |
|
|
Found 8-bit up counter for signal .
|
| 14242 |
|
|
Found 1-bit register for signal .
|
| 14243 |
|
|
Summary:
|
| 14244 |
|
|
inferred 1 Counter(s).
|
| 14245 |
|
|
inferred 2 D-type flip-flop(s).
|
| 14246 |
|
|
inferred 1 Multiplexer(s).
|
| 14247 |
|
|
Unit synthesized.
|
| 14248 |
|
|
|
| 14249 |
|
|
|
| 14250 |
|
|
Synthesizing Unit .
|
| 14251 |
|
|
Related source file is "top.v".
|
| 14252 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 14253 |
|
|
Found 16-bit tristate buffer for signal .
|
| 14254 |
|
|
Found 1-bit register for signal .
|
| 14255 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 14256 |
|
|
Found 16-bit tristate buffer for signal .
|
| 14257 |
|
|
Found 1-bit register for signal .
|
| 14258 |
|
|
Found 1-bit register for signal .
|
| 14259 |
|
|
Found 1-bit register for signal .
|
| 14260 |
|
|
Summary:
|
| 14261 |
|
|
inferred 4 D-type flip-flop(s).
|
| 14262 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 14263 |
|
|
inferred 96 Tristate(s).
|
| 14264 |
|
|
Unit synthesized.
|
| 14265 |
|
|
|
| 14266 |
|
|
|
| 14267 |
|
|
Synthesizing Unit .
|
| 14268 |
|
|
Related source file is "FrontPanel.v".
|
| 14269 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 14270 |
|
|
Found finite state machine for signal .
|
| 14271 |
|
|
-----------------------------------------------------------------------
|
| 14272 |
|
|
| States | 6 |
|
| 14273 |
|
|
| Transitions | 6 |
|
| 14274 |
|
|
| Inputs | 0 |
|
| 14275 |
|
|
| Outputs | 12 |
|
| 14276 |
|
|
| Clock | clockin (rising_edge) |
|
| 14277 |
|
|
| Clock enable | select (positive) |
|
| 14278 |
|
|
| Reset | clear (positive) |
|
| 14279 |
|
|
| Reset type | synchronous |
|
| 14280 |
|
|
| Reset State | 000001 |
|
| 14281 |
|
|
| Encoding | automatic |
|
| 14282 |
|
|
| Implementation | LUT |
|
| 14283 |
|
|
-----------------------------------------------------------------------
|
| 14284 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 14285 |
|
|
Found 4-bit register for signal .
|
| 14286 |
|
|
Found 16-bit register for signal .
|
| 14287 |
|
|
Summary:
|
| 14288 |
|
|
inferred 1 Finite State Machine(s).
|
| 14289 |
|
|
inferred 16 D-type flip-flop(s).
|
| 14290 |
|
|
inferred 16 Multiplexer(s).
|
| 14291 |
|
|
Unit synthesized.
|
| 14292 |
|
|
|
| 14293 |
|
|
|
| 14294 |
|
|
Synthesizing Unit .
|
| 14295 |
|
|
Related source file is "topbox.v".
|
| 14296 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 14297 |
|
|
Found 16-bit tristate buffer for signal .
|
| 14298 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 14299 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 14300 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 14301 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 14302 |
|
|
Found 4-bit register for signal .
|
| 14303 |
|
|
Found 1-bit register for signal .
|
| 14304 |
|
|
Found 1-bit register for signal .
|
| 14305 |
|
|
Found 16-bit register for signal .
|
| 14306 |
|
|
Summary:
|
| 14307 |
|
|
inferred 22 D-type flip-flop(s).
|
| 14308 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 14309 |
|
|
inferred 6 Multiplexer(s).
|
| 14310 |
|
|
inferred 48 Tristate(s).
|
| 14311 |
|
|
Unit synthesized.
|
| 14312 |
|
|
|
| 14313 |
|
|
|
| 14314 |
|
|
=========================================================================
|
| 14315 |
|
|
* Advanced HDL Synthesis *
|
| 14316 |
|
|
=========================================================================
|
| 14317 |
|
|
|
| 14318 |
|
|
Advanced RAM inference ...
|
| 14319 |
|
|
Advanced multiplier inference ...
|
| 14320 |
|
|
Advanced Registered AddSub inference ...
|
| 14321 |
|
|
Analyzing FSM for best encoding.
|
| 14322 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 14323 |
|
|
--------------------
|
| 14324 |
|
|
State | Encoding
|
| 14325 |
|
|
--------------------
|
| 14326 |
|
|
000001 | 100000
|
| 14327 |
|
|
000010 | 010000
|
| 14328 |
|
|
000100 | 001000
|
| 14329 |
|
|
001000 | 000100
|
| 14330 |
|
|
010000 | 000010
|
| 14331 |
|
|
100000 | 000001
|
| 14332 |
|
|
--------------------
|
| 14333 |
|
|
Dynamic shift register inference ...
|
| 14334 |
|
|
|
| 14335 |
|
|
=========================================================================
|
| 14336 |
|
|
HDL Synthesis Report
|
| 14337 |
|
|
|
| 14338 |
|
|
Macro Statistics
|
| 14339 |
|
|
# FSMs : 1
|
| 14340 |
|
|
# ROMs : 1
|
| 14341 |
|
|
16x7-bit ROM : 1
|
| 14342 |
|
|
# Adders/Subtractors : 5
|
| 14343 |
|
|
12-bit adder carry out : 1
|
| 14344 |
|
|
16-bit adder carry out : 1
|
| 14345 |
|
|
17-bit subtractor : 1
|
| 14346 |
|
|
4-bit adder : 2
|
| 14347 |
|
|
# Counters : 10
|
| 14348 |
|
|
19-bit down counter : 3
|
| 14349 |
|
|
2-bit down counter : 1
|
| 14350 |
|
|
24-bit up counter : 1
|
| 14351 |
|
|
3-bit up counter : 1
|
| 14352 |
|
|
4-bit up counter : 3
|
| 14353 |
|
|
8-bit up counter : 1
|
| 14354 |
|
|
# Registers : 138
|
| 14355 |
|
|
1-bit register : 125
|
| 14356 |
|
|
12-bit register : 4
|
| 14357 |
|
|
16-bit register : 4
|
| 14358 |
|
|
4-bit register : 3
|
| 14359 |
|
|
8-bit register : 2
|
| 14360 |
|
|
# Comparators : 3
|
| 14361 |
|
|
4-bit comparator greater : 2
|
| 14362 |
|
|
4-bit comparator less : 1
|
| 14363 |
|
|
# Multiplexers : 15
|
| 14364 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 14365 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 14366 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 14367 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 14368 |
|
|
# Decoders : 1
|
| 14369 |
|
|
1-of-4 decoder : 1
|
| 14370 |
|
|
# Tristates : 97
|
| 14371 |
|
|
1-bit tristate buffer : 80
|
| 14372 |
|
|
16-bit tristate buffer : 16
|
| 14373 |
|
|
8-bit tristate buffer : 1
|
| 14374 |
|
|
# Xors : 6
|
| 14375 |
|
|
1-bit xor2 : 5
|
| 14376 |
|
|
16-bit xor2 : 1
|
| 14377 |
|
|
|
| 14378 |
|
|
=========================================================================
|
| 14379 |
|
|
|
| 14380 |
|
|
=========================================================================
|
| 14381 |
|
|
* Low Level Synthesis *
|
| 14382 |
|
|
=========================================================================
|
| 14383 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 14384 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 14385 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 14386 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 14387 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 14388 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 14389 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 14390 |
|
|
|
| 14391 |
|
|
Optimizing unit ...
|
| 14392 |
|
|
|
| 14393 |
|
|
Optimizing unit ...
|
| 14394 |
|
|
|
| 14395 |
|
|
Optimizing unit ...
|
| 14396 |
|
|
|
| 14397 |
|
|
Optimizing unit ...
|
| 14398 |
|
|
|
| 14399 |
|
|
Optimizing unit ...
|
| 14400 |
|
|
|
| 14401 |
|
|
Optimizing unit ...
|
| 14402 |
|
|
|
| 14403 |
|
|
Optimizing unit ...
|
| 14404 |
|
|
|
| 14405 |
|
|
Optimizing unit ...
|
| 14406 |
|
|
|
| 14407 |
|
|
Optimizing unit ...
|
| 14408 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 14409 |
|
|
|
| 14410 |
|
|
Mapping all equations...
|
| 14411 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 14412 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 14413 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 14414 |
|
|
Building and optimizing final netlist ...
|
| 14415 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
|
| 14416 |
|
|
Forward register balancing over CPU/decoder/opdec78 of flipflops :
|
| 14417 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 14418 |
|
|
Forward register balancing over CPU/decoder/opxor1 of flipflops :
|
| 14419 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
|
| 14420 |
|
|
Forward register balancing over CPU/decoder/opand1 of flipflops :
|
| 14421 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 14422 |
|
|
Forward register balancing over CPU/decoder/opior1 of flipflops :
|
| 14423 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
|
| 14424 |
|
|
Forward register balancing over CPU/decoder/oplda1 of flipflops :
|
| 14425 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
|
| 14426 |
|
|
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
|
| 14427 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 14428 |
|
|
Forward register balancing over Ker571 of flipflops :
|
| 14429 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 14430 |
|
|
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
|
| 14431 |
|
|
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 14432 |
|
|
Forward register balancing over Ker2101 of flipflops :
|
| 14433 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 14434 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
|
| 14435 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
|
| 14436 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
|
| 14437 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 14438 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
|
| 14439 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
|
| 14440 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
|
| 14441 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 14442 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
|
| 14443 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 14444 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
|
| 14445 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
|
| 14446 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
|
| 14447 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 14448 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
|
| 14449 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 14450 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
|
| 14451 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 14452 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
|
| 14453 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
|
| 14454 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
|
| 14455 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 14456 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
|
| 14457 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
|
| 14458 |
|
|
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
|
| 14459 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 14460 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
|
| 14461 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 14462 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
|
| 14463 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 14464 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
|
| 14465 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 14466 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
|
| 14467 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 14468 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
|
| 14469 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 14470 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
|
| 14471 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 14472 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
|
| 14473 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 14474 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
|
| 14475 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4.
|
| 14476 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
|
| 14477 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 14478 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
|
| 14479 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
|
| 14480 |
|
|
Forward register balancing over Ker2161_SW0 of flipflops :
|
| 14481 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 14482 |
|
|
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
|
| 14483 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 14484 |
|
|
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
|
| 14485 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 14486 |
|
|
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
|
| 14487 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 14488 |
|
|
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
|
| 14489 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 14490 |
|
|
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
|
| 14491 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 14492 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
|
| 14493 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 14494 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
|
| 14495 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 14496 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
|
| 14497 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 14498 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
|
| 14499 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 14500 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
|
| 14501 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
|
| 14502 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
|
| 14503 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 14504 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
|
| 14505 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 14506 |
|
|
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
|
| 14507 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
|
| 14508 |
|
|
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
|
| 14509 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 14510 |
|
|
Forward register balancing over Ker161_SW0 of flipflops :
|
| 14511 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_6.
|
| 14512 |
|
|
Forward register balancing over CPU/decoder/opdec74 of flipflops :
|
| 14513 |
|
|
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
|
| 14514 |
|
|
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
|
| 14515 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 14516 |
|
|
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
|
| 14517 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 14518 |
|
|
Forward register balancing over CPU/msend9 of flipflops :
|
| 14519 |
|
|
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
|
| 14520 |
|
|
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
|
| 14521 |
|
|
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
|
| 14522 |
|
|
Forward register balancing over CPU/decoder/opadd1 of flipflops :
|
| 14523 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 14524 |
|
|
Forward register balancing over CPU/decoder/opdec41 of flipflops :
|
| 14525 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
|
| 14526 |
|
|
Forward register balancing over CPU/decoder/opinc41 of flipflops :
|
| 14527 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
|
| 14528 |
|
|
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
|
| 14529 |
|
|
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 14530 |
|
|
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
|
| 14531 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 14532 |
|
|
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
|
| 14533 |
|
|
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 14534 |
|
|
Forward register balancing over Ker212_SW0 of flipflops :
|
| 14535 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
|
| 14536 |
|
|
Forward register balancing over CPU/decoder/opdec714 of flipflops :
|
| 14537 |
|
|
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
|
| 14538 |
|
|
Register equivalent to has been removed
|
| 14539 |
|
|
Register equivalent to has been removed
|
| 14540 |
|
|
Register equivalent to has been removed
|
| 14541 |
|
|
Register equivalent to has been removed
|
| 14542 |
|
|
Register equivalent to has been removed
|
| 14543 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
|
| 14544 |
|
|
FlipFlop CPU/ctl/sim/F1_FRB has been replicated 2 time(s)
|
| 14545 |
|
|
FlipFlop CPU/ctl/sim/counter_0 has been replicated 3 time(s)
|
| 14546 |
|
|
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
|
| 14547 |
|
|
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
|
| 14548 |
|
|
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
|
| 14549 |
|
|
FlipFlop loadnow has been replicated 1 time(s)
|
| 14550 |
|
|
|
| 14551 |
|
|
=========================================================================
|
| 14552 |
|
|
* Final Report *
|
| 14553 |
|
|
=========================================================================
|
| 14554 |
|
|
|
| 14555 |
|
|
Device utilization summary:
|
| 14556 |
|
|
---------------------------
|
| 14557 |
|
|
|
| 14558 |
|
|
Selected Device : 3s200ft256-4
|
| 14559 |
|
|
|
| 14560 |
|
|
Number of Slices: 615 out of 1920 32%
|
| 14561 |
|
|
Number of Slice Flip Flops: 433 out of 3840 11%
|
| 14562 |
|
|
Number of 4 input LUTs: 1081 out of 3840 28%
|
| 14563 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 14564 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 14565 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 14566 |
|
|
|
| 14567 |
|
|
|
| 14568 |
|
|
=========================================================================
|
| 14569 |
|
|
TIMING REPORT
|
| 14570 |
|
|
|
| 14571 |
|
|
|
| 14572 |
|
|
Clock Information:
|
| 14573 |
|
|
------------------
|
| 14574 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 14575 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 14576 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 14577 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 433 |
|
| 14578 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 14579 |
|
|
|
| 14580 |
|
|
Timing Summary:
|
| 14581 |
|
|
---------------
|
| 14582 |
|
|
Speed Grade: -4
|
| 14583 |
|
|
|
| 14584 |
|
|
Minimum period: 13.483ns (Maximum Frequency: 74.169MHz)
|
| 14585 |
|
|
Minimum input arrival time before clock: 11.144ns
|
| 14586 |
|
|
Maximum output required time after clock: 23.107ns
|
| 14587 |
|
|
Maximum combinational path delay: 15.256ns
|
| 14588 |
|
|
|
| 14589 |
|
|
=========================================================================
|
| 14590 |
|
|
|
| 14591 |
|
|
|
| 14592 |
|
|
|
| 14593 |
|
|
|
| 14594 |
|
|
|
| 14595 |
|
|
Started process "Translate".
|
| 14596 |
|
|
|
| 14597 |
|
|
|
| 14598 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 14599 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 14600 |
|
|
|
| 14601 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 14602 |
|
|
|
| 14603 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 14604 |
|
|
|
| 14605 |
|
|
Checking timing specifications ...
|
| 14606 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 14607 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 14608 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 14609 |
|
|
20.408000 nS HIGH 50.000000%
|
| 14610 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 14611 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 14612 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 14613 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 14614 |
|
|
from this group.
|
| 14615 |
|
|
Checking expanded design ...
|
| 14616 |
|
|
|
| 14617 |
|
|
NGDBUILD Design Results Summary:
|
| 14618 |
|
|
Number of errors: 0
|
| 14619 |
|
|
Number of warnings: 1
|
| 14620 |
|
|
|
| 14621 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 14622 |
|
|
|
| 14623 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 14624 |
|
|
|
| 14625 |
|
|
NGDBUILD done.
|
| 14626 |
|
|
|
| 14627 |
|
|
|
| 14628 |
|
|
|
| 14629 |
|
|
|
| 14630 |
|
|
Started process "Map".
|
| 14631 |
|
|
|
| 14632 |
|
|
Using target part "3s200ft256-4".
|
| 14633 |
|
|
Mapping design into LUTs...
|
| 14634 |
|
|
Running directed packing...
|
| 14635 |
|
|
Running delay-based LUT packing...
|
| 14636 |
|
|
Running timing-driven packing...
|
| 14637 |
|
|
|
| 14638 |
|
|
Phase 1.1
|
| 14639 |
|
|
Phase 1.1 (Checksum:98d694) REAL time: 1 secs
|
| 14640 |
|
|
|
| 14641 |
|
|
Phase 2.31
|
| 14642 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
|
| 14643 |
|
|
|
| 14644 |
|
|
Phase 3.2
|
| 14645 |
|
|
.
|
| 14646 |
|
|
|
| 14647 |
|
|
|
| 14648 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
|
| 14649 |
|
|
|
| 14650 |
|
|
Phase 4.4
|
| 14651 |
|
|
..............
|
| 14652 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 4 secs
|
| 14653 |
|
|
|
| 14654 |
|
|
Phase 5.28
|
| 14655 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 4 secs
|
| 14656 |
|
|
|
| 14657 |
|
|
Phase 6.8
|
| 14658 |
|
|
........................
|
| 14659 |
|
|
.......
|
| 14660 |
|
|
..................
|
| 14661 |
|
|
...............
|
| 14662 |
|
|
...............
|
| 14663 |
|
|
Phase 6.8 (Checksum:ab4095) REAL time: 10 secs
|
| 14664 |
|
|
|
| 14665 |
|
|
Phase 7.29
|
| 14666 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs
|
| 14667 |
|
|
|
| 14668 |
|
|
Phase 8.5
|
| 14669 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs
|
| 14670 |
|
|
|
| 14671 |
|
|
Phase 9.18
|
| 14672 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 20 secs
|
| 14673 |
|
|
|
| 14674 |
|
|
Phase 10.5
|
| 14675 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 20 secs
|
| 14676 |
|
|
|
| 14677 |
|
|
|
| 14678 |
|
|
Design Summary:
|
| 14679 |
|
|
Number of errors: 0
|
| 14680 |
|
|
Number of warnings: 11
|
| 14681 |
|
|
Logic Utilization:
|
| 14682 |
|
|
Number of Slice Flip Flops: 407 out of 3,840 10%
|
| 14683 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 14684 |
|
|
Logic Distribution:
|
| 14685 |
|
|
Number of occupied Slices: 684 out of 1,920 35%
|
| 14686 |
|
|
Number of Slices containing only related logic: 684 out of 684 100%
|
| 14687 |
|
|
Number of Slices containing unrelated logic: 0 out of 684 0%
|
| 14688 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 14689 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 14690 |
|
|
Number used as logic: 1,131
|
| 14691 |
|
|
Number used as a route-thru: 4
|
| 14692 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 14693 |
|
|
IOB Flip Flops: 26
|
| 14694 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 14695 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 14696 |
|
|
|
| 14697 |
|
|
Total equivalent gate count for design: 18,123
|
| 14698 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 14699 |
|
|
Peak Memory Usage: 133 MB
|
| 14700 |
|
|
|
| 14701 |
|
|
Mapping completed.
|
| 14702 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 14703 |
|
|
|
| 14704 |
|
|
|
| 14705 |
|
|
|
| 14706 |
|
|
|
| 14707 |
|
|
Started process "Place & Route".
|
| 14708 |
|
|
|
| 14709 |
|
|
|
| 14710 |
|
|
|
| 14711 |
|
|
|
| 14712 |
|
|
Constraints file: topbox.pcf.
|
| 14713 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 14714 |
|
|
C:/Xilinx71.
|
| 14715 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 14716 |
|
|
|
| 14717 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 14718 |
|
|
Celsius)
|
| 14719 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 14720 |
|
|
|
| 14721 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 14722 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 14723 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 14724 |
|
|
ps (24.00 Mhz).
|
| 14725 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 14726 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 14727 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 14728 |
|
|
(210.04 Mhz).
|
| 14729 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 14730 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 14731 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 14732 |
|
|
ps (24.00 Mhz).
|
| 14733 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 14734 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 14735 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 14736 |
|
|
(210.04 Mhz).
|
| 14737 |
|
|
|
| 14738 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 14739 |
|
|
|
| 14740 |
|
|
|
| 14741 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 14742 |
|
|
achieve better performance.
|
| 14743 |
|
|
|
| 14744 |
|
|
Device Utilization Summary:
|
| 14745 |
|
|
|
| 14746 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 14747 |
|
|
Number of DCMs 1 out of 4 25%
|
| 14748 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 14749 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 14750 |
|
|
|
| 14751 |
|
|
Number of Slices 684 out of 1920 35%
|
| 14752 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 14753 |
|
|
|
| 14754 |
|
|
|
| 14755 |
|
|
|
| 14756 |
|
|
Overall effort level (-ol): High (set by user)
|
| 14757 |
|
|
Router effort level (-rl): High (set by user)
|
| 14758 |
|
|
|
| 14759 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 14760 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 14761 |
|
|
|
| 14762 |
|
|
Starting Router
|
| 14763 |
|
|
|
| 14764 |
|
|
Phase 1: 4897 unrouted; REAL time: 4 secs
|
| 14765 |
|
|
|
| 14766 |
|
|
Phase 2: 4533 unrouted; REAL time: 4 secs
|
| 14767 |
|
|
|
| 14768 |
|
|
Phase 3: 2191 unrouted; REAL time: 5 secs
|
| 14769 |
|
|
|
| 14770 |
|
|
Phase 4: 2191 unrouted; (0) REAL time: 5 secs
|
| 14771 |
|
|
|
| 14772 |
|
|
Phase 5: 2191 unrouted; (0) REAL time: 6 secs
|
| 14773 |
|
|
|
| 14774 |
|
|
Phase 6: 2191 unrouted; (0) REAL time: 6 secs
|
| 14775 |
|
|
|
| 14776 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 9 secs
|
| 14777 |
|
|
|
| 14778 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 10 secs
|
| 14779 |
|
|
|
| 14780 |
|
|
|
| 14781 |
|
|
Total REAL time to Router completion: 10 secs
|
| 14782 |
|
|
Total CPU time to Router completion: 10 secs
|
| 14783 |
|
|
|
| 14784 |
|
|
Generating "PAR" statistics.
|
| 14785 |
|
|
|
| 14786 |
|
|
**************************
|
| 14787 |
|
|
Generating Clock Report
|
| 14788 |
|
|
**************************
|
| 14789 |
|
|
|
| 14790 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 14791 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 14792 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 14793 |
|
|
| clk | BUFGMUX2| No | 344 | 0.041 | 1.051 |
|
| 14794 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 14795 |
|
|
|
| 14796 |
|
|
Timing Score: 0
|
| 14797 |
|
|
|
| 14798 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 14799 |
|
|
This may be due to a setup or hold violation.
|
| 14800 |
|
|
|
| 14801 |
|
|
--------------------------------------------------------------------------------
|
| 14802 |
|
|
Constraint | Requested | Actual | Logic
|
| 14803 |
|
|
| | | Levels
|
| 14804 |
|
|
--------------------------------------------------------------------------------
|
| 14805 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 14806 |
|
|
HIGH 50% | | |
|
| 14807 |
|
|
--------------------------------------------------------------------------------
|
| 14808 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 24.924ns | 4
|
| 14809 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 14810 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 14811 |
|
|
--------------------------------------------------------------------------------
|
| 14812 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 38.312ns | 10
|
| 14813 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 14814 |
|
|
HIGH 50% | | |
|
| 14815 |
|
|
--------------------------------------------------------------------------------
|
| 14816 |
|
|
|
| 14817 |
|
|
|
| 14818 |
|
|
All constraints were met.
|
| 14819 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 14820 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 14821 |
|
|
Generating Pad Report.
|
| 14822 |
|
|
|
| 14823 |
|
|
All signals are completely routed.
|
| 14824 |
|
|
|
| 14825 |
|
|
Total REAL time to PAR completion: 11 secs
|
| 14826 |
|
|
Total CPU time to PAR completion: 11 secs
|
| 14827 |
|
|
|
| 14828 |
|
|
Peak Memory Usage: 93 MB
|
| 14829 |
|
|
|
| 14830 |
|
|
Placer: Not run.
|
| 14831 |
|
|
Routing: Completed - No errors found.
|
| 14832 |
|
|
Timing: Completed - No errors found.
|
| 14833 |
|
|
|
| 14834 |
|
|
Number of error messages: 0
|
| 14835 |
|
|
Number of warning messages: 4
|
| 14836 |
|
|
Number of info messages: 1
|
| 14837 |
|
|
|
| 14838 |
|
|
Writing design to file topbox.ncd
|
| 14839 |
|
|
|
| 14840 |
|
|
|
| 14841 |
|
|
|
| 14842 |
|
|
PAR done!
|
| 14843 |
|
|
|
| 14844 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 14845 |
|
|
|
| 14846 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 14847 |
|
|
C:/Xilinx71.
|
| 14848 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 14849 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 14850 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 14851 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 14852 |
|
|
ps (24.00 Mhz).
|
| 14853 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 14854 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 14855 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 14856 |
|
|
(210.04 Mhz).
|
| 14857 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 14858 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 14859 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 14860 |
|
|
ps (24.00 Mhz).
|
| 14861 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 14862 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 14863 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 14864 |
|
|
(210.04 Mhz).
|
| 14865 |
|
|
|
| 14866 |
|
|
Analysis completed Sat Sep 30 00:33:08 2006
|
| 14867 |
|
|
--------------------------------------------------------------------------------
|
| 14868 |
|
|
|
| 14869 |
|
|
Generating Report ...
|
| 14870 |
|
|
|
| 14871 |
|
|
Number of warnings: 4
|
| 14872 |
|
|
Total time: 3 secs
|
| 14873 |
|
|
|
| 14874 |
|
|
|
| 14875 |
|
|
|
| 14876 |
|
|
|
| 14877 |
|
|
|
| 14878 |
|
|
|
| 14879 |
|
|
|
| 14880 |
|
|
Started process "Generate Programming File".
|
| 14881 |
|
|
|
| 14882 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 14883 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 14884 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 14885 |
|
|
Interactive Data Sheet.
|
| 14886 |
|
|
|
| 14887 |
|
|
|
| 14888 |
|
|
Project Navigator Auto-Make Log File
|
| 14889 |
|
|
-------------------------------------
|
| 14890 |
|
|
|
| 14891 |
|
|
|
| 14892 |
|
|
|
| 14893 |
|
|
|
| 14894 |
|
|
|
| 14895 |
|
|
|
| 14896 |
|
|
|
| 14897 |
|
|
|
| 14898 |
|
|
|
| 14899 |
|
|
|
| 14900 |
|
|
Started process "Synthesize".
|
| 14901 |
|
|
|
| 14902 |
|
|
|
| 14903 |
|
|
=========================================================================
|
| 14904 |
|
|
* HDL Compilation *
|
| 14905 |
|
|
=========================================================================
|
| 14906 |
|
|
Compiling verilog file "io.v"
|
| 14907 |
|
|
Module compiled
|
| 14908 |
|
|
Module compiled
|
| 14909 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 14910 |
|
|
Module compiled
|
| 14911 |
|
|
Compiling verilog file "misc.v"
|
| 14912 |
|
|
Module compiled
|
| 14913 |
|
|
Module compiled
|
| 14914 |
|
|
Module compiled
|
| 14915 |
|
|
Module compiled
|
| 14916 |
|
|
Module compiled
|
| 14917 |
|
|
Module compiled
|
| 14918 |
|
|
Compiling verilog file "alu.v"
|
| 14919 |
|
|
Module compiled
|
| 14920 |
|
|
Compiling verilog file "switchsync.v"
|
| 14921 |
|
|
Module compiled
|
| 14922 |
|
|
Compiling verilog file "jkff.v"
|
| 14923 |
|
|
Module compiled
|
| 14924 |
|
|
Compiling verilog file "control.v"
|
| 14925 |
|
|
Module compiled
|
| 14926 |
|
|
Module compiled
|
| 14927 |
|
|
Compiling verilog file "maindcm.v"
|
| 14928 |
|
|
Module compiled
|
| 14929 |
|
|
Compiling verilog file "idecode.v"
|
| 14930 |
|
|
Module compiled
|
| 14931 |
|
|
Compiling verilog file "top.v"
|
| 14932 |
|
|
Module compiled
|
| 14933 |
|
|
Compiling verilog file "rcvr.v"
|
| 14934 |
|
|
Module compiled
|
| 14935 |
|
|
Compiling verilog file "txmit.v"
|
| 14936 |
|
|
Module compiled
|
| 14937 |
|
|
Compiling verilog file "uart.v"
|
| 14938 |
|
|
Module compiled
|
| 14939 |
|
|
Compiling verilog file "topbox.v"
|
| 14940 |
|
|
Module compiled
|
| 14941 |
|
|
No errors in compilation
|
| 14942 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 14943 |
|
|
|
| 14944 |
|
|
|
| 14945 |
|
|
=========================================================================
|
| 14946 |
|
|
* HDL Analysis *
|
| 14947 |
|
|
=========================================================================
|
| 14948 |
|
|
Analyzing top module .
|
| 14949 |
|
|
Module is correct for synthesis.
|
| 14950 |
|
|
|
| 14951 |
|
|
Set property "resynthesize = true" for unit .
|
| 14952 |
|
|
Analyzing module .
|
| 14953 |
|
|
Module is correct for synthesis.
|
| 14954 |
|
|
|
| 14955 |
|
|
Analyzing module .
|
| 14956 |
|
|
pClockFrequency = 50
|
| 14957 |
|
|
pRefreshFrequency = 100
|
| 14958 |
|
|
pUpperLimit = 125000
|
| 14959 |
|
|
pDividerCounterBits = 24
|
| 14960 |
|
|
Module is correct for synthesis.
|
| 14961 |
|
|
|
| 14962 |
|
|
Analyzing module .
|
| 14963 |
|
|
pInitialValue = 0
|
| 14964 |
|
|
pTimerWidth = 19
|
| 14965 |
|
|
pInitialTimerValue = 500000
|
| 14966 |
|
|
Module is correct for synthesis.
|
| 14967 |
|
|
|
| 14968 |
|
|
Analyzing module .
|
| 14969 |
|
|
Module is correct for synthesis.
|
| 14970 |
|
|
|
| 14971 |
|
|
Analyzing module .
|
| 14972 |
|
|
SIZE = 16
|
| 14973 |
|
|
Module is correct for synthesis.
|
| 14974 |
|
|
|
| 14975 |
|
|
Analyzing module .
|
| 14976 |
|
|
Module is correct for synthesis.
|
| 14977 |
|
|
|
| 14978 |
|
|
Analyzing module .
|
| 14979 |
|
|
SIZE = 12
|
| 14980 |
|
|
Module is correct for synthesis.
|
| 14981 |
|
|
|
| 14982 |
|
|
Analyzing module .
|
| 14983 |
|
|
Module is correct for synthesis.
|
| 14984 |
|
|
|
| 14985 |
|
|
Analyzing module .
|
| 14986 |
|
|
VALUE = 0000000000000001
|
| 14987 |
|
|
Module is correct for synthesis.
|
| 14988 |
|
|
|
| 14989 |
|
|
Analyzing module .
|
| 14990 |
|
|
Module is correct for synthesis.
|
| 14991 |
|
|
|
| 14992 |
|
|
Analyzing module .
|
| 14993 |
|
|
VALUE = 1111111111111111
|
| 14994 |
|
|
Module is correct for synthesis.
|
| 14995 |
|
|
|
| 14996 |
|
|
Analyzing module .
|
| 14997 |
|
|
Module is correct for synthesis.
|
| 14998 |
|
|
|
| 14999 |
|
|
Analyzing module .
|
| 15000 |
|
|
VALUE = 0000000000000000
|
| 15001 |
|
|
Module is correct for synthesis.
|
| 15002 |
|
|
|
| 15003 |
|
|
Analyzing module .
|
| 15004 |
|
|
Module is correct for synthesis.
|
| 15005 |
|
|
|
| 15006 |
|
|
Analyzing module .
|
| 15007 |
|
|
Module is correct for synthesis.
|
| 15008 |
|
|
|
| 15009 |
|
|
Analyzing module .
|
| 15010 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 15011 |
|
|
Module is correct for synthesis.
|
| 15012 |
|
|
|
| 15013 |
|
|
Analyzing module .
|
| 15014 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 15015 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 15016 |
|
|
Module is correct for synthesis.
|
| 15017 |
|
|
|
| 15018 |
|
|
Analyzing module .
|
| 15019 |
|
|
Module is correct for synthesis.
|
| 15020 |
|
|
|
| 15021 |
|
|
Analyzing module .
|
| 15022 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15023 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15024 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15025 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15026 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15027 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15028 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15029 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15030 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15031 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15032 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15033 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15034 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15035 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 15036 |
|
|
Module is correct for synthesis.
|
| 15037 |
|
|
|
| 15038 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 15039 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 15040 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 15041 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 15042 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 15043 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 15044 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 15045 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 15046 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 15047 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 15048 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 15049 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 15050 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 15051 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 15052 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 15053 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 15054 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 15055 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 15056 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 15057 |
|
|
Analyzing module .
|
| 15058 |
|
|
Module is correct for synthesis.
|
| 15059 |
|
|
|
| 15060 |
|
|
Analyzing module .
|
| 15061 |
|
|
XTAL_CLK = 35000000
|
| 15062 |
|
|
BAUD = 9600
|
| 15063 |
|
|
CLK_DIV = 113
|
| 15064 |
|
|
CW = 8
|
| 15065 |
|
|
Module is correct for synthesis.
|
| 15066 |
|
|
|
| 15067 |
|
|
Analyzing module .
|
| 15068 |
|
|
Module is correct for synthesis.
|
| 15069 |
|
|
|
| 15070 |
|
|
Analyzing module .
|
| 15071 |
|
|
Module is correct for synthesis.
|
| 15072 |
|
|
|
| 15073 |
|
|
|
| 15074 |
|
|
=========================================================================
|
| 15075 |
|
|
* HDL Synthesis *
|
| 15076 |
|
|
=========================================================================
|
| 15077 |
|
|
|
| 15078 |
|
|
Synthesizing Unit .
|
| 15079 |
|
|
Related source file is "txmit.v".
|
| 15080 |
|
|
Found 1-bit register for signal .
|
| 15081 |
|
|
Found 1-bit register for signal .
|
| 15082 |
|
|
Found 1-bit register for signal .
|
| 15083 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 15084 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 15085 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 15086 |
|
|
Found 1-bit register for signal .
|
| 15087 |
|
|
Found 1-bit register for signal .
|
| 15088 |
|
|
Found 4-bit up counter for signal .
|
| 15089 |
|
|
Found 4-bit up counter for signal .
|
| 15090 |
|
|
Found 8-bit register for signal .
|
| 15091 |
|
|
Found 8-bit register for signal .
|
| 15092 |
|
|
Summary:
|
| 15093 |
|
|
inferred 2 Counter(s).
|
| 15094 |
|
|
inferred 21 D-type flip-flop(s).
|
| 15095 |
|
|
inferred 2 Comparator(s).
|
| 15096 |
|
|
inferred 1 Multiplexer(s).
|
| 15097 |
|
|
Unit synthesized.
|
| 15098 |
|
|
|
| 15099 |
|
|
|
| 15100 |
|
|
Synthesizing Unit .
|
| 15101 |
|
|
Related source file is "rcvr.v".
|
| 15102 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 15103 |
|
|
Found 1-bit register for signal .
|
| 15104 |
|
|
Found 1-bit register for signal .
|
| 15105 |
|
|
Found 1-bit register for signal .
|
| 15106 |
|
|
Found 8-bit tristate buffer for signal .
|
| 15107 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 15108 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 15109 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 15110 |
|
|
Found 1-bit register for signal .
|
| 15111 |
|
|
Found 1-bit register for signal .
|
| 15112 |
|
|
Found 4-bit register for signal .
|
| 15113 |
|
|
Found 4-bit up counter for signal .
|
| 15114 |
|
|
Found 8-bit register for signal .
|
| 15115 |
|
|
Found 7-bit register for signal >.
|
| 15116 |
|
|
Found 1-bit register for signal .
|
| 15117 |
|
|
Found 1-bit register for signal .
|
| 15118 |
|
|
Summary:
|
| 15119 |
|
|
inferred 1 Counter(s).
|
| 15120 |
|
|
inferred 26 D-type flip-flop(s).
|
| 15121 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 15122 |
|
|
inferred 1 Comparator(s).
|
| 15123 |
|
|
inferred 1 Multiplexer(s).
|
| 15124 |
|
|
inferred 8 Tristate(s).
|
| 15125 |
|
|
Unit synthesized.
|
| 15126 |
|
|
|
| 15127 |
|
|
|
| 15128 |
|
|
Synthesizing Unit .
|
| 15129 |
|
|
Related source file is "jkff.v".
|
| 15130 |
|
|
Found 1-bit register for signal .
|
| 15131 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 15132 |
|
|
Summary:
|
| 15133 |
|
|
inferred 1 D-type flip-flop(s).
|
| 15134 |
|
|
inferred 1 Multiplexer(s).
|
| 15135 |
|
|
Unit synthesized.
|
| 15136 |
|
|
|
| 15137 |
|
|
|
| 15138 |
|
|
Synthesizing Unit .
|
| 15139 |
|
|
Related source file is "switchsync.v".
|
| 15140 |
|
|
Found 1-bit register for signal .
|
| 15141 |
|
|
Found 1-bit register for signal .
|
| 15142 |
|
|
Summary:
|
| 15143 |
|
|
inferred 2 D-type flip-flop(s).
|
| 15144 |
|
|
Unit synthesized.
|
| 15145 |
|
|
|
| 15146 |
|
|
|
| 15147 |
|
|
Synthesizing Unit .
|
| 15148 |
|
|
Related source file is "maindcm.v".
|
| 15149 |
|
|
Unit synthesized.
|
| 15150 |
|
|
|
| 15151 |
|
|
|
| 15152 |
|
|
Synthesizing Unit .
|
| 15153 |
|
|
Related source file is "control.v".
|
| 15154 |
|
|
Found 1-bit register for signal .
|
| 15155 |
|
|
Found 1-bit register for signal .
|
| 15156 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 15157 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 15158 |
|
|
Found 3-bit up counter for signal .
|
| 15159 |
|
|
Summary:
|
| 15160 |
|
|
inferred 1 Counter(s).
|
| 15161 |
|
|
inferred 2 D-type flip-flop(s).
|
| 15162 |
|
|
inferred 2 Multiplexer(s).
|
| 15163 |
|
|
Unit synthesized.
|
| 15164 |
|
|
|
| 15165 |
|
|
|
| 15166 |
|
|
Synthesizing Unit .
|
| 15167 |
|
|
Related source file is "misc.v".
|
| 15168 |
|
|
Found 16-bit tristate buffer for signal .
|
| 15169 |
|
|
Summary:
|
| 15170 |
|
|
inferred 16 Tristate(s).
|
| 15171 |
|
|
Unit synthesized.
|
| 15172 |
|
|
|
| 15173 |
|
|
|
| 15174 |
|
|
Synthesizing Unit .
|
| 15175 |
|
|
Related source file is "misc.v".
|
| 15176 |
|
|
Found 16-bit tristate buffer for signal .
|
| 15177 |
|
|
Summary:
|
| 15178 |
|
|
inferred 16 Tristate(s).
|
| 15179 |
|
|
Unit synthesized.
|
| 15180 |
|
|
|
| 15181 |
|
|
|
| 15182 |
|
|
Synthesizing Unit .
|
| 15183 |
|
|
Related source file is "misc.v".
|
| 15184 |
|
|
Found 16-bit tristate buffer for signal .
|
| 15185 |
|
|
Summary:
|
| 15186 |
|
|
inferred 16 Tristate(s).
|
| 15187 |
|
|
Unit synthesized.
|
| 15188 |
|
|
|
| 15189 |
|
|
|
| 15190 |
|
|
Synthesizing Unit .
|
| 15191 |
|
|
Related source file is "misc.v".
|
| 15192 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 15193 |
|
|
Found 16-bit tristate buffer for signal .
|
| 15194 |
|
|
Found 12-bit register for signal .
|
| 15195 |
|
|
Summary:
|
| 15196 |
|
|
inferred 12 D-type flip-flop(s).
|
| 15197 |
|
|
inferred 16 Tristate(s).
|
| 15198 |
|
|
Unit synthesized.
|
| 15199 |
|
|
|
| 15200 |
|
|
|
| 15201 |
|
|
Synthesizing Unit .
|
| 15202 |
|
|
Related source file is "idecode.v".
|
| 15203 |
|
|
Unit synthesized.
|
| 15204 |
|
|
|
| 15205 |
|
|
|
| 15206 |
|
|
Synthesizing Unit .
|
| 15207 |
|
|
Related source file is "control.v".
|
| 15208 |
|
|
Unit synthesized.
|
| 15209 |
|
|
|
| 15210 |
|
|
|
| 15211 |
|
|
Synthesizing Unit .
|
| 15212 |
|
|
Related source file is "alu.v".
|
| 15213 |
|
|
Found 16-bit tristate buffer for signal .
|
| 15214 |
|
|
Found 17-bit subtractor for signal <$AUX_109>.
|
| 15215 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 15216 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 15217 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 15218 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 15219 |
|
|
Summary:
|
| 15220 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 15221 |
|
|
inferred 16 Tristate(s).
|
| 15222 |
|
|
Unit synthesized.
|
| 15223 |
|
|
|
| 15224 |
|
|
|
| 15225 |
|
|
Synthesizing Unit .
|
| 15226 |
|
|
Related source file is "misc.v".
|
| 15227 |
|
|
Unit synthesized.
|
| 15228 |
|
|
|
| 15229 |
|
|
|
| 15230 |
|
|
Synthesizing Unit .
|
| 15231 |
|
|
Related source file is "misc.v".
|
| 15232 |
|
|
Unit synthesized.
|
| 15233 |
|
|
|
| 15234 |
|
|
|
| 15235 |
|
|
Synthesizing Unit .
|
| 15236 |
|
|
Related source file is "misc.v".
|
| 15237 |
|
|
Unit synthesized.
|
| 15238 |
|
|
|
| 15239 |
|
|
|
| 15240 |
|
|
Synthesizing Unit .
|
| 15241 |
|
|
Related source file is "misc.v".
|
| 15242 |
|
|
Unit synthesized.
|
| 15243 |
|
|
|
| 15244 |
|
|
|
| 15245 |
|
|
Synthesizing Unit .
|
| 15246 |
|
|
Related source file is "misc.v".
|
| 15247 |
|
|
Found 16-bit tristate buffer for signal .
|
| 15248 |
|
|
Found 16-bit register for signal .
|
| 15249 |
|
|
Summary:
|
| 15250 |
|
|
inferred 16 D-type flip-flop(s).
|
| 15251 |
|
|
inferred 16 Tristate(s).
|
| 15252 |
|
|
Unit synthesized.
|
| 15253 |
|
|
|
| 15254 |
|
|
|
| 15255 |
|
|
Synthesizing Unit .
|
| 15256 |
|
|
Related source file is "io.v".
|
| 15257 |
|
|
Found 1-bit register for signal .
|
| 15258 |
|
|
Found 1-bit register for signal .
|
| 15259 |
|
|
Found 1-bit register for signal .
|
| 15260 |
|
|
Found 1-bit register for signal .
|
| 15261 |
|
|
Found 1-bit register for signal .
|
| 15262 |
|
|
Found 1-bit register for signal .
|
| 15263 |
|
|
Found 19-bit down counter for signal .
|
| 15264 |
|
|
Found 1-bit register for signal .
|
| 15265 |
|
|
Found 1-bit xor2 for signal .
|
| 15266 |
|
|
Summary:
|
| 15267 |
|
|
inferred 1 Counter(s).
|
| 15268 |
|
|
inferred 7 D-type flip-flop(s).
|
| 15269 |
|
|
Unit synthesized.
|
| 15270 |
|
|
|
| 15271 |
|
|
|
| 15272 |
|
|
Synthesizing Unit .
|
| 15273 |
|
|
Related source file is "io.v".
|
| 15274 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 15275 |
|
|
Found 1-bit register for signal .
|
| 15276 |
|
|
Found 1-bit register for signal .
|
| 15277 |
|
|
Found 1-bit register for signal .
|
| 15278 |
|
|
Found 1-bit register for signal .
|
| 15279 |
|
|
Found 1-bit register for signal .
|
| 15280 |
|
|
Found 1-bit register for signal .
|
| 15281 |
|
|
Found 1-bit register for signal .
|
| 15282 |
|
|
Found 1-bit register for signal .
|
| 15283 |
|
|
Found 1-bit register for signal .
|
| 15284 |
|
|
Found 1-bit register for signal .
|
| 15285 |
|
|
Found 1-bit register for signal .
|
| 15286 |
|
|
Found 1-bit register for signal .
|
| 15287 |
|
|
Found 24-bit up counter for signal .
|
| 15288 |
|
|
Found 1-of-4 decoder for signal .
|
| 15289 |
|
|
Found 2-bit down counter for signal .
|
| 15290 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 15291 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 15292 |
|
|
Summary:
|
| 15293 |
|
|
inferred 1 ROM(s).
|
| 15294 |
|
|
inferred 2 Counter(s).
|
| 15295 |
|
|
inferred 12 D-type flip-flop(s).
|
| 15296 |
|
|
inferred 9 Multiplexer(s).
|
| 15297 |
|
|
inferred 1 Decoder(s).
|
| 15298 |
|
|
Unit synthesized.
|
| 15299 |
|
|
|
| 15300 |
|
|
|
| 15301 |
|
|
Synthesizing Unit .
|
| 15302 |
|
|
Related source file is "uart.v".
|
| 15303 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 15304 |
|
|
Found 1-bit register for signal .
|
| 15305 |
|
|
Found 8-bit up counter for signal .
|
| 15306 |
|
|
Found 1-bit register for signal .
|
| 15307 |
|
|
Summary:
|
| 15308 |
|
|
inferred 1 Counter(s).
|
| 15309 |
|
|
inferred 2 D-type flip-flop(s).
|
| 15310 |
|
|
inferred 1 Multiplexer(s).
|
| 15311 |
|
|
Unit synthesized.
|
| 15312 |
|
|
|
| 15313 |
|
|
|
| 15314 |
|
|
Synthesizing Unit .
|
| 15315 |
|
|
Related source file is "top.v".
|
| 15316 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 15317 |
|
|
Found 16-bit tristate buffer for signal .
|
| 15318 |
|
|
Found 1-bit register for signal .
|
| 15319 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 15320 |
|
|
Found 16-bit tristate buffer for signal .
|
| 15321 |
|
|
Found 1-bit register for signal .
|
| 15322 |
|
|
Found 1-bit register for signal .
|
| 15323 |
|
|
Found 1-bit register for signal .
|
| 15324 |
|
|
Summary:
|
| 15325 |
|
|
inferred 4 D-type flip-flop(s).
|
| 15326 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 15327 |
|
|
inferred 96 Tristate(s).
|
| 15328 |
|
|
Unit synthesized.
|
| 15329 |
|
|
|
| 15330 |
|
|
|
| 15331 |
|
|
Synthesizing Unit .
|
| 15332 |
|
|
Related source file is "FrontPanel.v".
|
| 15333 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 15334 |
|
|
Found finite state machine for signal .
|
| 15335 |
|
|
-----------------------------------------------------------------------
|
| 15336 |
|
|
| States | 6 |
|
| 15337 |
|
|
| Transitions | 6 |
|
| 15338 |
|
|
| Inputs | 0 |
|
| 15339 |
|
|
| Outputs | 12 |
|
| 15340 |
|
|
| Clock | clockin (rising_edge) |
|
| 15341 |
|
|
| Clock enable | select (positive) |
|
| 15342 |
|
|
| Reset | clear (positive) |
|
| 15343 |
|
|
| Reset type | synchronous |
|
| 15344 |
|
|
| Reset State | 000001 |
|
| 15345 |
|
|
| Encoding | automatic |
|
| 15346 |
|
|
| Implementation | LUT |
|
| 15347 |
|
|
-----------------------------------------------------------------------
|
| 15348 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 15349 |
|
|
Found 4-bit register for signal .
|
| 15350 |
|
|
Found 16-bit register for signal .
|
| 15351 |
|
|
Summary:
|
| 15352 |
|
|
inferred 1 Finite State Machine(s).
|
| 15353 |
|
|
inferred 16 D-type flip-flop(s).
|
| 15354 |
|
|
inferred 16 Multiplexer(s).
|
| 15355 |
|
|
Unit synthesized.
|
| 15356 |
|
|
|
| 15357 |
|
|
|
| 15358 |
|
|
Synthesizing Unit .
|
| 15359 |
|
|
Related source file is "topbox.v".
|
| 15360 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 15361 |
|
|
Found 16-bit tristate buffer for signal .
|
| 15362 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 15363 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 15364 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 15365 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 15366 |
|
|
Found 4-bit register for signal .
|
| 15367 |
|
|
Found 1-bit register for signal .
|
| 15368 |
|
|
Found 1-bit register for signal .
|
| 15369 |
|
|
Found 16-bit register for signal .
|
| 15370 |
|
|
Summary:
|
| 15371 |
|
|
inferred 22 D-type flip-flop(s).
|
| 15372 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 15373 |
|
|
inferred 6 Multiplexer(s).
|
| 15374 |
|
|
inferred 48 Tristate(s).
|
| 15375 |
|
|
Unit synthesized.
|
| 15376 |
|
|
|
| 15377 |
|
|
|
| 15378 |
|
|
=========================================================================
|
| 15379 |
|
|
* Advanced HDL Synthesis *
|
| 15380 |
|
|
=========================================================================
|
| 15381 |
|
|
|
| 15382 |
|
|
Advanced RAM inference ...
|
| 15383 |
|
|
Advanced multiplier inference ...
|
| 15384 |
|
|
Advanced Registered AddSub inference ...
|
| 15385 |
|
|
Analyzing FSM for best encoding.
|
| 15386 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 15387 |
|
|
--------------------
|
| 15388 |
|
|
State | Encoding
|
| 15389 |
|
|
--------------------
|
| 15390 |
|
|
000001 | 100000
|
| 15391 |
|
|
000010 | 010000
|
| 15392 |
|
|
000100 | 001000
|
| 15393 |
|
|
001000 | 000100
|
| 15394 |
|
|
010000 | 000010
|
| 15395 |
|
|
100000 | 000001
|
| 15396 |
|
|
--------------------
|
| 15397 |
|
|
Dynamic shift register inference ...
|
| 15398 |
|
|
|
| 15399 |
|
|
=========================================================================
|
| 15400 |
|
|
HDL Synthesis Report
|
| 15401 |
|
|
|
| 15402 |
|
|
Macro Statistics
|
| 15403 |
|
|
# FSMs : 1
|
| 15404 |
|
|
# ROMs : 1
|
| 15405 |
|
|
16x7-bit ROM : 1
|
| 15406 |
|
|
# Adders/Subtractors : 5
|
| 15407 |
|
|
12-bit adder carry out : 1
|
| 15408 |
|
|
16-bit adder carry out : 1
|
| 15409 |
|
|
17-bit subtractor : 1
|
| 15410 |
|
|
4-bit adder : 2
|
| 15411 |
|
|
# Counters : 10
|
| 15412 |
|
|
19-bit down counter : 3
|
| 15413 |
|
|
2-bit down counter : 1
|
| 15414 |
|
|
24-bit up counter : 1
|
| 15415 |
|
|
3-bit up counter : 1
|
| 15416 |
|
|
4-bit up counter : 3
|
| 15417 |
|
|
8-bit up counter : 1
|
| 15418 |
|
|
# Registers : 138
|
| 15419 |
|
|
1-bit register : 125
|
| 15420 |
|
|
12-bit register : 4
|
| 15421 |
|
|
16-bit register : 4
|
| 15422 |
|
|
4-bit register : 3
|
| 15423 |
|
|
8-bit register : 2
|
| 15424 |
|
|
# Comparators : 3
|
| 15425 |
|
|
4-bit comparator greater : 2
|
| 15426 |
|
|
4-bit comparator less : 1
|
| 15427 |
|
|
# Multiplexers : 15
|
| 15428 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 15429 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 15430 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 15431 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 15432 |
|
|
# Decoders : 1
|
| 15433 |
|
|
1-of-4 decoder : 1
|
| 15434 |
|
|
# Tristates : 97
|
| 15435 |
|
|
1-bit tristate buffer : 80
|
| 15436 |
|
|
16-bit tristate buffer : 16
|
| 15437 |
|
|
8-bit tristate buffer : 1
|
| 15438 |
|
|
# Xors : 6
|
| 15439 |
|
|
1-bit xor2 : 5
|
| 15440 |
|
|
16-bit xor2 : 1
|
| 15441 |
|
|
|
| 15442 |
|
|
=========================================================================
|
| 15443 |
|
|
|
| 15444 |
|
|
=========================================================================
|
| 15445 |
|
|
* Low Level Synthesis *
|
| 15446 |
|
|
=========================================================================
|
| 15447 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 15448 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 15449 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 15450 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 15451 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 15452 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 15453 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 15454 |
|
|
|
| 15455 |
|
|
Optimizing unit ...
|
| 15456 |
|
|
|
| 15457 |
|
|
Optimizing unit ...
|
| 15458 |
|
|
|
| 15459 |
|
|
Optimizing unit ...
|
| 15460 |
|
|
|
| 15461 |
|
|
Optimizing unit ...
|
| 15462 |
|
|
|
| 15463 |
|
|
Optimizing unit ...
|
| 15464 |
|
|
|
| 15465 |
|
|
Optimizing unit ...
|
| 15466 |
|
|
|
| 15467 |
|
|
Optimizing unit ...
|
| 15468 |
|
|
|
| 15469 |
|
|
Optimizing unit ...
|
| 15470 |
|
|
|
| 15471 |
|
|
Optimizing unit ...
|
| 15472 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 15473 |
|
|
|
| 15474 |
|
|
Mapping all equations...
|
| 15475 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 15476 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 15477 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 15478 |
|
|
Building and optimizing final netlist ...
|
| 15479 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
|
| 15480 |
|
|
Forward register balancing over CPU/decoder/opdec78 of flipflops :
|
| 15481 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 15482 |
|
|
Forward register balancing over CPU/decoder/opxor1 of flipflops :
|
| 15483 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
|
| 15484 |
|
|
Forward register balancing over CPU/decoder/opand1 of flipflops :
|
| 15485 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 15486 |
|
|
Forward register balancing over CPU/decoder/opior1 of flipflops :
|
| 15487 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
|
| 15488 |
|
|
Forward register balancing over CPU/decoder/oplda1 of flipflops :
|
| 15489 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
|
| 15490 |
|
|
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
|
| 15491 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 15492 |
|
|
Forward register balancing over Ker571 of flipflops :
|
| 15493 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 15494 |
|
|
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
|
| 15495 |
|
|
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 15496 |
|
|
Forward register balancing over Ker2101 of flipflops :
|
| 15497 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 15498 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
|
| 15499 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
|
| 15500 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
|
| 15501 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 15502 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
|
| 15503 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
|
| 15504 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
|
| 15505 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 15506 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
|
| 15507 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 15508 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
|
| 15509 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
|
| 15510 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
|
| 15511 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 15512 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
|
| 15513 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 15514 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
|
| 15515 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 15516 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
|
| 15517 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
|
| 15518 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
|
| 15519 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 15520 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
|
| 15521 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
|
| 15522 |
|
|
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
|
| 15523 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 15524 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
|
| 15525 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 15526 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
|
| 15527 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 15528 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
|
| 15529 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 15530 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
|
| 15531 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 15532 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
|
| 15533 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 15534 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
|
| 15535 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 15536 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
|
| 15537 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 15538 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
|
| 15539 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4.
|
| 15540 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
|
| 15541 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 15542 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
|
| 15543 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
|
| 15544 |
|
|
Forward register balancing over Ker2161_SW0 of flipflops :
|
| 15545 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 15546 |
|
|
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
|
| 15547 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 15548 |
|
|
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
|
| 15549 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 15550 |
|
|
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
|
| 15551 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 15552 |
|
|
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
|
| 15553 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 15554 |
|
|
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
|
| 15555 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 15556 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
|
| 15557 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 15558 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
|
| 15559 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 15560 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
|
| 15561 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 15562 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
|
| 15563 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 15564 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
|
| 15565 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
|
| 15566 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
|
| 15567 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 15568 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
|
| 15569 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 15570 |
|
|
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
|
| 15571 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
|
| 15572 |
|
|
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
|
| 15573 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 15574 |
|
|
Forward register balancing over Ker161_SW0 of flipflops :
|
| 15575 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_6.
|
| 15576 |
|
|
Forward register balancing over CPU/decoder/opdec74 of flipflops :
|
| 15577 |
|
|
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
|
| 15578 |
|
|
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
|
| 15579 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 15580 |
|
|
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
|
| 15581 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 15582 |
|
|
Forward register balancing over CPU/msend9 of flipflops :
|
| 15583 |
|
|
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
|
| 15584 |
|
|
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
|
| 15585 |
|
|
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
|
| 15586 |
|
|
Forward register balancing over CPU/decoder/opadd1 of flipflops :
|
| 15587 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 15588 |
|
|
Forward register balancing over CPU/decoder/opdec41 of flipflops :
|
| 15589 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
|
| 15590 |
|
|
Forward register balancing over CPU/decoder/opinc41 of flipflops :
|
| 15591 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
|
| 15592 |
|
|
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
|
| 15593 |
|
|
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 15594 |
|
|
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
|
| 15595 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 15596 |
|
|
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
|
| 15597 |
|
|
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 15598 |
|
|
Forward register balancing over Ker212_SW0 of flipflops :
|
| 15599 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
|
| 15600 |
|
|
Forward register balancing over CPU/decoder/opdec714 of flipflops :
|
| 15601 |
|
|
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
|
| 15602 |
|
|
Register equivalent to has been removed
|
| 15603 |
|
|
Register equivalent to has been removed
|
| 15604 |
|
|
Register equivalent to has been removed
|
| 15605 |
|
|
Register equivalent to has been removed
|
| 15606 |
|
|
Register equivalent to has been removed
|
| 15607 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
|
| 15608 |
|
|
FlipFlop CPU/ctl/sim/F1_FRB has been replicated 2 time(s)
|
| 15609 |
|
|
FlipFlop CPU/ctl/sim/counter_0 has been replicated 3 time(s)
|
| 15610 |
|
|
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
|
| 15611 |
|
|
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
|
| 15612 |
|
|
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
|
| 15613 |
|
|
FlipFlop loadnow has been replicated 1 time(s)
|
| 15614 |
|
|
|
| 15615 |
|
|
=========================================================================
|
| 15616 |
|
|
* Final Report *
|
| 15617 |
|
|
=========================================================================
|
| 15618 |
|
|
|
| 15619 |
|
|
Device utilization summary:
|
| 15620 |
|
|
---------------------------
|
| 15621 |
|
|
|
| 15622 |
|
|
Selected Device : 3s200ft256-4
|
| 15623 |
|
|
|
| 15624 |
|
|
Number of Slices: 615 out of 1920 32%
|
| 15625 |
|
|
Number of Slice Flip Flops: 433 out of 3840 11%
|
| 15626 |
|
|
Number of 4 input LUTs: 1081 out of 3840 28%
|
| 15627 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 15628 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 15629 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 15630 |
|
|
|
| 15631 |
|
|
|
| 15632 |
|
|
=========================================================================
|
| 15633 |
|
|
TIMING REPORT
|
| 15634 |
|
|
|
| 15635 |
|
|
|
| 15636 |
|
|
Clock Information:
|
| 15637 |
|
|
------------------
|
| 15638 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 15639 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 15640 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 15641 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 433 |
|
| 15642 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 15643 |
|
|
|
| 15644 |
|
|
Timing Summary:
|
| 15645 |
|
|
---------------
|
| 15646 |
|
|
Speed Grade: -4
|
| 15647 |
|
|
|
| 15648 |
|
|
Minimum period: 13.483ns (Maximum Frequency: 74.169MHz)
|
| 15649 |
|
|
Minimum input arrival time before clock: 11.144ns
|
| 15650 |
|
|
Maximum output required time after clock: 23.107ns
|
| 15651 |
|
|
Maximum combinational path delay: 15.256ns
|
| 15652 |
|
|
|
| 15653 |
|
|
=========================================================================
|
| 15654 |
|
|
|
| 15655 |
|
|
|
| 15656 |
|
|
|
| 15657 |
|
|
|
| 15658 |
|
|
Started process "Translate".
|
| 15659 |
|
|
|
| 15660 |
|
|
|
| 15661 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 15662 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 15663 |
|
|
|
| 15664 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 15665 |
|
|
|
| 15666 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 15667 |
|
|
|
| 15668 |
|
|
Checking timing specifications ...
|
| 15669 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 15670 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 15671 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 15672 |
|
|
20.408000 nS HIGH 50.000000%
|
| 15673 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 15674 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 15675 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 15676 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 15677 |
|
|
from this group.
|
| 15678 |
|
|
Checking expanded design ...
|
| 15679 |
|
|
|
| 15680 |
|
|
NGDBUILD Design Results Summary:
|
| 15681 |
|
|
Number of errors: 0
|
| 15682 |
|
|
Number of warnings: 1
|
| 15683 |
|
|
|
| 15684 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 15685 |
|
|
|
| 15686 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 15687 |
|
|
|
| 15688 |
|
|
NGDBUILD done.
|
| 15689 |
|
|
|
| 15690 |
|
|
|
| 15691 |
|
|
|
| 15692 |
|
|
|
| 15693 |
|
|
Started process "Map".
|
| 15694 |
|
|
|
| 15695 |
|
|
Using target part "3s200ft256-4".
|
| 15696 |
|
|
Mapping design into LUTs...
|
| 15697 |
|
|
Running directed packing...
|
| 15698 |
|
|
Running delay-based LUT packing...
|
| 15699 |
|
|
Running timing-driven packing...
|
| 15700 |
|
|
|
| 15701 |
|
|
Phase 1.1
|
| 15702 |
|
|
Phase 1.1 (Checksum:98d694) REAL time: 1 secs
|
| 15703 |
|
|
|
| 15704 |
|
|
Phase 2.31
|
| 15705 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs
|
| 15706 |
|
|
|
| 15707 |
|
|
Phase 3.2
|
| 15708 |
|
|
.
|
| 15709 |
|
|
|
| 15710 |
|
|
|
| 15711 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
|
| 15712 |
|
|
|
| 15713 |
|
|
Phase 4.4
|
| 15714 |
|
|
..............
|
| 15715 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 4 secs
|
| 15716 |
|
|
|
| 15717 |
|
|
Phase 5.28
|
| 15718 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 4 secs
|
| 15719 |
|
|
|
| 15720 |
|
|
Phase 6.8
|
| 15721 |
|
|
........................
|
| 15722 |
|
|
.......
|
| 15723 |
|
|
..................
|
| 15724 |
|
|
...............
|
| 15725 |
|
|
...............
|
| 15726 |
|
|
Phase 6.8 (Checksum:ab4095) REAL time: 10 secs
|
| 15727 |
|
|
|
| 15728 |
|
|
Phase 7.29
|
| 15729 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs
|
| 15730 |
|
|
|
| 15731 |
|
|
Phase 8.5
|
| 15732 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs
|
| 15733 |
|
|
|
| 15734 |
|
|
Phase 9.18
|
| 15735 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 20 secs
|
| 15736 |
|
|
|
| 15737 |
|
|
Phase 10.5
|
| 15738 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 20 secs
|
| 15739 |
|
|
|
| 15740 |
|
|
|
| 15741 |
|
|
Design Summary:
|
| 15742 |
|
|
Number of errors: 0
|
| 15743 |
|
|
Number of warnings: 11
|
| 15744 |
|
|
Logic Utilization:
|
| 15745 |
|
|
Number of Slice Flip Flops: 407 out of 3,840 10%
|
| 15746 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 15747 |
|
|
Logic Distribution:
|
| 15748 |
|
|
Number of occupied Slices: 684 out of 1,920 35%
|
| 15749 |
|
|
Number of Slices containing only related logic: 684 out of 684 100%
|
| 15750 |
|
|
Number of Slices containing unrelated logic: 0 out of 684 0%
|
| 15751 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 15752 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 15753 |
|
|
Number used as logic: 1,131
|
| 15754 |
|
|
Number used as a route-thru: 4
|
| 15755 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 15756 |
|
|
IOB Flip Flops: 26
|
| 15757 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 15758 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 15759 |
|
|
|
| 15760 |
|
|
Total equivalent gate count for design: 18,123
|
| 15761 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 15762 |
|
|
Peak Memory Usage: 133 MB
|
| 15763 |
|
|
|
| 15764 |
|
|
Mapping completed.
|
| 15765 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 15766 |
|
|
|
| 15767 |
|
|
|
| 15768 |
|
|
|
| 15769 |
|
|
|
| 15770 |
|
|
Started process "Place & Route".
|
| 15771 |
|
|
|
| 15772 |
|
|
|
| 15773 |
|
|
|
| 15774 |
|
|
|
| 15775 |
|
|
Constraints file: topbox.pcf.
|
| 15776 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 15777 |
|
|
C:/Xilinx71.
|
| 15778 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 15779 |
|
|
|
| 15780 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 15781 |
|
|
Celsius)
|
| 15782 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 15783 |
|
|
|
| 15784 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 15785 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 15786 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 15787 |
|
|
ps (24.00 Mhz).
|
| 15788 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 15789 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 15790 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 15791 |
|
|
(210.04 Mhz).
|
| 15792 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 15793 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 15794 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 15795 |
|
|
ps (24.00 Mhz).
|
| 15796 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 15797 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 15798 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 15799 |
|
|
(210.04 Mhz).
|
| 15800 |
|
|
|
| 15801 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 15802 |
|
|
|
| 15803 |
|
|
|
| 15804 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 15805 |
|
|
achieve better performance.
|
| 15806 |
|
|
|
| 15807 |
|
|
Device Utilization Summary:
|
| 15808 |
|
|
|
| 15809 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 15810 |
|
|
Number of DCMs 1 out of 4 25%
|
| 15811 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 15812 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 15813 |
|
|
|
| 15814 |
|
|
Number of Slices 684 out of 1920 35%
|
| 15815 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 15816 |
|
|
|
| 15817 |
|
|
|
| 15818 |
|
|
|
| 15819 |
|
|
Overall effort level (-ol): High (set by user)
|
| 15820 |
|
|
Router effort level (-rl): High (set by user)
|
| 15821 |
|
|
|
| 15822 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 15823 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 15824 |
|
|
|
| 15825 |
|
|
Starting Router
|
| 15826 |
|
|
|
| 15827 |
|
|
Phase 1: 4897 unrouted; REAL time: 5 secs
|
| 15828 |
|
|
|
| 15829 |
|
|
Phase 2: 4533 unrouted; REAL time: 5 secs
|
| 15830 |
|
|
|
| 15831 |
|
|
Phase 3: 2191 unrouted; REAL time: 5 secs
|
| 15832 |
|
|
|
| 15833 |
|
|
Phase 4: 2191 unrouted; (0) REAL time: 6 secs
|
| 15834 |
|
|
|
| 15835 |
|
|
Phase 5: 2191 unrouted; (0) REAL time: 6 secs
|
| 15836 |
|
|
|
| 15837 |
|
|
Phase 6: 2191 unrouted; (0) REAL time: 6 secs
|
| 15838 |
|
|
|
| 15839 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 9 secs
|
| 15840 |
|
|
|
| 15841 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 10 secs
|
| 15842 |
|
|
|
| 15843 |
|
|
|
| 15844 |
|
|
Total REAL time to Router completion: 10 secs
|
| 15845 |
|
|
Total CPU time to Router completion: 10 secs
|
| 15846 |
|
|
|
| 15847 |
|
|
Generating "PAR" statistics.
|
| 15848 |
|
|
|
| 15849 |
|
|
**************************
|
| 15850 |
|
|
Generating Clock Report
|
| 15851 |
|
|
**************************
|
| 15852 |
|
|
|
| 15853 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 15854 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 15855 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 15856 |
|
|
| clk | BUFGMUX2| No | 344 | 0.041 | 1.051 |
|
| 15857 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 15858 |
|
|
|
| 15859 |
|
|
Timing Score: 0
|
| 15860 |
|
|
|
| 15861 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 15862 |
|
|
This may be due to a setup or hold violation.
|
| 15863 |
|
|
|
| 15864 |
|
|
--------------------------------------------------------------------------------
|
| 15865 |
|
|
Constraint | Requested | Actual | Logic
|
| 15866 |
|
|
| | | Levels
|
| 15867 |
|
|
--------------------------------------------------------------------------------
|
| 15868 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 15869 |
|
|
HIGH 50% | | |
|
| 15870 |
|
|
--------------------------------------------------------------------------------
|
| 15871 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 23.930ns | 5
|
| 15872 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 15873 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 15874 |
|
|
--------------------------------------------------------------------------------
|
| 15875 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 40.472ns | 9
|
| 15876 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 15877 |
|
|
HIGH 50% | | |
|
| 15878 |
|
|
--------------------------------------------------------------------------------
|
| 15879 |
|
|
|
| 15880 |
|
|
|
| 15881 |
|
|
All constraints were met.
|
| 15882 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 15883 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 15884 |
|
|
Generating Pad Report.
|
| 15885 |
|
|
|
| 15886 |
|
|
All signals are completely routed.
|
| 15887 |
|
|
|
| 15888 |
|
|
Total REAL time to PAR completion: 12 secs
|
| 15889 |
|
|
Total CPU time to PAR completion: 11 secs
|
| 15890 |
|
|
|
| 15891 |
|
|
Peak Memory Usage: 92 MB
|
| 15892 |
|
|
|
| 15893 |
|
|
Placer: Not run.
|
| 15894 |
|
|
Routing: Completed - No errors found.
|
| 15895 |
|
|
Timing: Completed - No errors found.
|
| 15896 |
|
|
|
| 15897 |
|
|
Number of error messages: 0
|
| 15898 |
|
|
Number of warning messages: 4
|
| 15899 |
|
|
Number of info messages: 1
|
| 15900 |
|
|
|
| 15901 |
|
|
Writing design to file topbox.ncd
|
| 15902 |
|
|
|
| 15903 |
|
|
|
| 15904 |
|
|
|
| 15905 |
|
|
PAR done!
|
| 15906 |
|
|
|
| 15907 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 15908 |
|
|
|
| 15909 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 15910 |
|
|
C:/Xilinx71.
|
| 15911 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 15912 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 15913 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 15914 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 15915 |
|
|
ps (24.00 Mhz).
|
| 15916 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 15917 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 15918 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 15919 |
|
|
(210.04 Mhz).
|
| 15920 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 15921 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 15922 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 15923 |
|
|
ps (24.00 Mhz).
|
| 15924 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 15925 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 15926 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 15927 |
|
|
(210.04 Mhz).
|
| 15928 |
|
|
|
| 15929 |
|
|
Analysis completed Sat Sep 30 20:03:53 2006
|
| 15930 |
|
|
--------------------------------------------------------------------------------
|
| 15931 |
|
|
|
| 15932 |
|
|
Generating Report ...
|
| 15933 |
|
|
|
| 15934 |
|
|
Number of warnings: 4
|
| 15935 |
|
|
Total time: 3 secs
|
| 15936 |
|
|
|
| 15937 |
|
|
|
| 15938 |
|
|
|
| 15939 |
|
|
|
| 15940 |
|
|
|
| 15941 |
|
|
|
| 15942 |
|
|
|
| 15943 |
|
|
Started process "Generate Programming File".
|
| 15944 |
|
|
|
| 15945 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 15946 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 15947 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 15948 |
|
|
Interactive Data Sheet.
|
| 15949 |
|
|
|
| 15950 |
|
|
|
| 15951 |
|
|
Project Navigator Auto-Make Log File
|
| 15952 |
|
|
-------------------------------------
|
| 15953 |
|
|
|
| 15954 |
|
|
|
| 15955 |
|
|
|
| 15956 |
|
|
|
| 15957 |
|
|
|
| 15958 |
|
|
|
| 15959 |
|
|
|
| 15960 |
|
|
|
| 15961 |
|
|
|
| 15962 |
|
|
|
| 15963 |
|
|
Started process "Synthesize".
|
| 15964 |
|
|
|
| 15965 |
|
|
|
| 15966 |
|
|
=========================================================================
|
| 15967 |
|
|
* HDL Compilation *
|
| 15968 |
|
|
=========================================================================
|
| 15969 |
|
|
Compiling verilog file "io.v"
|
| 15970 |
|
|
Module compiled
|
| 15971 |
|
|
Module compiled
|
| 15972 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 15973 |
|
|
Module compiled
|
| 15974 |
|
|
Compiling verilog file "misc.v"
|
| 15975 |
|
|
Module compiled
|
| 15976 |
|
|
Module compiled
|
| 15977 |
|
|
Module compiled
|
| 15978 |
|
|
Module compiled
|
| 15979 |
|
|
Module compiled
|
| 15980 |
|
|
Module compiled
|
| 15981 |
|
|
Compiling verilog file "alu.v"
|
| 15982 |
|
|
Module compiled
|
| 15983 |
|
|
Compiling verilog file "switchsync.v"
|
| 15984 |
|
|
Module compiled
|
| 15985 |
|
|
Compiling verilog file "jkff.v"
|
| 15986 |
|
|
Module compiled
|
| 15987 |
|
|
Compiling verilog file "control.v"
|
| 15988 |
|
|
Module compiled
|
| 15989 |
|
|
Module compiled
|
| 15990 |
|
|
Compiling verilog file "maindcm.v"
|
| 15991 |
|
|
Module compiled
|
| 15992 |
|
|
Compiling verilog file "idecode.v"
|
| 15993 |
|
|
Module compiled
|
| 15994 |
|
|
Compiling verilog file "top.v"
|
| 15995 |
|
|
Module compiled
|
| 15996 |
|
|
Compiling verilog file "rcvr.v"
|
| 15997 |
|
|
Module compiled
|
| 15998 |
|
|
Compiling verilog file "txmit.v"
|
| 15999 |
|
|
Module compiled
|
| 16000 |
|
|
Compiling verilog file "uart.v"
|
| 16001 |
|
|
Module compiled
|
| 16002 |
|
|
Compiling verilog file "topbox.v"
|
| 16003 |
|
|
Module compiled
|
| 16004 |
|
|
No errors in compilation
|
| 16005 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 16006 |
|
|
|
| 16007 |
|
|
|
| 16008 |
|
|
=========================================================================
|
| 16009 |
|
|
* HDL Analysis *
|
| 16010 |
|
|
=========================================================================
|
| 16011 |
|
|
Analyzing top module .
|
| 16012 |
|
|
Module is correct for synthesis.
|
| 16013 |
|
|
|
| 16014 |
|
|
Set property "resynthesize = true" for unit .
|
| 16015 |
|
|
Analyzing module .
|
| 16016 |
|
|
Module is correct for synthesis.
|
| 16017 |
|
|
|
| 16018 |
|
|
Analyzing module .
|
| 16019 |
|
|
pClockFrequency = 50
|
| 16020 |
|
|
pRefreshFrequency = 100
|
| 16021 |
|
|
pUpperLimit = 125000
|
| 16022 |
|
|
pDividerCounterBits = 24
|
| 16023 |
|
|
Module is correct for synthesis.
|
| 16024 |
|
|
|
| 16025 |
|
|
Analyzing module .
|
| 16026 |
|
|
pInitialValue = 0
|
| 16027 |
|
|
pTimerWidth = 19
|
| 16028 |
|
|
pInitialTimerValue = 500000
|
| 16029 |
|
|
Module is correct for synthesis.
|
| 16030 |
|
|
|
| 16031 |
|
|
Analyzing module .
|
| 16032 |
|
|
Module is correct for synthesis.
|
| 16033 |
|
|
|
| 16034 |
|
|
Analyzing module .
|
| 16035 |
|
|
SIZE = 16
|
| 16036 |
|
|
Module is correct for synthesis.
|
| 16037 |
|
|
|
| 16038 |
|
|
Analyzing module .
|
| 16039 |
|
|
Module is correct for synthesis.
|
| 16040 |
|
|
|
| 16041 |
|
|
Analyzing module .
|
| 16042 |
|
|
SIZE = 12
|
| 16043 |
|
|
Module is correct for synthesis.
|
| 16044 |
|
|
|
| 16045 |
|
|
Analyzing module .
|
| 16046 |
|
|
Module is correct for synthesis.
|
| 16047 |
|
|
|
| 16048 |
|
|
Analyzing module .
|
| 16049 |
|
|
VALUE = 0000000000000001
|
| 16050 |
|
|
Module is correct for synthesis.
|
| 16051 |
|
|
|
| 16052 |
|
|
Analyzing module .
|
| 16053 |
|
|
Module is correct for synthesis.
|
| 16054 |
|
|
|
| 16055 |
|
|
Analyzing module .
|
| 16056 |
|
|
VALUE = 1111111111111111
|
| 16057 |
|
|
Module is correct for synthesis.
|
| 16058 |
|
|
|
| 16059 |
|
|
Analyzing module .
|
| 16060 |
|
|
Module is correct for synthesis.
|
| 16061 |
|
|
|
| 16062 |
|
|
Analyzing module .
|
| 16063 |
|
|
VALUE = 0000000000000000
|
| 16064 |
|
|
Module is correct for synthesis.
|
| 16065 |
|
|
|
| 16066 |
|
|
Analyzing module .
|
| 16067 |
|
|
Module is correct for synthesis.
|
| 16068 |
|
|
|
| 16069 |
|
|
Analyzing module .
|
| 16070 |
|
|
Module is correct for synthesis.
|
| 16071 |
|
|
|
| 16072 |
|
|
Analyzing module .
|
| 16073 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 16074 |
|
|
ERROR:Xst:899 - "control.v" line 48: The logic for does not match a known FF or Latch template.
|
| 16075 |
|
|
ERROR:Xst:899 - "control.v" line 46: The logic for does not match a known FF or Latch template.
|
| 16076 |
|
|
|
| 16077 |
|
|
Found 2 error(s). Aborting synthesis.
|
| 16078 |
|
|
-->
|
| 16079 |
|
|
|
| 16080 |
|
|
Total memory usage is 80468 kilobytes
|
| 16081 |
|
|
|
| 16082 |
|
|
Number of errors : 2 ( 0 filtered)
|
| 16083 |
|
|
Number of warnings : 1 ( 0 filtered)
|
| 16084 |
|
|
Number of infos : 0 ( 0 filtered)
|
| 16085 |
|
|
|
| 16086 |
|
|
ERROR: XST failed
|
| 16087 |
|
|
Process "Synthesize" did not complete.
|
| 16088 |
|
|
|
| 16089 |
|
|
|
| 16090 |
|
|
Project Navigator Auto-Make Log File
|
| 16091 |
|
|
-------------------------------------
|
| 16092 |
|
|
|
| 16093 |
|
|
|
| 16094 |
|
|
|
| 16095 |
|
|
|
| 16096 |
|
|
|
| 16097 |
|
|
|
| 16098 |
|
|
|
| 16099 |
|
|
|
| 16100 |
|
|
|
| 16101 |
|
|
|
| 16102 |
|
|
Started process "Synthesize".
|
| 16103 |
|
|
|
| 16104 |
|
|
|
| 16105 |
|
|
=========================================================================
|
| 16106 |
|
|
* HDL Compilation *
|
| 16107 |
|
|
=========================================================================
|
| 16108 |
|
|
Compiling verilog file "io.v"
|
| 16109 |
|
|
Module compiled
|
| 16110 |
|
|
Module compiled
|
| 16111 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 16112 |
|
|
Module compiled
|
| 16113 |
|
|
Compiling verilog file "misc.v"
|
| 16114 |
|
|
Module compiled
|
| 16115 |
|
|
Module compiled
|
| 16116 |
|
|
Module compiled
|
| 16117 |
|
|
Module compiled
|
| 16118 |
|
|
Module compiled
|
| 16119 |
|
|
Module compiled
|
| 16120 |
|
|
Compiling verilog file "alu.v"
|
| 16121 |
|
|
Module compiled
|
| 16122 |
|
|
Compiling verilog file "switchsync.v"
|
| 16123 |
|
|
Module compiled
|
| 16124 |
|
|
Compiling verilog file "jkff.v"
|
| 16125 |
|
|
Module compiled
|
| 16126 |
|
|
Compiling verilog file "control.v"
|
| 16127 |
|
|
Module compiled
|
| 16128 |
|
|
Module compiled
|
| 16129 |
|
|
Compiling verilog file "maindcm.v"
|
| 16130 |
|
|
Module compiled
|
| 16131 |
|
|
Compiling verilog file "idecode.v"
|
| 16132 |
|
|
Module compiled
|
| 16133 |
|
|
Compiling verilog file "top.v"
|
| 16134 |
|
|
Module compiled
|
| 16135 |
|
|
Compiling verilog file "rcvr.v"
|
| 16136 |
|
|
Module compiled
|
| 16137 |
|
|
Compiling verilog file "txmit.v"
|
| 16138 |
|
|
Module compiled
|
| 16139 |
|
|
Compiling verilog file "uart.v"
|
| 16140 |
|
|
Module compiled
|
| 16141 |
|
|
Compiling verilog file "topbox.v"
|
| 16142 |
|
|
Module compiled
|
| 16143 |
|
|
No errors in compilation
|
| 16144 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 16145 |
|
|
|
| 16146 |
|
|
|
| 16147 |
|
|
=========================================================================
|
| 16148 |
|
|
* HDL Analysis *
|
| 16149 |
|
|
=========================================================================
|
| 16150 |
|
|
Analyzing top module .
|
| 16151 |
|
|
Module is correct for synthesis.
|
| 16152 |
|
|
|
| 16153 |
|
|
Set property "resynthesize = true" for unit .
|
| 16154 |
|
|
Analyzing module .
|
| 16155 |
|
|
Module is correct for synthesis.
|
| 16156 |
|
|
|
| 16157 |
|
|
Analyzing module .
|
| 16158 |
|
|
pClockFrequency = 50
|
| 16159 |
|
|
pRefreshFrequency = 100
|
| 16160 |
|
|
pUpperLimit = 125000
|
| 16161 |
|
|
pDividerCounterBits = 24
|
| 16162 |
|
|
Module is correct for synthesis.
|
| 16163 |
|
|
|
| 16164 |
|
|
Analyzing module .
|
| 16165 |
|
|
pInitialValue = 0
|
| 16166 |
|
|
pTimerWidth = 19
|
| 16167 |
|
|
pInitialTimerValue = 500000
|
| 16168 |
|
|
Module is correct for synthesis.
|
| 16169 |
|
|
|
| 16170 |
|
|
Analyzing module .
|
| 16171 |
|
|
Module is correct for synthesis.
|
| 16172 |
|
|
|
| 16173 |
|
|
Analyzing module .
|
| 16174 |
|
|
SIZE = 16
|
| 16175 |
|
|
Module is correct for synthesis.
|
| 16176 |
|
|
|
| 16177 |
|
|
Analyzing module .
|
| 16178 |
|
|
Module is correct for synthesis.
|
| 16179 |
|
|
|
| 16180 |
|
|
Analyzing module .
|
| 16181 |
|
|
SIZE = 12
|
| 16182 |
|
|
Module is correct for synthesis.
|
| 16183 |
|
|
|
| 16184 |
|
|
Analyzing module .
|
| 16185 |
|
|
Module is correct for synthesis.
|
| 16186 |
|
|
|
| 16187 |
|
|
Analyzing module .
|
| 16188 |
|
|
VALUE = 0000000000000001
|
| 16189 |
|
|
Module is correct for synthesis.
|
| 16190 |
|
|
|
| 16191 |
|
|
Analyzing module .
|
| 16192 |
|
|
Module is correct for synthesis.
|
| 16193 |
|
|
|
| 16194 |
|
|
Analyzing module .
|
| 16195 |
|
|
VALUE = 1111111111111111
|
| 16196 |
|
|
Module is correct for synthesis.
|
| 16197 |
|
|
|
| 16198 |
|
|
Analyzing module .
|
| 16199 |
|
|
Module is correct for synthesis.
|
| 16200 |
|
|
|
| 16201 |
|
|
Analyzing module .
|
| 16202 |
|
|
VALUE = 0000000000000000
|
| 16203 |
|
|
Module is correct for synthesis.
|
| 16204 |
|
|
|
| 16205 |
|
|
Analyzing module .
|
| 16206 |
|
|
Module is correct for synthesis.
|
| 16207 |
|
|
|
| 16208 |
|
|
Analyzing module .
|
| 16209 |
|
|
Module is correct for synthesis.
|
| 16210 |
|
|
|
| 16211 |
|
|
Analyzing module .
|
| 16212 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 16213 |
|
|
ERROR:Xst:899 - "control.v" line 48: The logic for does not match a known FF or Latch template.
|
| 16214 |
|
|
ERROR:Xst:899 - "control.v" line 46: The logic for does not match a known FF or Latch template.
|
| 16215 |
|
|
|
| 16216 |
|
|
Found 2 error(s). Aborting synthesis.
|
| 16217 |
|
|
-->
|
| 16218 |
|
|
|
| 16219 |
|
|
Total memory usage is 80468 kilobytes
|
| 16220 |
|
|
|
| 16221 |
|
|
Number of errors : 2 ( 0 filtered)
|
| 16222 |
|
|
Number of warnings : 1 ( 0 filtered)
|
| 16223 |
|
|
Number of infos : 0 ( 0 filtered)
|
| 16224 |
|
|
|
| 16225 |
|
|
ERROR: XST failed
|
| 16226 |
|
|
Process "Synthesize" did not complete.
|
| 16227 |
|
|
|
| 16228 |
|
|
|
| 16229 |
|
|
Project Navigator Auto-Make Log File
|
| 16230 |
|
|
-------------------------------------
|
| 16231 |
|
|
|
| 16232 |
|
|
|
| 16233 |
|
|
|
| 16234 |
|
|
|
| 16235 |
|
|
|
| 16236 |
|
|
|
| 16237 |
|
|
|
| 16238 |
|
|
|
| 16239 |
|
|
|
| 16240 |
|
|
|
| 16241 |
|
|
Started process "Synthesize".
|
| 16242 |
|
|
|
| 16243 |
|
|
|
| 16244 |
|
|
=========================================================================
|
| 16245 |
|
|
* HDL Compilation *
|
| 16246 |
|
|
=========================================================================
|
| 16247 |
|
|
Compiling verilog file "io.v"
|
| 16248 |
|
|
Module compiled
|
| 16249 |
|
|
Module compiled
|
| 16250 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 16251 |
|
|
Module compiled
|
| 16252 |
|
|
Compiling verilog file "misc.v"
|
| 16253 |
|
|
Module compiled
|
| 16254 |
|
|
Module compiled
|
| 16255 |
|
|
Module compiled
|
| 16256 |
|
|
Module compiled
|
| 16257 |
|
|
Module compiled
|
| 16258 |
|
|
Module compiled
|
| 16259 |
|
|
Compiling verilog file "alu.v"
|
| 16260 |
|
|
Module compiled
|
| 16261 |
|
|
Compiling verilog file "switchsync.v"
|
| 16262 |
|
|
Module compiled
|
| 16263 |
|
|
Compiling verilog file "jkff.v"
|
| 16264 |
|
|
Module compiled
|
| 16265 |
|
|
Compiling verilog file "control.v"
|
| 16266 |
|
|
ERROR:HDLCompilers:28 - "control.v" line 67 'lodpc1' has not been declared
|
| 16267 |
|
|
Module compiled
|
| 16268 |
|
|
Module compiled
|
| 16269 |
|
|
Compiling verilog file "maindcm.v"
|
| 16270 |
|
|
Module compiled
|
| 16271 |
|
|
Compiling verilog file "idecode.v"
|
| 16272 |
|
|
Module compiled
|
| 16273 |
|
|
Compiling verilog file "top.v"
|
| 16274 |
|
|
Module compiled
|
| 16275 |
|
|
Compiling verilog file "rcvr.v"
|
| 16276 |
|
|
Module compiled
|
| 16277 |
|
|
Compiling verilog file "txmit.v"
|
| 16278 |
|
|
Module compiled
|
| 16279 |
|
|
Compiling verilog file "uart.v"
|
| 16280 |
|
|
Module compiled
|
| 16281 |
|
|
Compiling verilog file "topbox.v"
|
| 16282 |
|
|
Module compiled
|
| 16283 |
|
|
Analysis of file <"topbox.prj"> failed.
|
| 16284 |
|
|
-->
|
| 16285 |
|
|
|
| 16286 |
|
|
Total memory usage is 75092 kilobytes
|
| 16287 |
|
|
|
| 16288 |
|
|
Number of errors : 1 ( 0 filtered)
|
| 16289 |
|
|
Number of warnings : 0 ( 0 filtered)
|
| 16290 |
|
|
Number of infos : 0 ( 0 filtered)
|
| 16291 |
|
|
|
| 16292 |
|
|
ERROR: XST failed
|
| 16293 |
|
|
Process "Synthesize" did not complete.
|
| 16294 |
|
|
|
| 16295 |
|
|
|
| 16296 |
|
|
Project Navigator Auto-Make Log File
|
| 16297 |
|
|
-------------------------------------
|
| 16298 |
|
|
|
| 16299 |
|
|
|
| 16300 |
|
|
|
| 16301 |
|
|
|
| 16302 |
|
|
|
| 16303 |
|
|
|
| 16304 |
|
|
|
| 16305 |
|
|
|
| 16306 |
|
|
|
| 16307 |
|
|
|
| 16308 |
|
|
Started process "Synthesize".
|
| 16309 |
|
|
|
| 16310 |
|
|
|
| 16311 |
|
|
=========================================================================
|
| 16312 |
|
|
* HDL Compilation *
|
| 16313 |
|
|
=========================================================================
|
| 16314 |
|
|
Compiling verilog file "io.v"
|
| 16315 |
|
|
Module compiled
|
| 16316 |
|
|
Module compiled
|
| 16317 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 16318 |
|
|
Module compiled
|
| 16319 |
|
|
Compiling verilog file "misc.v"
|
| 16320 |
|
|
Module compiled
|
| 16321 |
|
|
Module compiled
|
| 16322 |
|
|
Module compiled
|
| 16323 |
|
|
Module compiled
|
| 16324 |
|
|
Module compiled
|
| 16325 |
|
|
Module compiled
|
| 16326 |
|
|
Compiling verilog file "alu.v"
|
| 16327 |
|
|
Module compiled
|
| 16328 |
|
|
Compiling verilog file "switchsync.v"
|
| 16329 |
|
|
Module compiled
|
| 16330 |
|
|
Compiling verilog file "jkff.v"
|
| 16331 |
|
|
Module compiled
|
| 16332 |
|
|
Compiling verilog file "control.v"
|
| 16333 |
|
|
Module compiled
|
| 16334 |
|
|
Module compiled
|
| 16335 |
|
|
Compiling verilog file "maindcm.v"
|
| 16336 |
|
|
Module compiled
|
| 16337 |
|
|
Compiling verilog file "idecode.v"
|
| 16338 |
|
|
Module compiled
|
| 16339 |
|
|
Compiling verilog file "top.v"
|
| 16340 |
|
|
Module compiled
|
| 16341 |
|
|
Compiling verilog file "rcvr.v"
|
| 16342 |
|
|
Module compiled
|
| 16343 |
|
|
Compiling verilog file "txmit.v"
|
| 16344 |
|
|
Module compiled
|
| 16345 |
|
|
Compiling verilog file "uart.v"
|
| 16346 |
|
|
Module compiled
|
| 16347 |
|
|
Compiling verilog file "topbox.v"
|
| 16348 |
|
|
Module compiled
|
| 16349 |
|
|
No errors in compilation
|
| 16350 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 16351 |
|
|
|
| 16352 |
|
|
|
| 16353 |
|
|
=========================================================================
|
| 16354 |
|
|
* HDL Analysis *
|
| 16355 |
|
|
=========================================================================
|
| 16356 |
|
|
Analyzing top module .
|
| 16357 |
|
|
Module is correct for synthesis.
|
| 16358 |
|
|
|
| 16359 |
|
|
Set property "resynthesize = true" for unit .
|
| 16360 |
|
|
Analyzing module .
|
| 16361 |
|
|
Module is correct for synthesis.
|
| 16362 |
|
|
|
| 16363 |
|
|
Analyzing module .
|
| 16364 |
|
|
pClockFrequency = 50
|
| 16365 |
|
|
pRefreshFrequency = 100
|
| 16366 |
|
|
pUpperLimit = 125000
|
| 16367 |
|
|
pDividerCounterBits = 24
|
| 16368 |
|
|
Module is correct for synthesis.
|
| 16369 |
|
|
|
| 16370 |
|
|
Analyzing module .
|
| 16371 |
|
|
pInitialValue = 0
|
| 16372 |
|
|
pTimerWidth = 19
|
| 16373 |
|
|
pInitialTimerValue = 500000
|
| 16374 |
|
|
Module is correct for synthesis.
|
| 16375 |
|
|
|
| 16376 |
|
|
Analyzing module .
|
| 16377 |
|
|
Module is correct for synthesis.
|
| 16378 |
|
|
|
| 16379 |
|
|
Analyzing module .
|
| 16380 |
|
|
SIZE = 16
|
| 16381 |
|
|
Module is correct for synthesis.
|
| 16382 |
|
|
|
| 16383 |
|
|
Analyzing module .
|
| 16384 |
|
|
Module is correct for synthesis.
|
| 16385 |
|
|
|
| 16386 |
|
|
Analyzing module .
|
| 16387 |
|
|
SIZE = 12
|
| 16388 |
|
|
Module is correct for synthesis.
|
| 16389 |
|
|
|
| 16390 |
|
|
Analyzing module .
|
| 16391 |
|
|
Module is correct for synthesis.
|
| 16392 |
|
|
|
| 16393 |
|
|
Analyzing module .
|
| 16394 |
|
|
VALUE = 0000000000000001
|
| 16395 |
|
|
Module is correct for synthesis.
|
| 16396 |
|
|
|
| 16397 |
|
|
Analyzing module .
|
| 16398 |
|
|
Module is correct for synthesis.
|
| 16399 |
|
|
|
| 16400 |
|
|
Analyzing module .
|
| 16401 |
|
|
VALUE = 1111111111111111
|
| 16402 |
|
|
Module is correct for synthesis.
|
| 16403 |
|
|
|
| 16404 |
|
|
Analyzing module .
|
| 16405 |
|
|
Module is correct for synthesis.
|
| 16406 |
|
|
|
| 16407 |
|
|
Analyzing module .
|
| 16408 |
|
|
VALUE = 0000000000000000
|
| 16409 |
|
|
Module is correct for synthesis.
|
| 16410 |
|
|
|
| 16411 |
|
|
Analyzing module .
|
| 16412 |
|
|
Module is correct for synthesis.
|
| 16413 |
|
|
|
| 16414 |
|
|
Analyzing module .
|
| 16415 |
|
|
Module is correct for synthesis.
|
| 16416 |
|
|
|
| 16417 |
|
|
Analyzing module .
|
| 16418 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 16419 |
|
|
Module is correct for synthesis.
|
| 16420 |
|
|
|
| 16421 |
|
|
Analyzing module .
|
| 16422 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 16423 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 16424 |
|
|
Module is correct for synthesis.
|
| 16425 |
|
|
|
| 16426 |
|
|
Analyzing module .
|
| 16427 |
|
|
Module is correct for synthesis.
|
| 16428 |
|
|
|
| 16429 |
|
|
Analyzing module .
|
| 16430 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16431 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16432 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16433 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16434 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16435 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16436 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16437 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16438 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16439 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16440 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16441 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16442 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16443 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 16444 |
|
|
Module is correct for synthesis.
|
| 16445 |
|
|
|
| 16446 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 16447 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 16448 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 16449 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 16450 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 16451 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 16452 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 16453 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 16454 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 16455 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 16456 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 16457 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 16458 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 16459 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 16460 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 16461 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 16462 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 16463 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 16464 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 16465 |
|
|
Analyzing module .
|
| 16466 |
|
|
Module is correct for synthesis.
|
| 16467 |
|
|
|
| 16468 |
|
|
Analyzing module .
|
| 16469 |
|
|
XTAL_CLK = 35000000
|
| 16470 |
|
|
BAUD = 9600
|
| 16471 |
|
|
CLK_DIV = 113
|
| 16472 |
|
|
CW = 8
|
| 16473 |
|
|
Module is correct for synthesis.
|
| 16474 |
|
|
|
| 16475 |
|
|
Analyzing module .
|
| 16476 |
|
|
Module is correct for synthesis.
|
| 16477 |
|
|
|
| 16478 |
|
|
Analyzing module .
|
| 16479 |
|
|
Module is correct for synthesis.
|
| 16480 |
|
|
|
| 16481 |
|
|
|
| 16482 |
|
|
=========================================================================
|
| 16483 |
|
|
* HDL Synthesis *
|
| 16484 |
|
|
=========================================================================
|
| 16485 |
|
|
|
| 16486 |
|
|
Synthesizing Unit .
|
| 16487 |
|
|
Related source file is "txmit.v".
|
| 16488 |
|
|
Found 1-bit register for signal .
|
| 16489 |
|
|
Found 1-bit register for signal .
|
| 16490 |
|
|
Found 1-bit register for signal .
|
| 16491 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 16492 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 16493 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 16494 |
|
|
Found 1-bit register for signal .
|
| 16495 |
|
|
Found 1-bit register for signal .
|
| 16496 |
|
|
Found 4-bit up counter for signal .
|
| 16497 |
|
|
Found 4-bit up counter for signal .
|
| 16498 |
|
|
Found 8-bit register for signal .
|
| 16499 |
|
|
Found 8-bit register for signal .
|
| 16500 |
|
|
Summary:
|
| 16501 |
|
|
inferred 2 Counter(s).
|
| 16502 |
|
|
inferred 21 D-type flip-flop(s).
|
| 16503 |
|
|
inferred 2 Comparator(s).
|
| 16504 |
|
|
inferred 1 Multiplexer(s).
|
| 16505 |
|
|
Unit synthesized.
|
| 16506 |
|
|
|
| 16507 |
|
|
|
| 16508 |
|
|
Synthesizing Unit .
|
| 16509 |
|
|
Related source file is "rcvr.v".
|
| 16510 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 16511 |
|
|
Found 1-bit register for signal .
|
| 16512 |
|
|
Found 1-bit register for signal .
|
| 16513 |
|
|
Found 1-bit register for signal .
|
| 16514 |
|
|
Found 8-bit tristate buffer for signal .
|
| 16515 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 16516 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 16517 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 16518 |
|
|
Found 1-bit register for signal .
|
| 16519 |
|
|
Found 1-bit register for signal .
|
| 16520 |
|
|
Found 4-bit register for signal .
|
| 16521 |
|
|
Found 4-bit up counter for signal .
|
| 16522 |
|
|
Found 8-bit register for signal .
|
| 16523 |
|
|
Found 7-bit register for signal >.
|
| 16524 |
|
|
Found 1-bit register for signal .
|
| 16525 |
|
|
Found 1-bit register for signal .
|
| 16526 |
|
|
Summary:
|
| 16527 |
|
|
inferred 1 Counter(s).
|
| 16528 |
|
|
inferred 26 D-type flip-flop(s).
|
| 16529 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 16530 |
|
|
inferred 1 Comparator(s).
|
| 16531 |
|
|
inferred 1 Multiplexer(s).
|
| 16532 |
|
|
inferred 8 Tristate(s).
|
| 16533 |
|
|
Unit synthesized.
|
| 16534 |
|
|
|
| 16535 |
|
|
|
| 16536 |
|
|
Synthesizing Unit .
|
| 16537 |
|
|
Related source file is "jkff.v".
|
| 16538 |
|
|
Found 1-bit register for signal .
|
| 16539 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 16540 |
|
|
Summary:
|
| 16541 |
|
|
inferred 1 D-type flip-flop(s).
|
| 16542 |
|
|
inferred 1 Multiplexer(s).
|
| 16543 |
|
|
Unit synthesized.
|
| 16544 |
|
|
|
| 16545 |
|
|
|
| 16546 |
|
|
Synthesizing Unit .
|
| 16547 |
|
|
Related source file is "switchsync.v".
|
| 16548 |
|
|
Found 1-bit register for signal .
|
| 16549 |
|
|
Found 1-bit register for signal .
|
| 16550 |
|
|
Summary:
|
| 16551 |
|
|
inferred 2 D-type flip-flop(s).
|
| 16552 |
|
|
Unit synthesized.
|
| 16553 |
|
|
|
| 16554 |
|
|
|
| 16555 |
|
|
Synthesizing Unit .
|
| 16556 |
|
|
Related source file is "maindcm.v".
|
| 16557 |
|
|
Unit synthesized.
|
| 16558 |
|
|
|
| 16559 |
|
|
|
| 16560 |
|
|
Synthesizing Unit .
|
| 16561 |
|
|
Related source file is "control.v".
|
| 16562 |
|
|
Found 1-bit register for signal .
|
| 16563 |
|
|
Found 1-bit register for signal .
|
| 16564 |
|
|
Found 3-bit up counter for signal .
|
| 16565 |
|
|
Summary:
|
| 16566 |
|
|
inferred 1 Counter(s).
|
| 16567 |
|
|
inferred 2 D-type flip-flop(s).
|
| 16568 |
|
|
Unit synthesized.
|
| 16569 |
|
|
|
| 16570 |
|
|
|
| 16571 |
|
|
Synthesizing Unit .
|
| 16572 |
|
|
Related source file is "misc.v".
|
| 16573 |
|
|
Found 16-bit tristate buffer for signal .
|
| 16574 |
|
|
Summary:
|
| 16575 |
|
|
inferred 16 Tristate(s).
|
| 16576 |
|
|
Unit synthesized.
|
| 16577 |
|
|
|
| 16578 |
|
|
|
| 16579 |
|
|
Synthesizing Unit .
|
| 16580 |
|
|
Related source file is "misc.v".
|
| 16581 |
|
|
Found 16-bit tristate buffer for signal .
|
| 16582 |
|
|
Summary:
|
| 16583 |
|
|
inferred 16 Tristate(s).
|
| 16584 |
|
|
Unit synthesized.
|
| 16585 |
|
|
|
| 16586 |
|
|
|
| 16587 |
|
|
Synthesizing Unit .
|
| 16588 |
|
|
Related source file is "misc.v".
|
| 16589 |
|
|
Found 16-bit tristate buffer for signal .
|
| 16590 |
|
|
Summary:
|
| 16591 |
|
|
inferred 16 Tristate(s).
|
| 16592 |
|
|
Unit synthesized.
|
| 16593 |
|
|
|
| 16594 |
|
|
|
| 16595 |
|
|
Synthesizing Unit .
|
| 16596 |
|
|
Related source file is "misc.v".
|
| 16597 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 16598 |
|
|
Found 16-bit tristate buffer for signal .
|
| 16599 |
|
|
Found 12-bit register for signal .
|
| 16600 |
|
|
Summary:
|
| 16601 |
|
|
inferred 12 D-type flip-flop(s).
|
| 16602 |
|
|
inferred 16 Tristate(s).
|
| 16603 |
|
|
Unit synthesized.
|
| 16604 |
|
|
|
| 16605 |
|
|
|
| 16606 |
|
|
Synthesizing Unit .
|
| 16607 |
|
|
Related source file is "idecode.v".
|
| 16608 |
|
|
Unit synthesized.
|
| 16609 |
|
|
|
| 16610 |
|
|
|
| 16611 |
|
|
Synthesizing Unit .
|
| 16612 |
|
|
Related source file is "control.v".
|
| 16613 |
|
|
Unit synthesized.
|
| 16614 |
|
|
|
| 16615 |
|
|
|
| 16616 |
|
|
Synthesizing Unit .
|
| 16617 |
|
|
Related source file is "alu.v".
|
| 16618 |
|
|
Found 16-bit tristate buffer for signal .
|
| 16619 |
|
|
Found 17-bit subtractor for signal <$AUX_109>.
|
| 16620 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 16621 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 16622 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 16623 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 16624 |
|
|
Summary:
|
| 16625 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 16626 |
|
|
inferred 16 Tristate(s).
|
| 16627 |
|
|
Unit synthesized.
|
| 16628 |
|
|
|
| 16629 |
|
|
|
| 16630 |
|
|
Synthesizing Unit .
|
| 16631 |
|
|
Related source file is "misc.v".
|
| 16632 |
|
|
Unit synthesized.
|
| 16633 |
|
|
|
| 16634 |
|
|
|
| 16635 |
|
|
Synthesizing Unit .
|
| 16636 |
|
|
Related source file is "misc.v".
|
| 16637 |
|
|
Unit synthesized.
|
| 16638 |
|
|
|
| 16639 |
|
|
|
| 16640 |
|
|
Synthesizing Unit .
|
| 16641 |
|
|
Related source file is "misc.v".
|
| 16642 |
|
|
Unit synthesized.
|
| 16643 |
|
|
|
| 16644 |
|
|
|
| 16645 |
|
|
Synthesizing Unit .
|
| 16646 |
|
|
Related source file is "misc.v".
|
| 16647 |
|
|
Unit synthesized.
|
| 16648 |
|
|
|
| 16649 |
|
|
|
| 16650 |
|
|
Synthesizing Unit .
|
| 16651 |
|
|
Related source file is "misc.v".
|
| 16652 |
|
|
Found 16-bit tristate buffer for signal .
|
| 16653 |
|
|
Found 16-bit register for signal .
|
| 16654 |
|
|
Summary:
|
| 16655 |
|
|
inferred 16 D-type flip-flop(s).
|
| 16656 |
|
|
inferred 16 Tristate(s).
|
| 16657 |
|
|
Unit synthesized.
|
| 16658 |
|
|
|
| 16659 |
|
|
|
| 16660 |
|
|
Synthesizing Unit .
|
| 16661 |
|
|
Related source file is "io.v".
|
| 16662 |
|
|
Found 1-bit register for signal .
|
| 16663 |
|
|
Found 1-bit register for signal .
|
| 16664 |
|
|
Found 1-bit register for signal .
|
| 16665 |
|
|
Found 1-bit register for signal .
|
| 16666 |
|
|
Found 1-bit register for signal .
|
| 16667 |
|
|
Found 1-bit register for signal .
|
| 16668 |
|
|
Found 19-bit down counter for signal .
|
| 16669 |
|
|
Found 1-bit register for signal .
|
| 16670 |
|
|
Found 1-bit xor2 for signal .
|
| 16671 |
|
|
Summary:
|
| 16672 |
|
|
inferred 1 Counter(s).
|
| 16673 |
|
|
inferred 7 D-type flip-flop(s).
|
| 16674 |
|
|
Unit synthesized.
|
| 16675 |
|
|
|
| 16676 |
|
|
|
| 16677 |
|
|
Synthesizing Unit .
|
| 16678 |
|
|
Related source file is "io.v".
|
| 16679 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 16680 |
|
|
Found 1-bit register for signal .
|
| 16681 |
|
|
Found 1-bit register for signal .
|
| 16682 |
|
|
Found 1-bit register for signal .
|
| 16683 |
|
|
Found 1-bit register for signal .
|
| 16684 |
|
|
Found 1-bit register for signal .
|
| 16685 |
|
|
Found 1-bit register for signal .
|
| 16686 |
|
|
Found 1-bit register for signal .
|
| 16687 |
|
|
Found 1-bit register for signal .
|
| 16688 |
|
|
Found 1-bit register for signal .
|
| 16689 |
|
|
Found 1-bit register for signal .
|
| 16690 |
|
|
Found 1-bit register for signal .
|
| 16691 |
|
|
Found 1-bit register for signal .
|
| 16692 |
|
|
Found 24-bit up counter for signal .
|
| 16693 |
|
|
Found 1-of-4 decoder for signal .
|
| 16694 |
|
|
Found 2-bit down counter for signal .
|
| 16695 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 16696 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 16697 |
|
|
Summary:
|
| 16698 |
|
|
inferred 1 ROM(s).
|
| 16699 |
|
|
inferred 2 Counter(s).
|
| 16700 |
|
|
inferred 12 D-type flip-flop(s).
|
| 16701 |
|
|
inferred 9 Multiplexer(s).
|
| 16702 |
|
|
inferred 1 Decoder(s).
|
| 16703 |
|
|
Unit synthesized.
|
| 16704 |
|
|
|
| 16705 |
|
|
|
| 16706 |
|
|
Synthesizing Unit .
|
| 16707 |
|
|
Related source file is "uart.v".
|
| 16708 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 16709 |
|
|
Found 1-bit register for signal .
|
| 16710 |
|
|
Found 8-bit up counter for signal .
|
| 16711 |
|
|
Found 1-bit register for signal .
|
| 16712 |
|
|
Summary:
|
| 16713 |
|
|
inferred 1 Counter(s).
|
| 16714 |
|
|
inferred 2 D-type flip-flop(s).
|
| 16715 |
|
|
inferred 1 Multiplexer(s).
|
| 16716 |
|
|
Unit synthesized.
|
| 16717 |
|
|
|
| 16718 |
|
|
|
| 16719 |
|
|
Synthesizing Unit .
|
| 16720 |
|
|
Related source file is "top.v".
|
| 16721 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 16722 |
|
|
Found 16-bit tristate buffer for signal .
|
| 16723 |
|
|
Found 1-bit register for signal .
|
| 16724 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 16725 |
|
|
Found 16-bit tristate buffer for signal .
|
| 16726 |
|
|
Found 1-bit register for signal .
|
| 16727 |
|
|
Found 1-bit register for signal .
|
| 16728 |
|
|
Found 1-bit register for signal .
|
| 16729 |
|
|
Summary:
|
| 16730 |
|
|
inferred 4 D-type flip-flop(s).
|
| 16731 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 16732 |
|
|
inferred 96 Tristate(s).
|
| 16733 |
|
|
Unit synthesized.
|
| 16734 |
|
|
|
| 16735 |
|
|
|
| 16736 |
|
|
Synthesizing Unit .
|
| 16737 |
|
|
Related source file is "FrontPanel.v".
|
| 16738 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 16739 |
|
|
Found finite state machine for signal .
|
| 16740 |
|
|
-----------------------------------------------------------------------
|
| 16741 |
|
|
| States | 6 |
|
| 16742 |
|
|
| Transitions | 6 |
|
| 16743 |
|
|
| Inputs | 0 |
|
| 16744 |
|
|
| Outputs | 12 |
|
| 16745 |
|
|
| Clock | clockin (rising_edge) |
|
| 16746 |
|
|
| Clock enable | select (positive) |
|
| 16747 |
|
|
| Reset | clear (positive) |
|
| 16748 |
|
|
| Reset type | asynchronous |
|
| 16749 |
|
|
| Reset State | 000001 |
|
| 16750 |
|
|
| Encoding | automatic |
|
| 16751 |
|
|
| Implementation | LUT |
|
| 16752 |
|
|
-----------------------------------------------------------------------
|
| 16753 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 16754 |
|
|
Found 4-bit register for signal .
|
| 16755 |
|
|
Found 16-bit register for signal .
|
| 16756 |
|
|
Summary:
|
| 16757 |
|
|
inferred 1 Finite State Machine(s).
|
| 16758 |
|
|
inferred 16 D-type flip-flop(s).
|
| 16759 |
|
|
inferred 16 Multiplexer(s).
|
| 16760 |
|
|
Unit synthesized.
|
| 16761 |
|
|
|
| 16762 |
|
|
|
| 16763 |
|
|
Synthesizing Unit .
|
| 16764 |
|
|
Related source file is "topbox.v".
|
| 16765 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 16766 |
|
|
Found 16-bit tristate buffer for signal .
|
| 16767 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 16768 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 16769 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 16770 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 16771 |
|
|
Found 4-bit register for signal .
|
| 16772 |
|
|
Found 1-bit register for signal .
|
| 16773 |
|
|
Found 1-bit register for signal .
|
| 16774 |
|
|
Found 16-bit register for signal .
|
| 16775 |
|
|
Summary:
|
| 16776 |
|
|
inferred 22 D-type flip-flop(s).
|
| 16777 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 16778 |
|
|
inferred 6 Multiplexer(s).
|
| 16779 |
|
|
inferred 48 Tristate(s).
|
| 16780 |
|
|
Unit synthesized.
|
| 16781 |
|
|
|
| 16782 |
|
|
|
| 16783 |
|
|
=========================================================================
|
| 16784 |
|
|
* Advanced HDL Synthesis *
|
| 16785 |
|
|
=========================================================================
|
| 16786 |
|
|
|
| 16787 |
|
|
Advanced RAM inference ...
|
| 16788 |
|
|
Advanced multiplier inference ...
|
| 16789 |
|
|
Advanced Registered AddSub inference ...
|
| 16790 |
|
|
Analyzing FSM for best encoding.
|
| 16791 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 16792 |
|
|
--------------------
|
| 16793 |
|
|
State | Encoding
|
| 16794 |
|
|
--------------------
|
| 16795 |
|
|
000001 | 100000
|
| 16796 |
|
|
000010 | 010000
|
| 16797 |
|
|
000100 | 001000
|
| 16798 |
|
|
001000 | 000100
|
| 16799 |
|
|
010000 | 000010
|
| 16800 |
|
|
100000 | 000001
|
| 16801 |
|
|
--------------------
|
| 16802 |
|
|
Dynamic shift register inference ...
|
| 16803 |
|
|
|
| 16804 |
|
|
=========================================================================
|
| 16805 |
|
|
HDL Synthesis Report
|
| 16806 |
|
|
|
| 16807 |
|
|
Macro Statistics
|
| 16808 |
|
|
# FSMs : 1
|
| 16809 |
|
|
# ROMs : 1
|
| 16810 |
|
|
16x7-bit ROM : 1
|
| 16811 |
|
|
# Adders/Subtractors : 5
|
| 16812 |
|
|
12-bit adder carry out : 1
|
| 16813 |
|
|
16-bit adder carry out : 1
|
| 16814 |
|
|
17-bit subtractor : 1
|
| 16815 |
|
|
4-bit adder : 2
|
| 16816 |
|
|
# Counters : 10
|
| 16817 |
|
|
19-bit down counter : 3
|
| 16818 |
|
|
2-bit down counter : 1
|
| 16819 |
|
|
24-bit up counter : 1
|
| 16820 |
|
|
3-bit up counter : 1
|
| 16821 |
|
|
4-bit up counter : 3
|
| 16822 |
|
|
8-bit up counter : 1
|
| 16823 |
|
|
# Registers : 138
|
| 16824 |
|
|
1-bit register : 125
|
| 16825 |
|
|
12-bit register : 4
|
| 16826 |
|
|
16-bit register : 4
|
| 16827 |
|
|
4-bit register : 3
|
| 16828 |
|
|
8-bit register : 2
|
| 16829 |
|
|
# Comparators : 3
|
| 16830 |
|
|
4-bit comparator greater : 2
|
| 16831 |
|
|
4-bit comparator less : 1
|
| 16832 |
|
|
# Multiplexers : 13
|
| 16833 |
|
|
1-bit 4-to-1 multiplexer : 10
|
| 16834 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 16835 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 16836 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 16837 |
|
|
# Decoders : 1
|
| 16838 |
|
|
1-of-4 decoder : 1
|
| 16839 |
|
|
# Tristates : 97
|
| 16840 |
|
|
1-bit tristate buffer : 80
|
| 16841 |
|
|
16-bit tristate buffer : 16
|
| 16842 |
|
|
8-bit tristate buffer : 1
|
| 16843 |
|
|
# Xors : 6
|
| 16844 |
|
|
1-bit xor2 : 5
|
| 16845 |
|
|
16-bit xor2 : 1
|
| 16846 |
|
|
|
| 16847 |
|
|
=========================================================================
|
| 16848 |
|
|
|
| 16849 |
|
|
=========================================================================
|
| 16850 |
|
|
* Low Level Synthesis *
|
| 16851 |
|
|
=========================================================================
|
| 16852 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 16853 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 16854 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 16855 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 16856 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 16857 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 16858 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 16859 |
|
|
|
| 16860 |
|
|
Optimizing unit ...
|
| 16861 |
|
|
|
| 16862 |
|
|
Optimizing unit ...
|
| 16863 |
|
|
|
| 16864 |
|
|
Optimizing unit ...
|
| 16865 |
|
|
|
| 16866 |
|
|
Optimizing unit ...
|
| 16867 |
|
|
|
| 16868 |
|
|
Optimizing unit ...
|
| 16869 |
|
|
|
| 16870 |
|
|
Optimizing unit ...
|
| 16871 |
|
|
|
| 16872 |
|
|
Optimizing unit ...
|
| 16873 |
|
|
|
| 16874 |
|
|
Optimizing unit ...
|
| 16875 |
|
|
|
| 16876 |
|
|
Optimizing unit ...
|
| 16877 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 16878 |
|
|
|
| 16879 |
|
|
Mapping all equations...
|
| 16880 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 16881 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 16882 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 16883 |
|
|
Building and optimizing final netlist ...
|
| 16884 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
|
| 16885 |
|
|
Forward register balancing over CPU/decoder/opdec78 of flipflops :
|
| 16886 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 16887 |
|
|
Forward register balancing over CPU/decoder/opxor1 of flipflops :
|
| 16888 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
|
| 16889 |
|
|
Forward register balancing over CPU/decoder/opand1 of flipflops :
|
| 16890 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 16891 |
|
|
Forward register balancing over CPU/decoder/opior1 of flipflops :
|
| 16892 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
|
| 16893 |
|
|
Forward register balancing over CPU/decoder/oplda1 of flipflops :
|
| 16894 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
|
| 16895 |
|
|
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
|
| 16896 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 16897 |
|
|
Forward register balancing over Ker571 of flipflops :
|
| 16898 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 16899 |
|
|
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
|
| 16900 |
|
|
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 16901 |
|
|
Forward register balancing over Ker2101 of flipflops :
|
| 16902 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 16903 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
|
| 16904 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
|
| 16905 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
|
| 16906 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 16907 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
|
| 16908 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
|
| 16909 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
|
| 16910 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 16911 |
|
|
Forward register balancing over CPU/msend9 of flipflops :
|
| 16912 |
|
|
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
|
| 16913 |
|
|
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
|
| 16914 |
|
|
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
|
| 16915 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
|
| 16916 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 16917 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
|
| 16918 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 16919 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
|
| 16920 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 16921 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
|
| 16922 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 16923 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
|
| 16924 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 16925 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
|
| 16926 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
|
| 16927 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
|
| 16928 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 16929 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
|
| 16930 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
|
| 16931 |
|
|
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
|
| 16932 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 16933 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
|
| 16934 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 16935 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
|
| 16936 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 16937 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
|
| 16938 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 16939 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
|
| 16940 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 16941 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
|
| 16942 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 16943 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
|
| 16944 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 16945 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
|
| 16946 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 16947 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
|
| 16948 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 16949 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
|
| 16950 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 16951 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
|
| 16952 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
|
| 16953 |
|
|
Forward register balancing over Ker2161_SW0 of flipflops :
|
| 16954 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 16955 |
|
|
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
|
| 16956 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 16957 |
|
|
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
|
| 16958 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
|
| 16959 |
|
|
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
|
| 16960 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 16961 |
|
|
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
|
| 16962 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 16963 |
|
|
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
|
| 16964 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 16965 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
|
| 16966 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 16967 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
|
| 16968 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 16969 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
|
| 16970 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 16971 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
|
| 16972 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 16973 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
|
| 16974 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
|
| 16975 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
|
| 16976 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 16977 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
|
| 16978 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 16979 |
|
|
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
|
| 16980 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
|
| 16981 |
|
|
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
|
| 16982 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 16983 |
|
|
Forward register balancing over Ker161_SW0 of flipflops :
|
| 16984 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 16985 |
|
|
Forward register balancing over CPU/decoder/opdec74 of flipflops :
|
| 16986 |
|
|
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
|
| 16987 |
|
|
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
|
| 16988 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 16989 |
|
|
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
|
| 16990 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 16991 |
|
|
Forward register balancing over CPU/ctl/sim/Ker71 of flipflops :
|
| 16992 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
|
| 16993 |
|
|
Forward register balancing over CPU/ctl/sim/_n00121 of flipflops :
|
| 16994 |
|
|
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
|
| 16995 |
|
|
Forward register balancing over CPU/ctl/sim/_n00111 of flipflops :
|
| 16996 |
|
|
CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2.
|
| 16997 |
|
|
Forward register balancing over CPU/ctl/sim/_n00101 of flipflops :
|
| 16998 |
|
|
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
|
| 16999 |
|
|
Forward register balancing over CPU/bus<0>__n0000<0>_N01_SW0 of flipflops :
|
| 17000 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
|
| 17001 |
|
|
Forward register balancing over CPU/decoder/opadd1 of flipflops :
|
| 17002 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 17003 |
|
|
Forward register balancing over CPU/decoder/opdec41 of flipflops :
|
| 17004 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
|
| 17005 |
|
|
Forward register balancing over CPU/decoder/opinc41 of flipflops :
|
| 17006 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
|
| 17007 |
|
|
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
|
| 17008 |
|
|
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 17009 |
|
|
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
|
| 17010 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 17011 |
|
|
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
|
| 17012 |
|
|
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 17013 |
|
|
Forward register balancing over Ker212_SW0 of flipflops :
|
| 17014 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
|
| 17015 |
|
|
Forward register balancing over CPU/decoder/opdec714 of flipflops :
|
| 17016 |
|
|
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
|
| 17017 |
|
|
Forward register balancing over CPU/ctl/sim/_n00151 of flipflops :
|
| 17018 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_1.
|
| 17019 |
|
|
Register equivalent to has been removed
|
| 17020 |
|
|
Register equivalent to has been removed
|
| 17021 |
|
|
Register equivalent to has been removed
|
| 17022 |
|
|
Register equivalent to has been removed
|
| 17023 |
|
|
Register equivalent to has been removed
|
| 17024 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
|
| 17025 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
|
| 17026 |
|
|
FlipFlop CPU/ctl/sim/_n00111_FRB has been replicated 7 time(s)
|
| 17027 |
|
|
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
|
| 17028 |
|
|
FlipFlop loadnow has been replicated 1 time(s)
|
| 17029 |
|
|
|
| 17030 |
|
|
=========================================================================
|
| 17031 |
|
|
* Final Report *
|
| 17032 |
|
|
=========================================================================
|
| 17033 |
|
|
|
| 17034 |
|
|
Device utilization summary:
|
| 17035 |
|
|
---------------------------
|
| 17036 |
|
|
|
| 17037 |
|
|
Selected Device : 3s200ft256-4
|
| 17038 |
|
|
|
| 17039 |
|
|
Number of Slices: 616 out of 1920 32%
|
| 17040 |
|
|
Number of Slice Flip Flops: 436 out of 3840 11%
|
| 17041 |
|
|
Number of 4 input LUTs: 1080 out of 3840 28%
|
| 17042 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 17043 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 17044 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 17045 |
|
|
|
| 17046 |
|
|
|
| 17047 |
|
|
=========================================================================
|
| 17048 |
|
|
TIMING REPORT
|
| 17049 |
|
|
|
| 17050 |
|
|
|
| 17051 |
|
|
Clock Information:
|
| 17052 |
|
|
------------------
|
| 17053 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 17054 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 17055 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 17056 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 436 |
|
| 17057 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 17058 |
|
|
|
| 17059 |
|
|
Timing Summary:
|
| 17060 |
|
|
---------------
|
| 17061 |
|
|
Speed Grade: -4
|
| 17062 |
|
|
|
| 17063 |
|
|
Minimum period: 13.584ns (Maximum Frequency: 73.618MHz)
|
| 17064 |
|
|
Minimum input arrival time before clock: 10.967ns
|
| 17065 |
|
|
Maximum output required time after clock: 23.172ns
|
| 17066 |
|
|
Maximum combinational path delay: 15.112ns
|
| 17067 |
|
|
|
| 17068 |
|
|
=========================================================================
|
| 17069 |
|
|
|
| 17070 |
|
|
|
| 17071 |
|
|
|
| 17072 |
|
|
|
| 17073 |
|
|
Started process "Translate".
|
| 17074 |
|
|
|
| 17075 |
|
|
|
| 17076 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 17077 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 17078 |
|
|
|
| 17079 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 17080 |
|
|
|
| 17081 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 17082 |
|
|
|
| 17083 |
|
|
Checking timing specifications ...
|
| 17084 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 17085 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 17086 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 17087 |
|
|
20.408000 nS HIGH 50.000000%
|
| 17088 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 17089 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 17090 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 17091 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 17092 |
|
|
from this group.
|
| 17093 |
|
|
Checking expanded design ...
|
| 17094 |
|
|
|
| 17095 |
|
|
NGDBUILD Design Results Summary:
|
| 17096 |
|
|
Number of errors: 0
|
| 17097 |
|
|
Number of warnings: 1
|
| 17098 |
|
|
|
| 17099 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 17100 |
|
|
|
| 17101 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 17102 |
|
|
|
| 17103 |
|
|
NGDBUILD done.
|
| 17104 |
|
|
|
| 17105 |
|
|
|
| 17106 |
|
|
|
| 17107 |
|
|
|
| 17108 |
|
|
Started process "Map".
|
| 17109 |
|
|
|
| 17110 |
|
|
Using target part "3s200ft256-4".
|
| 17111 |
|
|
Mapping design into LUTs...
|
| 17112 |
|
|
Running directed packing...
|
| 17113 |
|
|
Running delay-based LUT packing...
|
| 17114 |
|
|
Running timing-driven packing...
|
| 17115 |
|
|
|
| 17116 |
|
|
Phase 1.1
|
| 17117 |
|
|
Phase 1.1 (Checksum:98d1df) REAL time: 0 secs
|
| 17118 |
|
|
|
| 17119 |
|
|
Phase 2.31
|
| 17120 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs
|
| 17121 |
|
|
|
| 17122 |
|
|
Phase 3.2
|
| 17123 |
|
|
.
|
| 17124 |
|
|
|
| 17125 |
|
|
|
| 17126 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
|
| 17127 |
|
|
|
| 17128 |
|
|
Phase 4.4
|
| 17129 |
|
|
.................
|
| 17130 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs
|
| 17131 |
|
|
|
| 17132 |
|
|
Phase 5.28
|
| 17133 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs
|
| 17134 |
|
|
|
| 17135 |
|
|
Phase 6.8
|
| 17136 |
|
|
............................
|
| 17137 |
|
|
..............
|
| 17138 |
|
|
..........................
|
| 17139 |
|
|
...............
|
| 17140 |
|
|
...............
|
| 17141 |
|
|
Phase 6.8 (Checksum:abc08d) REAL time: 10 secs
|
| 17142 |
|
|
|
| 17143 |
|
|
Phase 7.29
|
| 17144 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs
|
| 17145 |
|
|
|
| 17146 |
|
|
Phase 8.5
|
| 17147 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs
|
| 17148 |
|
|
|
| 17149 |
|
|
Phase 9.18
|
| 17150 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 21 secs
|
| 17151 |
|
|
|
| 17152 |
|
|
Phase 10.5
|
| 17153 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 21 secs
|
| 17154 |
|
|
|
| 17155 |
|
|
|
| 17156 |
|
|
Design Summary:
|
| 17157 |
|
|
Number of errors: 0
|
| 17158 |
|
|
Number of warnings: 11
|
| 17159 |
|
|
Logic Utilization:
|
| 17160 |
|
|
Number of Slice Flip Flops: 410 out of 3,840 10%
|
| 17161 |
|
|
Number of 4 input LUTs: 1,130 out of 3,840 29%
|
| 17162 |
|
|
Logic Distribution:
|
| 17163 |
|
|
Number of occupied Slices: 654 out of 1,920 34%
|
| 17164 |
|
|
Number of Slices containing only related logic: 654 out of 654 100%
|
| 17165 |
|
|
Number of Slices containing unrelated logic: 0 out of 654 0%
|
| 17166 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 17167 |
|
|
Total Number 4 input LUTs: 1,134 out of 3,840 29%
|
| 17168 |
|
|
Number used as logic: 1,130
|
| 17169 |
|
|
Number used as a route-thru: 4
|
| 17170 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 17171 |
|
|
IOB Flip Flops: 26
|
| 17172 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 17173 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 17174 |
|
|
|
| 17175 |
|
|
Total equivalent gate count for design: 18,138
|
| 17176 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 17177 |
|
|
Peak Memory Usage: 133 MB
|
| 17178 |
|
|
|
| 17179 |
|
|
Mapping completed.
|
| 17180 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 17181 |
|
|
|
| 17182 |
|
|
|
| 17183 |
|
|
|
| 17184 |
|
|
|
| 17185 |
|
|
Started process "Place & Route".
|
| 17186 |
|
|
|
| 17187 |
|
|
|
| 17188 |
|
|
|
| 17189 |
|
|
|
| 17190 |
|
|
Constraints file: topbox.pcf.
|
| 17191 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 17192 |
|
|
C:/Xilinx71.
|
| 17193 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 17194 |
|
|
|
| 17195 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 17196 |
|
|
Celsius)
|
| 17197 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 17198 |
|
|
|
| 17199 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 17200 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 17201 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 17202 |
|
|
ps (24.00 Mhz).
|
| 17203 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 17204 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 17205 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 17206 |
|
|
(210.04 Mhz).
|
| 17207 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 17208 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 17209 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 17210 |
|
|
ps (24.00 Mhz).
|
| 17211 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 17212 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 17213 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 17214 |
|
|
(210.04 Mhz).
|
| 17215 |
|
|
|
| 17216 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 17217 |
|
|
|
| 17218 |
|
|
|
| 17219 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 17220 |
|
|
achieve better performance.
|
| 17221 |
|
|
|
| 17222 |
|
|
Device Utilization Summary:
|
| 17223 |
|
|
|
| 17224 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 17225 |
|
|
Number of DCMs 1 out of 4 25%
|
| 17226 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 17227 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 17228 |
|
|
|
| 17229 |
|
|
Number of Slices 654 out of 1920 34%
|
| 17230 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 17231 |
|
|
|
| 17232 |
|
|
|
| 17233 |
|
|
|
| 17234 |
|
|
Overall effort level (-ol): High (set by user)
|
| 17235 |
|
|
Router effort level (-rl): High (set by user)
|
| 17236 |
|
|
|
| 17237 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 17238 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 17239 |
|
|
|
| 17240 |
|
|
Starting Router
|
| 17241 |
|
|
|
| 17242 |
|
|
Phase 1: 4861 unrouted; REAL time: 4 secs
|
| 17243 |
|
|
|
| 17244 |
|
|
Phase 2: 4524 unrouted; REAL time: 4 secs
|
| 17245 |
|
|
|
| 17246 |
|
|
Phase 3: 2173 unrouted; REAL time: 5 secs
|
| 17247 |
|
|
|
| 17248 |
|
|
Phase 4: 2173 unrouted; (0) REAL time: 5 secs
|
| 17249 |
|
|
|
| 17250 |
|
|
Phase 5: 2173 unrouted; (0) REAL time: 5 secs
|
| 17251 |
|
|
|
| 17252 |
|
|
Phase 6: 2173 unrouted; (0) REAL time: 6 secs
|
| 17253 |
|
|
|
| 17254 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 9 secs
|
| 17255 |
|
|
|
| 17256 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 10 secs
|
| 17257 |
|
|
|
| 17258 |
|
|
|
| 17259 |
|
|
Total REAL time to Router completion: 10 secs
|
| 17260 |
|
|
Total CPU time to Router completion: 10 secs
|
| 17261 |
|
|
|
| 17262 |
|
|
Generating "PAR" statistics.
|
| 17263 |
|
|
|
| 17264 |
|
|
**************************
|
| 17265 |
|
|
Generating Clock Report
|
| 17266 |
|
|
**************************
|
| 17267 |
|
|
|
| 17268 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 17269 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 17270 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 17271 |
|
|
| clk | BUFGMUX2| No | 317 | 0.041 | 1.051 |
|
| 17272 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 17273 |
|
|
|
| 17274 |
|
|
Timing Score: 0
|
| 17275 |
|
|
|
| 17276 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 17277 |
|
|
This may be due to a setup or hold violation.
|
| 17278 |
|
|
|
| 17279 |
|
|
--------------------------------------------------------------------------------
|
| 17280 |
|
|
Constraint | Requested | Actual | Logic
|
| 17281 |
|
|
| | | Levels
|
| 17282 |
|
|
--------------------------------------------------------------------------------
|
| 17283 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 17284 |
|
|
HIGH 50% | | |
|
| 17285 |
|
|
--------------------------------------------------------------------------------
|
| 17286 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 26.908ns | 6
|
| 17287 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 17288 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 17289 |
|
|
--------------------------------------------------------------------------------
|
| 17290 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 38.772ns | 9
|
| 17291 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 17292 |
|
|
HIGH 50% | | |
|
| 17293 |
|
|
--------------------------------------------------------------------------------
|
| 17294 |
|
|
|
| 17295 |
|
|
|
| 17296 |
|
|
All constraints were met.
|
| 17297 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 17298 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 17299 |
|
|
Generating Pad Report.
|
| 17300 |
|
|
|
| 17301 |
|
|
All signals are completely routed.
|
| 17302 |
|
|
|
| 17303 |
|
|
Total REAL time to PAR completion: 12 secs
|
| 17304 |
|
|
Total CPU time to PAR completion: 11 secs
|
| 17305 |
|
|
|
| 17306 |
|
|
Peak Memory Usage: 93 MB
|
| 17307 |
|
|
|
| 17308 |
|
|
Placer: Not run.
|
| 17309 |
|
|
Routing: Completed - No errors found.
|
| 17310 |
|
|
Timing: Completed - No errors found.
|
| 17311 |
|
|
|
| 17312 |
|
|
Number of error messages: 0
|
| 17313 |
|
|
Number of warning messages: 4
|
| 17314 |
|
|
Number of info messages: 1
|
| 17315 |
|
|
|
| 17316 |
|
|
Writing design to file topbox.ncd
|
| 17317 |
|
|
|
| 17318 |
|
|
|
| 17319 |
|
|
|
| 17320 |
|
|
PAR done!
|
| 17321 |
|
|
|
| 17322 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 17323 |
|
|
|
| 17324 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 17325 |
|
|
C:/Xilinx71.
|
| 17326 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 17327 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 17328 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 17329 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 17330 |
|
|
ps (24.00 Mhz).
|
| 17331 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 17332 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 17333 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 17334 |
|
|
(210.04 Mhz).
|
| 17335 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 17336 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 17337 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 17338 |
|
|
ps (24.00 Mhz).
|
| 17339 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 17340 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 17341 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 17342 |
|
|
(210.04 Mhz).
|
| 17343 |
|
|
|
| 17344 |
|
|
Analysis completed Sat Sep 30 20:20:07 2006
|
| 17345 |
|
|
--------------------------------------------------------------------------------
|
| 17346 |
|
|
|
| 17347 |
|
|
Generating Report ...
|
| 17348 |
|
|
|
| 17349 |
|
|
Number of warnings: 4
|
| 17350 |
|
|
Total time: 3 secs
|
| 17351 |
|
|
|
| 17352 |
|
|
|
| 17353 |
|
|
|
| 17354 |
|
|
|
| 17355 |
|
|
|
| 17356 |
|
|
|
| 17357 |
|
|
|
| 17358 |
|
|
Started process "Generate Programming File".
|
| 17359 |
|
|
|
| 17360 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 17361 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 17362 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 17363 |
|
|
Interactive Data Sheet.
|
| 17364 |
|
|
|
| 17365 |
|
|
|
| 17366 |
|
|
Project Navigator Auto-Make Log File
|
| 17367 |
|
|
-------------------------------------
|
| 17368 |
|
|
|
| 17369 |
|
|
|
| 17370 |
|
|
|
| 17371 |
|
|
|
| 17372 |
|
|
|
| 17373 |
|
|
|
| 17374 |
|
|
|
| 17375 |
|
|
|
| 17376 |
|
|
|
| 17377 |
|
|
|
| 17378 |
|
|
Started process "Synthesize".
|
| 17379 |
|
|
|
| 17380 |
|
|
|
| 17381 |
|
|
=========================================================================
|
| 17382 |
|
|
* HDL Compilation *
|
| 17383 |
|
|
=========================================================================
|
| 17384 |
|
|
Compiling verilog file "io.v"
|
| 17385 |
|
|
Module compiled
|
| 17386 |
|
|
Module compiled
|
| 17387 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 17388 |
|
|
Module compiled
|
| 17389 |
|
|
Compiling verilog file "misc.v"
|
| 17390 |
|
|
Module compiled
|
| 17391 |
|
|
Module compiled
|
| 17392 |
|
|
Module compiled
|
| 17393 |
|
|
Module compiled
|
| 17394 |
|
|
Module compiled
|
| 17395 |
|
|
Module compiled
|
| 17396 |
|
|
Compiling verilog file "alu.v"
|
| 17397 |
|
|
Module compiled
|
| 17398 |
|
|
Compiling verilog file "switchsync.v"
|
| 17399 |
|
|
Module compiled
|
| 17400 |
|
|
Compiling verilog file "jkff.v"
|
| 17401 |
|
|
Module compiled
|
| 17402 |
|
|
Compiling verilog file "control.v"
|
| 17403 |
|
|
Module compiled
|
| 17404 |
|
|
Module compiled
|
| 17405 |
|
|
Compiling verilog file "maindcm.v"
|
| 17406 |
|
|
Module compiled
|
| 17407 |
|
|
Compiling verilog file "idecode.v"
|
| 17408 |
|
|
Module compiled
|
| 17409 |
|
|
Compiling verilog file "top.v"
|
| 17410 |
|
|
Module compiled
|
| 17411 |
|
|
Compiling verilog file "rcvr.v"
|
| 17412 |
|
|
Module compiled
|
| 17413 |
|
|
Compiling verilog file "txmit.v"
|
| 17414 |
|
|
Module compiled
|
| 17415 |
|
|
Compiling verilog file "uart.v"
|
| 17416 |
|
|
Module compiled
|
| 17417 |
|
|
Compiling verilog file "topbox.v"
|
| 17418 |
|
|
Module compiled
|
| 17419 |
|
|
No errors in compilation
|
| 17420 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 17421 |
|
|
|
| 17422 |
|
|
|
| 17423 |
|
|
=========================================================================
|
| 17424 |
|
|
* HDL Analysis *
|
| 17425 |
|
|
=========================================================================
|
| 17426 |
|
|
Analyzing top module .
|
| 17427 |
|
|
Module is correct for synthesis.
|
| 17428 |
|
|
|
| 17429 |
|
|
Set property "resynthesize = true" for unit .
|
| 17430 |
|
|
Analyzing module .
|
| 17431 |
|
|
Module is correct for synthesis.
|
| 17432 |
|
|
|
| 17433 |
|
|
Analyzing module .
|
| 17434 |
|
|
pClockFrequency = 50
|
| 17435 |
|
|
pRefreshFrequency = 100
|
| 17436 |
|
|
pUpperLimit = 125000
|
| 17437 |
|
|
pDividerCounterBits = 24
|
| 17438 |
|
|
Module is correct for synthesis.
|
| 17439 |
|
|
|
| 17440 |
|
|
Analyzing module .
|
| 17441 |
|
|
pInitialValue = 0
|
| 17442 |
|
|
pTimerWidth = 19
|
| 17443 |
|
|
pInitialTimerValue = 500000
|
| 17444 |
|
|
Module is correct for synthesis.
|
| 17445 |
|
|
|
| 17446 |
|
|
Analyzing module .
|
| 17447 |
|
|
Module is correct for synthesis.
|
| 17448 |
|
|
|
| 17449 |
|
|
Analyzing module .
|
| 17450 |
|
|
SIZE = 16
|
| 17451 |
|
|
Module is correct for synthesis.
|
| 17452 |
|
|
|
| 17453 |
|
|
Analyzing module .
|
| 17454 |
|
|
Module is correct for synthesis.
|
| 17455 |
|
|
|
| 17456 |
|
|
Analyzing module .
|
| 17457 |
|
|
SIZE = 12
|
| 17458 |
|
|
Module is correct for synthesis.
|
| 17459 |
|
|
|
| 17460 |
|
|
Analyzing module .
|
| 17461 |
|
|
Module is correct for synthesis.
|
| 17462 |
|
|
|
| 17463 |
|
|
Analyzing module .
|
| 17464 |
|
|
VALUE = 0000000000000001
|
| 17465 |
|
|
Module is correct for synthesis.
|
| 17466 |
|
|
|
| 17467 |
|
|
Analyzing module .
|
| 17468 |
|
|
Module is correct for synthesis.
|
| 17469 |
|
|
|
| 17470 |
|
|
Analyzing module .
|
| 17471 |
|
|
VALUE = 1111111111111111
|
| 17472 |
|
|
Module is correct for synthesis.
|
| 17473 |
|
|
|
| 17474 |
|
|
Analyzing module .
|
| 17475 |
|
|
Module is correct for synthesis.
|
| 17476 |
|
|
|
| 17477 |
|
|
Analyzing module .
|
| 17478 |
|
|
VALUE = 0000000000000000
|
| 17479 |
|
|
Module is correct for synthesis.
|
| 17480 |
|
|
|
| 17481 |
|
|
Analyzing module .
|
| 17482 |
|
|
Module is correct for synthesis.
|
| 17483 |
|
|
|
| 17484 |
|
|
Analyzing module .
|
| 17485 |
|
|
Module is correct for synthesis.
|
| 17486 |
|
|
|
| 17487 |
|
|
Analyzing module .
|
| 17488 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 17489 |
|
|
Module is correct for synthesis.
|
| 17490 |
|
|
|
| 17491 |
|
|
Analyzing module .
|
| 17492 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 17493 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 17494 |
|
|
Module is correct for synthesis.
|
| 17495 |
|
|
|
| 17496 |
|
|
Analyzing module .
|
| 17497 |
|
|
Module is correct for synthesis.
|
| 17498 |
|
|
|
| 17499 |
|
|
Analyzing module .
|
| 17500 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17501 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17502 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17503 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17504 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17505 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17506 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17507 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17508 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17509 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17510 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17511 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17512 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17513 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 17514 |
|
|
Module is correct for synthesis.
|
| 17515 |
|
|
|
| 17516 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 17517 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 17518 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 17519 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 17520 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 17521 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 17522 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 17523 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 17524 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 17525 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 17526 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 17527 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 17528 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 17529 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 17530 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 17531 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 17532 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 17533 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 17534 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 17535 |
|
|
Analyzing module .
|
| 17536 |
|
|
Module is correct for synthesis.
|
| 17537 |
|
|
|
| 17538 |
|
|
Analyzing module .
|
| 17539 |
|
|
XTAL_CLK = 35000000
|
| 17540 |
|
|
BAUD = 9600
|
| 17541 |
|
|
CLK_DIV = 113
|
| 17542 |
|
|
CW = 8
|
| 17543 |
|
|
Module is correct for synthesis.
|
| 17544 |
|
|
|
| 17545 |
|
|
Analyzing module .
|
| 17546 |
|
|
Module is correct for synthesis.
|
| 17547 |
|
|
|
| 17548 |
|
|
Analyzing module .
|
| 17549 |
|
|
Module is correct for synthesis.
|
| 17550 |
|
|
|
| 17551 |
|
|
|
| 17552 |
|
|
=========================================================================
|
| 17553 |
|
|
* HDL Synthesis *
|
| 17554 |
|
|
=========================================================================
|
| 17555 |
|
|
|
| 17556 |
|
|
Synthesizing Unit .
|
| 17557 |
|
|
Related source file is "txmit.v".
|
| 17558 |
|
|
Found 1-bit register for signal .
|
| 17559 |
|
|
Found 1-bit register for signal .
|
| 17560 |
|
|
Found 1-bit register for signal .
|
| 17561 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 17562 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 17563 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 17564 |
|
|
Found 1-bit register for signal .
|
| 17565 |
|
|
Found 1-bit register for signal .
|
| 17566 |
|
|
Found 4-bit up counter for signal .
|
| 17567 |
|
|
Found 4-bit up counter for signal .
|
| 17568 |
|
|
Found 8-bit register for signal .
|
| 17569 |
|
|
Found 8-bit register for signal .
|
| 17570 |
|
|
Summary:
|
| 17571 |
|
|
inferred 2 Counter(s).
|
| 17572 |
|
|
inferred 21 D-type flip-flop(s).
|
| 17573 |
|
|
inferred 2 Comparator(s).
|
| 17574 |
|
|
inferred 1 Multiplexer(s).
|
| 17575 |
|
|
Unit synthesized.
|
| 17576 |
|
|
|
| 17577 |
|
|
|
| 17578 |
|
|
Synthesizing Unit .
|
| 17579 |
|
|
Related source file is "rcvr.v".
|
| 17580 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 17581 |
|
|
Found 1-bit register for signal .
|
| 17582 |
|
|
Found 1-bit register for signal .
|
| 17583 |
|
|
Found 1-bit register for signal .
|
| 17584 |
|
|
Found 8-bit tristate buffer for signal .
|
| 17585 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 17586 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 17587 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 17588 |
|
|
Found 1-bit register for signal .
|
| 17589 |
|
|
Found 1-bit register for signal .
|
| 17590 |
|
|
Found 4-bit register for signal .
|
| 17591 |
|
|
Found 4-bit up counter for signal .
|
| 17592 |
|
|
Found 8-bit register for signal .
|
| 17593 |
|
|
Found 7-bit register for signal >.
|
| 17594 |
|
|
Found 1-bit register for signal .
|
| 17595 |
|
|
Found 1-bit register for signal .
|
| 17596 |
|
|
Summary:
|
| 17597 |
|
|
inferred 1 Counter(s).
|
| 17598 |
|
|
inferred 26 D-type flip-flop(s).
|
| 17599 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 17600 |
|
|
inferred 1 Comparator(s).
|
| 17601 |
|
|
inferred 1 Multiplexer(s).
|
| 17602 |
|
|
inferred 8 Tristate(s).
|
| 17603 |
|
|
Unit synthesized.
|
| 17604 |
|
|
|
| 17605 |
|
|
|
| 17606 |
|
|
Synthesizing Unit .
|
| 17607 |
|
|
Related source file is "jkff.v".
|
| 17608 |
|
|
Found 1-bit register for signal .
|
| 17609 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 17610 |
|
|
Summary:
|
| 17611 |
|
|
inferred 1 D-type flip-flop(s).
|
| 17612 |
|
|
inferred 1 Multiplexer(s).
|
| 17613 |
|
|
Unit synthesized.
|
| 17614 |
|
|
|
| 17615 |
|
|
|
| 17616 |
|
|
Synthesizing Unit .
|
| 17617 |
|
|
Related source file is "switchsync.v".
|
| 17618 |
|
|
Found 1-bit register for signal .
|
| 17619 |
|
|
Found 1-bit register for signal .
|
| 17620 |
|
|
Summary:
|
| 17621 |
|
|
inferred 2 D-type flip-flop(s).
|
| 17622 |
|
|
Unit synthesized.
|
| 17623 |
|
|
|
| 17624 |
|
|
|
| 17625 |
|
|
Synthesizing Unit .
|
| 17626 |
|
|
Related source file is "maindcm.v".
|
| 17627 |
|
|
Unit synthesized.
|
| 17628 |
|
|
|
| 17629 |
|
|
|
| 17630 |
|
|
Synthesizing Unit .
|
| 17631 |
|
|
Related source file is "control.v".
|
| 17632 |
|
|
Found 1-bit register for signal .
|
| 17633 |
|
|
Found 1-bit register for signal .
|
| 17634 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
|
| 17635 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
|
| 17636 |
|
|
Found 3-bit up counter for signal .
|
| 17637 |
|
|
Summary:
|
| 17638 |
|
|
inferred 1 Counter(s).
|
| 17639 |
|
|
inferred 2 D-type flip-flop(s).
|
| 17640 |
|
|
inferred 2 Multiplexer(s).
|
| 17641 |
|
|
Unit synthesized.
|
| 17642 |
|
|
|
| 17643 |
|
|
|
| 17644 |
|
|
Synthesizing Unit .
|
| 17645 |
|
|
Related source file is "misc.v".
|
| 17646 |
|
|
Found 16-bit tristate buffer for signal .
|
| 17647 |
|
|
Summary:
|
| 17648 |
|
|
inferred 16 Tristate(s).
|
| 17649 |
|
|
Unit synthesized.
|
| 17650 |
|
|
|
| 17651 |
|
|
|
| 17652 |
|
|
Synthesizing Unit .
|
| 17653 |
|
|
Related source file is "misc.v".
|
| 17654 |
|
|
Found 16-bit tristate buffer for signal .
|
| 17655 |
|
|
Summary:
|
| 17656 |
|
|
inferred 16 Tristate(s).
|
| 17657 |
|
|
Unit synthesized.
|
| 17658 |
|
|
|
| 17659 |
|
|
|
| 17660 |
|
|
Synthesizing Unit .
|
| 17661 |
|
|
Related source file is "misc.v".
|
| 17662 |
|
|
Found 16-bit tristate buffer for signal .
|
| 17663 |
|
|
Summary:
|
| 17664 |
|
|
inferred 16 Tristate(s).
|
| 17665 |
|
|
Unit synthesized.
|
| 17666 |
|
|
|
| 17667 |
|
|
|
| 17668 |
|
|
Synthesizing Unit .
|
| 17669 |
|
|
Related source file is "misc.v".
|
| 17670 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 17671 |
|
|
Found 16-bit tristate buffer for signal .
|
| 17672 |
|
|
Found 12-bit register for signal .
|
| 17673 |
|
|
Summary:
|
| 17674 |
|
|
inferred 12 D-type flip-flop(s).
|
| 17675 |
|
|
inferred 16 Tristate(s).
|
| 17676 |
|
|
Unit synthesized.
|
| 17677 |
|
|
|
| 17678 |
|
|
|
| 17679 |
|
|
Synthesizing Unit .
|
| 17680 |
|
|
Related source file is "idecode.v".
|
| 17681 |
|
|
Unit synthesized.
|
| 17682 |
|
|
|
| 17683 |
|
|
|
| 17684 |
|
|
Synthesizing Unit .
|
| 17685 |
|
|
Related source file is "control.v".
|
| 17686 |
|
|
Unit synthesized.
|
| 17687 |
|
|
|
| 17688 |
|
|
|
| 17689 |
|
|
Synthesizing Unit .
|
| 17690 |
|
|
Related source file is "alu.v".
|
| 17691 |
|
|
Found 16-bit tristate buffer for signal .
|
| 17692 |
|
|
Found 17-bit subtractor for signal <$AUX_109>.
|
| 17693 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 17694 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 17695 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 17696 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 17697 |
|
|
Summary:
|
| 17698 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 17699 |
|
|
inferred 16 Tristate(s).
|
| 17700 |
|
|
Unit synthesized.
|
| 17701 |
|
|
|
| 17702 |
|
|
|
| 17703 |
|
|
Synthesizing Unit .
|
| 17704 |
|
|
Related source file is "misc.v".
|
| 17705 |
|
|
Unit synthesized.
|
| 17706 |
|
|
|
| 17707 |
|
|
|
| 17708 |
|
|
Synthesizing Unit .
|
| 17709 |
|
|
Related source file is "misc.v".
|
| 17710 |
|
|
Unit synthesized.
|
| 17711 |
|
|
|
| 17712 |
|
|
|
| 17713 |
|
|
Synthesizing Unit .
|
| 17714 |
|
|
Related source file is "misc.v".
|
| 17715 |
|
|
Unit synthesized.
|
| 17716 |
|
|
|
| 17717 |
|
|
|
| 17718 |
|
|
Synthesizing Unit .
|
| 17719 |
|
|
Related source file is "misc.v".
|
| 17720 |
|
|
Unit synthesized.
|
| 17721 |
|
|
|
| 17722 |
|
|
|
| 17723 |
|
|
Synthesizing Unit .
|
| 17724 |
|
|
Related source file is "misc.v".
|
| 17725 |
|
|
Found 16-bit tristate buffer for signal .
|
| 17726 |
|
|
Found 16-bit register for signal .
|
| 17727 |
|
|
Summary:
|
| 17728 |
|
|
inferred 16 D-type flip-flop(s).
|
| 17729 |
|
|
inferred 16 Tristate(s).
|
| 17730 |
|
|
Unit synthesized.
|
| 17731 |
|
|
|
| 17732 |
|
|
|
| 17733 |
|
|
Synthesizing Unit .
|
| 17734 |
|
|
Related source file is "io.v".
|
| 17735 |
|
|
Found 1-bit register for signal .
|
| 17736 |
|
|
Found 1-bit register for signal .
|
| 17737 |
|
|
Found 1-bit register for signal .
|
| 17738 |
|
|
Found 1-bit register for signal .
|
| 17739 |
|
|
Found 1-bit register for signal .
|
| 17740 |
|
|
Found 1-bit register for signal .
|
| 17741 |
|
|
Found 19-bit down counter for signal .
|
| 17742 |
|
|
Found 1-bit register for signal .
|
| 17743 |
|
|
Found 1-bit xor2 for signal .
|
| 17744 |
|
|
Summary:
|
| 17745 |
|
|
inferred 1 Counter(s).
|
| 17746 |
|
|
inferred 7 D-type flip-flop(s).
|
| 17747 |
|
|
Unit synthesized.
|
| 17748 |
|
|
|
| 17749 |
|
|
|
| 17750 |
|
|
Synthesizing Unit .
|
| 17751 |
|
|
Related source file is "io.v".
|
| 17752 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 17753 |
|
|
Found 1-bit register for signal .
|
| 17754 |
|
|
Found 1-bit register for signal .
|
| 17755 |
|
|
Found 1-bit register for signal .
|
| 17756 |
|
|
Found 1-bit register for signal .
|
| 17757 |
|
|
Found 1-bit register for signal .
|
| 17758 |
|
|
Found 1-bit register for signal .
|
| 17759 |
|
|
Found 1-bit register for signal .
|
| 17760 |
|
|
Found 1-bit register for signal .
|
| 17761 |
|
|
Found 1-bit register for signal .
|
| 17762 |
|
|
Found 1-bit register for signal .
|
| 17763 |
|
|
Found 1-bit register for signal .
|
| 17764 |
|
|
Found 1-bit register for signal .
|
| 17765 |
|
|
Found 24-bit up counter for signal .
|
| 17766 |
|
|
Found 1-of-4 decoder for signal .
|
| 17767 |
|
|
Found 2-bit down counter for signal .
|
| 17768 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 17769 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 17770 |
|
|
Summary:
|
| 17771 |
|
|
inferred 1 ROM(s).
|
| 17772 |
|
|
inferred 2 Counter(s).
|
| 17773 |
|
|
inferred 12 D-type flip-flop(s).
|
| 17774 |
|
|
inferred 9 Multiplexer(s).
|
| 17775 |
|
|
inferred 1 Decoder(s).
|
| 17776 |
|
|
Unit synthesized.
|
| 17777 |
|
|
|
| 17778 |
|
|
|
| 17779 |
|
|
Synthesizing Unit .
|
| 17780 |
|
|
Related source file is "uart.v".
|
| 17781 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 17782 |
|
|
Found 1-bit register for signal .
|
| 17783 |
|
|
Found 8-bit up counter for signal .
|
| 17784 |
|
|
Found 1-bit register for signal .
|
| 17785 |
|
|
Summary:
|
| 17786 |
|
|
inferred 1 Counter(s).
|
| 17787 |
|
|
inferred 2 D-type flip-flop(s).
|
| 17788 |
|
|
inferred 1 Multiplexer(s).
|
| 17789 |
|
|
Unit synthesized.
|
| 17790 |
|
|
|
| 17791 |
|
|
|
| 17792 |
|
|
Synthesizing Unit .
|
| 17793 |
|
|
Related source file is "top.v".
|
| 17794 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 17795 |
|
|
Found 16-bit tristate buffer for signal .
|
| 17796 |
|
|
Found 1-bit register for signal .
|
| 17797 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 17798 |
|
|
Found 16-bit tristate buffer for signal .
|
| 17799 |
|
|
Found 1-bit register for signal .
|
| 17800 |
|
|
Found 1-bit register for signal .
|
| 17801 |
|
|
Found 1-bit register for signal .
|
| 17802 |
|
|
Summary:
|
| 17803 |
|
|
inferred 4 D-type flip-flop(s).
|
| 17804 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 17805 |
|
|
inferred 96 Tristate(s).
|
| 17806 |
|
|
Unit synthesized.
|
| 17807 |
|
|
|
| 17808 |
|
|
|
| 17809 |
|
|
Synthesizing Unit .
|
| 17810 |
|
|
Related source file is "FrontPanel.v".
|
| 17811 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 17812 |
|
|
Found finite state machine for signal .
|
| 17813 |
|
|
-----------------------------------------------------------------------
|
| 17814 |
|
|
| States | 6 |
|
| 17815 |
|
|
| Transitions | 6 |
|
| 17816 |
|
|
| Inputs | 0 |
|
| 17817 |
|
|
| Outputs | 12 |
|
| 17818 |
|
|
| Clock | clockin (rising_edge) |
|
| 17819 |
|
|
| Clock enable | select (positive) |
|
| 17820 |
|
|
| Reset | clear (positive) |
|
| 17821 |
|
|
| Reset type | asynchronous |
|
| 17822 |
|
|
| Reset State | 000001 |
|
| 17823 |
|
|
| Encoding | automatic |
|
| 17824 |
|
|
| Implementation | LUT |
|
| 17825 |
|
|
-----------------------------------------------------------------------
|
| 17826 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 17827 |
|
|
Found 4-bit register for signal .
|
| 17828 |
|
|
Found 16-bit register for signal .
|
| 17829 |
|
|
Summary:
|
| 17830 |
|
|
inferred 1 Finite State Machine(s).
|
| 17831 |
|
|
inferred 16 D-type flip-flop(s).
|
| 17832 |
|
|
inferred 16 Multiplexer(s).
|
| 17833 |
|
|
Unit synthesized.
|
| 17834 |
|
|
|
| 17835 |
|
|
|
| 17836 |
|
|
Synthesizing Unit .
|
| 17837 |
|
|
Related source file is "topbox.v".
|
| 17838 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 17839 |
|
|
Found 16-bit tristate buffer for signal .
|
| 17840 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 17841 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 17842 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 17843 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 17844 |
|
|
Found 4-bit register for signal .
|
| 17845 |
|
|
Found 1-bit register for signal .
|
| 17846 |
|
|
Found 1-bit register for signal .
|
| 17847 |
|
|
Found 16-bit register for signal .
|
| 17848 |
|
|
Summary:
|
| 17849 |
|
|
inferred 22 D-type flip-flop(s).
|
| 17850 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 17851 |
|
|
inferred 6 Multiplexer(s).
|
| 17852 |
|
|
inferred 48 Tristate(s).
|
| 17853 |
|
|
Unit synthesized.
|
| 17854 |
|
|
|
| 17855 |
|
|
|
| 17856 |
|
|
=========================================================================
|
| 17857 |
|
|
* Advanced HDL Synthesis *
|
| 17858 |
|
|
=========================================================================
|
| 17859 |
|
|
|
| 17860 |
|
|
Advanced RAM inference ...
|
| 17861 |
|
|
Advanced multiplier inference ...
|
| 17862 |
|
|
Advanced Registered AddSub inference ...
|
| 17863 |
|
|
Analyzing FSM for best encoding.
|
| 17864 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 17865 |
|
|
--------------------
|
| 17866 |
|
|
State | Encoding
|
| 17867 |
|
|
--------------------
|
| 17868 |
|
|
000001 | 100000
|
| 17869 |
|
|
000010 | 010000
|
| 17870 |
|
|
000100 | 001000
|
| 17871 |
|
|
001000 | 000100
|
| 17872 |
|
|
010000 | 000010
|
| 17873 |
|
|
100000 | 000001
|
| 17874 |
|
|
--------------------
|
| 17875 |
|
|
Dynamic shift register inference ...
|
| 17876 |
|
|
|
| 17877 |
|
|
=========================================================================
|
| 17878 |
|
|
HDL Synthesis Report
|
| 17879 |
|
|
|
| 17880 |
|
|
Macro Statistics
|
| 17881 |
|
|
# FSMs : 1
|
| 17882 |
|
|
# ROMs : 1
|
| 17883 |
|
|
16x7-bit ROM : 1
|
| 17884 |
|
|
# Adders/Subtractors : 5
|
| 17885 |
|
|
12-bit adder carry out : 1
|
| 17886 |
|
|
16-bit adder carry out : 1
|
| 17887 |
|
|
17-bit subtractor : 1
|
| 17888 |
|
|
4-bit adder : 2
|
| 17889 |
|
|
# Counters : 10
|
| 17890 |
|
|
19-bit down counter : 3
|
| 17891 |
|
|
2-bit down counter : 1
|
| 17892 |
|
|
24-bit up counter : 1
|
| 17893 |
|
|
3-bit up counter : 1
|
| 17894 |
|
|
4-bit up counter : 3
|
| 17895 |
|
|
8-bit up counter : 1
|
| 17896 |
|
|
# Registers : 138
|
| 17897 |
|
|
1-bit register : 125
|
| 17898 |
|
|
12-bit register : 4
|
| 17899 |
|
|
16-bit register : 4
|
| 17900 |
|
|
4-bit register : 3
|
| 17901 |
|
|
8-bit register : 2
|
| 17902 |
|
|
# Comparators : 3
|
| 17903 |
|
|
4-bit comparator greater : 2
|
| 17904 |
|
|
4-bit comparator less : 1
|
| 17905 |
|
|
# Multiplexers : 15
|
| 17906 |
|
|
1-bit 4-to-1 multiplexer : 12
|
| 17907 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 17908 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 17909 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 17910 |
|
|
# Decoders : 1
|
| 17911 |
|
|
1-of-4 decoder : 1
|
| 17912 |
|
|
# Tristates : 97
|
| 17913 |
|
|
1-bit tristate buffer : 80
|
| 17914 |
|
|
16-bit tristate buffer : 16
|
| 17915 |
|
|
8-bit tristate buffer : 1
|
| 17916 |
|
|
# Xors : 6
|
| 17917 |
|
|
1-bit xor2 : 5
|
| 17918 |
|
|
16-bit xor2 : 1
|
| 17919 |
|
|
|
| 17920 |
|
|
=========================================================================
|
| 17921 |
|
|
|
| 17922 |
|
|
=========================================================================
|
| 17923 |
|
|
* Low Level Synthesis *
|
| 17924 |
|
|
=========================================================================
|
| 17925 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 17926 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 17927 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 17928 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 17929 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 17930 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 17931 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 17932 |
|
|
|
| 17933 |
|
|
Optimizing unit ...
|
| 17934 |
|
|
|
| 17935 |
|
|
Optimizing unit ...
|
| 17936 |
|
|
|
| 17937 |
|
|
Optimizing unit ...
|
| 17938 |
|
|
|
| 17939 |
|
|
Optimizing unit ...
|
| 17940 |
|
|
|
| 17941 |
|
|
Optimizing unit ...
|
| 17942 |
|
|
|
| 17943 |
|
|
Optimizing unit ...
|
| 17944 |
|
|
|
| 17945 |
|
|
Optimizing unit ...
|
| 17946 |
|
|
|
| 17947 |
|
|
Optimizing unit ...
|
| 17948 |
|
|
|
| 17949 |
|
|
Optimizing unit ...
|
| 17950 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 17951 |
|
|
|
| 17952 |
|
|
Mapping all equations...
|
| 17953 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 17954 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 17955 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 17956 |
|
|
Building and optimizing final netlist ...
|
| 17957 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
|
| 17958 |
|
|
Forward register balancing over CPU/decoder/opdec78 of flipflops :
|
| 17959 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 17960 |
|
|
Forward register balancing over CPU/decoder/opxor1 of flipflops :
|
| 17961 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
|
| 17962 |
|
|
Forward register balancing over CPU/decoder/opand1 of flipflops :
|
| 17963 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 17964 |
|
|
Forward register balancing over CPU/decoder/opior1 of flipflops :
|
| 17965 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
|
| 17966 |
|
|
Forward register balancing over CPU/decoder/oplda1 of flipflops :
|
| 17967 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
|
| 17968 |
|
|
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
|
| 17969 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 17970 |
|
|
Forward register balancing over Ker571 of flipflops :
|
| 17971 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 17972 |
|
|
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
|
| 17973 |
|
|
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 17974 |
|
|
Forward register balancing over Ker2101 of flipflops :
|
| 17975 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 17976 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
|
| 17977 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
|
| 17978 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
|
| 17979 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 17980 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
|
| 17981 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
|
| 17982 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
|
| 17983 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 17984 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
|
| 17985 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 17986 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
|
| 17987 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 17988 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
|
| 17989 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 17990 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
|
| 17991 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 17992 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
|
| 17993 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 17994 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
|
| 17995 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
|
| 17996 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
|
| 17997 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 17998 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
|
| 17999 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
|
| 18000 |
|
|
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
|
| 18001 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 18002 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
|
| 18003 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 18004 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
|
| 18005 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 18006 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
|
| 18007 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 18008 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
|
| 18009 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 18010 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
|
| 18011 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 18012 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
|
| 18013 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 18014 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
|
| 18015 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 18016 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
|
| 18017 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 18018 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
|
| 18019 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 18020 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
|
| 18021 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
|
| 18022 |
|
|
Forward register balancing over Ker2161_SW0 of flipflops :
|
| 18023 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 18024 |
|
|
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
|
| 18025 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 18026 |
|
|
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
|
| 18027 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
|
| 18028 |
|
|
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
|
| 18029 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 18030 |
|
|
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
|
| 18031 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 18032 |
|
|
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
|
| 18033 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 18034 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
|
| 18035 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 18036 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
|
| 18037 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 18038 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
|
| 18039 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 18040 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
|
| 18041 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 18042 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
|
| 18043 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
|
| 18044 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
|
| 18045 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 18046 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
|
| 18047 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 18048 |
|
|
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
|
| 18049 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
|
| 18050 |
|
|
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
|
| 18051 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 18052 |
|
|
Forward register balancing over Ker161_SW0 of flipflops :
|
| 18053 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 18054 |
|
|
Forward register balancing over CPU/decoder/opdec74 of flipflops :
|
| 18055 |
|
|
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
|
| 18056 |
|
|
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
|
| 18057 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 18058 |
|
|
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
|
| 18059 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 18060 |
|
|
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
|
| 18061 |
|
|
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
|
| 18062 |
|
|
Forward register balancing over CPU/ctl/sim/Ker71 of flipflops :
|
| 18063 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
|
| 18064 |
|
|
Forward register balancing over CPU/ctl/sim/_n00131 of flipflops :
|
| 18065 |
|
|
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
|
| 18066 |
|
|
Forward register balancing over CPU/ctl/sim/_n00121 of flipflops :
|
| 18067 |
|
|
CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2.
|
| 18068 |
|
|
Forward register balancing over CPU/ctl/sim/_n00111 of flipflops :
|
| 18069 |
|
|
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
|
| 18070 |
|
|
Forward register balancing over CPU/bus<0>__n0000<0>_N01_SW0 of flipflops :
|
| 18071 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
|
| 18072 |
|
|
Forward register balancing over CPU/msend9 of flipflops :
|
| 18073 |
|
|
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
|
| 18074 |
|
|
Forward register balancing over CPU/decoder/opadd1 of flipflops :
|
| 18075 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 18076 |
|
|
Forward register balancing over CPU/decoder/opdec41 of flipflops :
|
| 18077 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
|
| 18078 |
|
|
Forward register balancing over CPU/decoder/opinc41 of flipflops :
|
| 18079 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
|
| 18080 |
|
|
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
|
| 18081 |
|
|
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 18082 |
|
|
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
|
| 18083 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 18084 |
|
|
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
|
| 18085 |
|
|
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 18086 |
|
|
Forward register balancing over Ker212_SW0 of flipflops :
|
| 18087 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
|
| 18088 |
|
|
Forward register balancing over CPU/decoder/opdec714 of flipflops :
|
| 18089 |
|
|
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
|
| 18090 |
|
|
Forward register balancing over CPU/ctl/sim/_n00161 of flipflops :
|
| 18091 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_1.
|
| 18092 |
|
|
Register equivalent to has been removed
|
| 18093 |
|
|
Register equivalent to has been removed
|
| 18094 |
|
|
Register equivalent to has been removed
|
| 18095 |
|
|
Register equivalent to has been removed
|
| 18096 |
|
|
Register equivalent to has been removed
|
| 18097 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
|
| 18098 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
|
| 18099 |
|
|
FlipFlop CPU/ctl/sim/_n00121_FRB has been replicated 7 time(s)
|
| 18100 |
|
|
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
|
| 18101 |
|
|
FlipFlop loadnow has been replicated 1 time(s)
|
| 18102 |
|
|
|
| 18103 |
|
|
=========================================================================
|
| 18104 |
|
|
* Final Report *
|
| 18105 |
|
|
=========================================================================
|
| 18106 |
|
|
|
| 18107 |
|
|
Device utilization summary:
|
| 18108 |
|
|
---------------------------
|
| 18109 |
|
|
|
| 18110 |
|
|
Selected Device : 3s200ft256-4
|
| 18111 |
|
|
|
| 18112 |
|
|
Number of Slices: 617 out of 1920 32%
|
| 18113 |
|
|
Number of Slice Flip Flops: 436 out of 3840 11%
|
| 18114 |
|
|
Number of 4 input LUTs: 1083 out of 3840 28%
|
| 18115 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 18116 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 18117 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 18118 |
|
|
|
| 18119 |
|
|
|
| 18120 |
|
|
=========================================================================
|
| 18121 |
|
|
TIMING REPORT
|
| 18122 |
|
|
|
| 18123 |
|
|
|
| 18124 |
|
|
Clock Information:
|
| 18125 |
|
|
------------------
|
| 18126 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 18127 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 18128 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 18129 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 436 |
|
| 18130 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 18131 |
|
|
|
| 18132 |
|
|
Timing Summary:
|
| 18133 |
|
|
---------------
|
| 18134 |
|
|
Speed Grade: -4
|
| 18135 |
|
|
|
| 18136 |
|
|
Minimum period: 13.516ns (Maximum Frequency: 73.984MHz)
|
| 18137 |
|
|
Minimum input arrival time before clock: 10.967ns
|
| 18138 |
|
|
Maximum output required time after clock: 23.076ns
|
| 18139 |
|
|
Maximum combinational path delay: 15.112ns
|
| 18140 |
|
|
|
| 18141 |
|
|
=========================================================================
|
| 18142 |
|
|
|
| 18143 |
|
|
|
| 18144 |
|
|
|
| 18145 |
|
|
|
| 18146 |
|
|
Started process "Translate".
|
| 18147 |
|
|
|
| 18148 |
|
|
|
| 18149 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 18150 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 18151 |
|
|
|
| 18152 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 18153 |
|
|
|
| 18154 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 18155 |
|
|
|
| 18156 |
|
|
Checking timing specifications ...
|
| 18157 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 18158 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 18159 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 18160 |
|
|
20.408000 nS HIGH 50.000000%
|
| 18161 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 18162 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 18163 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 18164 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 18165 |
|
|
from this group.
|
| 18166 |
|
|
Checking expanded design ...
|
| 18167 |
|
|
|
| 18168 |
|
|
NGDBUILD Design Results Summary:
|
| 18169 |
|
|
Number of errors: 0
|
| 18170 |
|
|
Number of warnings: 1
|
| 18171 |
|
|
|
| 18172 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 18173 |
|
|
|
| 18174 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 18175 |
|
|
|
| 18176 |
|
|
NGDBUILD done.
|
| 18177 |
|
|
|
| 18178 |
|
|
|
| 18179 |
|
|
|
| 18180 |
|
|
|
| 18181 |
|
|
Started process "Map".
|
| 18182 |
|
|
|
| 18183 |
|
|
Using target part "3s200ft256-4".
|
| 18184 |
|
|
Mapping design into LUTs...
|
| 18185 |
|
|
Running directed packing...
|
| 18186 |
|
|
Running delay-based LUT packing...
|
| 18187 |
|
|
Running timing-driven packing...
|
| 18188 |
|
|
|
| 18189 |
|
|
Phase 1.1
|
| 18190 |
|
|
Phase 1.1 (Checksum:98d1ef) REAL time: 0 secs
|
| 18191 |
|
|
|
| 18192 |
|
|
Phase 2.31
|
| 18193 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs
|
| 18194 |
|
|
|
| 18195 |
|
|
Phase 3.2
|
| 18196 |
|
|
.
|
| 18197 |
|
|
|
| 18198 |
|
|
|
| 18199 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
|
| 18200 |
|
|
|
| 18201 |
|
|
Phase 4.4
|
| 18202 |
|
|
......................
|
| 18203 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs
|
| 18204 |
|
|
|
| 18205 |
|
|
Phase 5.28
|
| 18206 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs
|
| 18207 |
|
|
|
| 18208 |
|
|
Phase 6.8
|
| 18209 |
|
|
.......................................
|
| 18210 |
|
|
......................
|
| 18211 |
|
|
........................................
|
| 18212 |
|
|
................
|
| 18213 |
|
|
...............
|
| 18214 |
|
|
Phase 6.8 (Checksum:ac1e2f) REAL time: 11 secs
|
| 18215 |
|
|
|
| 18216 |
|
|
Phase 7.29
|
| 18217 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 11 secs
|
| 18218 |
|
|
|
| 18219 |
|
|
Phase 8.5
|
| 18220 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 11 secs
|
| 18221 |
|
|
|
| 18222 |
|
|
Phase 9.18
|
| 18223 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 21 secs
|
| 18224 |
|
|
|
| 18225 |
|
|
Phase 10.5
|
| 18226 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 21 secs
|
| 18227 |
|
|
|
| 18228 |
|
|
|
| 18229 |
|
|
Design Summary:
|
| 18230 |
|
|
Number of errors: 0
|
| 18231 |
|
|
Number of warnings: 11
|
| 18232 |
|
|
Logic Utilization:
|
| 18233 |
|
|
Number of Slice Flip Flops: 410 out of 3,840 10%
|
| 18234 |
|
|
Number of 4 input LUTs: 1,133 out of 3,840 29%
|
| 18235 |
|
|
Logic Distribution:
|
| 18236 |
|
|
Number of occupied Slices: 677 out of 1,920 35%
|
| 18237 |
|
|
Number of Slices containing only related logic: 677 out of 677 100%
|
| 18238 |
|
|
Number of Slices containing unrelated logic: 0 out of 677 0%
|
| 18239 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 18240 |
|
|
Total Number 4 input LUTs: 1,137 out of 3,840 29%
|
| 18241 |
|
|
Number used as logic: 1,133
|
| 18242 |
|
|
Number used as a route-thru: 4
|
| 18243 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 18244 |
|
|
IOB Flip Flops: 26
|
| 18245 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 18246 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 18247 |
|
|
|
| 18248 |
|
|
Total equivalent gate count for design: 18,156
|
| 18249 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 18250 |
|
|
Peak Memory Usage: 133 MB
|
| 18251 |
|
|
|
| 18252 |
|
|
Mapping completed.
|
| 18253 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 18254 |
|
|
|
| 18255 |
|
|
|
| 18256 |
|
|
|
| 18257 |
|
|
|
| 18258 |
|
|
Started process "Place & Route".
|
| 18259 |
|
|
|
| 18260 |
|
|
|
| 18261 |
|
|
|
| 18262 |
|
|
|
| 18263 |
|
|
Constraints file: topbox.pcf.
|
| 18264 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 18265 |
|
|
C:/Xilinx71.
|
| 18266 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 18267 |
|
|
|
| 18268 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 18269 |
|
|
Celsius)
|
| 18270 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 18271 |
|
|
|
| 18272 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 18273 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 18274 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 18275 |
|
|
ps (24.00 Mhz).
|
| 18276 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 18277 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 18278 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 18279 |
|
|
(210.04 Mhz).
|
| 18280 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 18281 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 18282 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 18283 |
|
|
ps (24.00 Mhz).
|
| 18284 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 18285 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 18286 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 18287 |
|
|
(210.04 Mhz).
|
| 18288 |
|
|
|
| 18289 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 18290 |
|
|
|
| 18291 |
|
|
|
| 18292 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 18293 |
|
|
achieve better performance.
|
| 18294 |
|
|
|
| 18295 |
|
|
Device Utilization Summary:
|
| 18296 |
|
|
|
| 18297 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 18298 |
|
|
Number of DCMs 1 out of 4 25%
|
| 18299 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 18300 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 18301 |
|
|
|
| 18302 |
|
|
Number of Slices 677 out of 1920 35%
|
| 18303 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 18304 |
|
|
|
| 18305 |
|
|
|
| 18306 |
|
|
|
| 18307 |
|
|
Overall effort level (-ol): High (set by user)
|
| 18308 |
|
|
Router effort level (-rl): High (set by user)
|
| 18309 |
|
|
|
| 18310 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 18311 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 18312 |
|
|
|
| 18313 |
|
|
Starting Router
|
| 18314 |
|
|
|
| 18315 |
|
|
Phase 1: 4958 unrouted; REAL time: 4 secs
|
| 18316 |
|
|
|
| 18317 |
|
|
Phase 2: 4588 unrouted; REAL time: 4 secs
|
| 18318 |
|
|
|
| 18319 |
|
|
Phase 3: 2217 unrouted; REAL time: 5 secs
|
| 18320 |
|
|
|
| 18321 |
|
|
Phase 4: 2217 unrouted; (0) REAL time: 6 secs
|
| 18322 |
|
|
|
| 18323 |
|
|
Phase 5: 2217 unrouted; (0) REAL time: 6 secs
|
| 18324 |
|
|
|
| 18325 |
|
|
Phase 6: 2217 unrouted; (0) REAL time: 6 secs
|
| 18326 |
|
|
|
| 18327 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 13 secs
|
| 18328 |
|
|
|
| 18329 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 14 secs
|
| 18330 |
|
|
|
| 18331 |
|
|
|
| 18332 |
|
|
Total REAL time to Router completion: 14 secs
|
| 18333 |
|
|
Total CPU time to Router completion: 14 secs
|
| 18334 |
|
|
|
| 18335 |
|
|
Generating "PAR" statistics.
|
| 18336 |
|
|
|
| 18337 |
|
|
**************************
|
| 18338 |
|
|
Generating Clock Report
|
| 18339 |
|
|
**************************
|
| 18340 |
|
|
|
| 18341 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 18342 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 18343 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 18344 |
|
|
| clk | BUFGMUX2| No | 350 | 0.041 | 1.051 |
|
| 18345 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 18346 |
|
|
|
| 18347 |
|
|
Timing Score: 0
|
| 18348 |
|
|
|
| 18349 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 18350 |
|
|
This may be due to a setup or hold violation.
|
| 18351 |
|
|
|
| 18352 |
|
|
--------------------------------------------------------------------------------
|
| 18353 |
|
|
Constraint | Requested | Actual | Logic
|
| 18354 |
|
|
| | | Levels
|
| 18355 |
|
|
--------------------------------------------------------------------------------
|
| 18356 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 18357 |
|
|
HIGH 50% | | |
|
| 18358 |
|
|
--------------------------------------------------------------------------------
|
| 18359 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 31.382ns | 6
|
| 18360 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 18361 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 18362 |
|
|
--------------------------------------------------------------------------------
|
| 18363 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 40.278ns | 11
|
| 18364 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 18365 |
|
|
HIGH 50% | | |
|
| 18366 |
|
|
--------------------------------------------------------------------------------
|
| 18367 |
|
|
|
| 18368 |
|
|
|
| 18369 |
|
|
All constraints were met.
|
| 18370 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 18371 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 18372 |
|
|
Generating Pad Report.
|
| 18373 |
|
|
|
| 18374 |
|
|
All signals are completely routed.
|
| 18375 |
|
|
|
| 18376 |
|
|
Total REAL time to PAR completion: 15 secs
|
| 18377 |
|
|
Total CPU time to PAR completion: 15 secs
|
| 18378 |
|
|
|
| 18379 |
|
|
Peak Memory Usage: 95 MB
|
| 18380 |
|
|
|
| 18381 |
|
|
Placer: Not run.
|
| 18382 |
|
|
Routing: Completed - No errors found.
|
| 18383 |
|
|
Timing: Completed - No errors found.
|
| 18384 |
|
|
|
| 18385 |
|
|
Number of error messages: 0
|
| 18386 |
|
|
Number of warning messages: 4
|
| 18387 |
|
|
Number of info messages: 1
|
| 18388 |
|
|
|
| 18389 |
|
|
Writing design to file topbox.ncd
|
| 18390 |
|
|
|
| 18391 |
|
|
|
| 18392 |
|
|
|
| 18393 |
|
|
PAR done!
|
| 18394 |
|
|
|
| 18395 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 18396 |
|
|
|
| 18397 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 18398 |
|
|
C:/Xilinx71.
|
| 18399 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 18400 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 18401 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 18402 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 18403 |
|
|
ps (24.00 Mhz).
|
| 18404 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 18405 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 18406 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 18407 |
|
|
(210.04 Mhz).
|
| 18408 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 18409 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 18410 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 18411 |
|
|
ps (24.00 Mhz).
|
| 18412 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 18413 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 18414 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 18415 |
|
|
(210.04 Mhz).
|
| 18416 |
|
|
|
| 18417 |
|
|
Analysis completed Sat Sep 30 20:24:47 2006
|
| 18418 |
|
|
--------------------------------------------------------------------------------
|
| 18419 |
|
|
|
| 18420 |
|
|
Generating Report ...
|
| 18421 |
|
|
|
| 18422 |
|
|
Number of warnings: 4
|
| 18423 |
|
|
Total time: 3 secs
|
| 18424 |
|
|
|
| 18425 |
|
|
|
| 18426 |
|
|
|
| 18427 |
|
|
|
| 18428 |
|
|
|
| 18429 |
|
|
|
| 18430 |
|
|
|
| 18431 |
|
|
Started process "Generate Programming File".
|
| 18432 |
|
|
|
| 18433 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 18434 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 18435 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 18436 |
|
|
Interactive Data Sheet.
|
| 18437 |
|
|
|
| 18438 |
|
|
|
| 18439 |
|
|
Project Navigator Auto-Make Log File
|
| 18440 |
|
|
-------------------------------------
|
| 18441 |
|
|
|
| 18442 |
|
|
|
| 18443 |
|
|
|
| 18444 |
|
|
|
| 18445 |
|
|
|
| 18446 |
|
|
|
| 18447 |
|
|
|
| 18448 |
|
|
|
| 18449 |
|
|
|
| 18450 |
|
|
|
| 18451 |
|
|
Started process "Synthesize".
|
| 18452 |
|
|
|
| 18453 |
|
|
|
| 18454 |
|
|
=========================================================================
|
| 18455 |
|
|
* HDL Compilation *
|
| 18456 |
|
|
=========================================================================
|
| 18457 |
|
|
Compiling verilog file "io.v"
|
| 18458 |
|
|
Module compiled
|
| 18459 |
|
|
Module compiled
|
| 18460 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 18461 |
|
|
Module compiled
|
| 18462 |
|
|
Compiling verilog file "misc.v"
|
| 18463 |
|
|
Module compiled
|
| 18464 |
|
|
Module compiled
|
| 18465 |
|
|
Module compiled
|
| 18466 |
|
|
Module compiled
|
| 18467 |
|
|
Module compiled
|
| 18468 |
|
|
Module compiled
|
| 18469 |
|
|
Compiling verilog file "alu.v"
|
| 18470 |
|
|
Module compiled
|
| 18471 |
|
|
Compiling verilog file "switchsync.v"
|
| 18472 |
|
|
Module compiled
|
| 18473 |
|
|
Compiling verilog file "jkff.v"
|
| 18474 |
|
|
Module compiled
|
| 18475 |
|
|
Compiling verilog file "control.v"
|
| 18476 |
|
|
Module compiled
|
| 18477 |
|
|
Module compiled
|
| 18478 |
|
|
Compiling verilog file "maindcm.v"
|
| 18479 |
|
|
Module compiled
|
| 18480 |
|
|
Compiling verilog file "idecode.v"
|
| 18481 |
|
|
Module compiled
|
| 18482 |
|
|
Compiling verilog file "top.v"
|
| 18483 |
|
|
Module compiled
|
| 18484 |
|
|
Compiling verilog file "rcvr.v"
|
| 18485 |
|
|
Module compiled
|
| 18486 |
|
|
Compiling verilog file "txmit.v"
|
| 18487 |
|
|
Module compiled
|
| 18488 |
|
|
Compiling verilog file "uart.v"
|
| 18489 |
|
|
Module compiled
|
| 18490 |
|
|
Compiling verilog file "topbox.v"
|
| 18491 |
|
|
Module compiled
|
| 18492 |
|
|
No errors in compilation
|
| 18493 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 18494 |
|
|
|
| 18495 |
|
|
|
| 18496 |
|
|
=========================================================================
|
| 18497 |
|
|
* HDL Analysis *
|
| 18498 |
|
|
=========================================================================
|
| 18499 |
|
|
Analyzing top module .
|
| 18500 |
|
|
Module is correct for synthesis.
|
| 18501 |
|
|
|
| 18502 |
|
|
Set property "resynthesize = true" for unit .
|
| 18503 |
|
|
Analyzing module .
|
| 18504 |
|
|
Module is correct for synthesis.
|
| 18505 |
|
|
|
| 18506 |
|
|
Analyzing module .
|
| 18507 |
|
|
pClockFrequency = 50
|
| 18508 |
|
|
pRefreshFrequency = 100
|
| 18509 |
|
|
pUpperLimit = 125000
|
| 18510 |
|
|
pDividerCounterBits = 24
|
| 18511 |
|
|
Module is correct for synthesis.
|
| 18512 |
|
|
|
| 18513 |
|
|
Analyzing module .
|
| 18514 |
|
|
pInitialValue = 0
|
| 18515 |
|
|
pTimerWidth = 19
|
| 18516 |
|
|
pInitialTimerValue = 500000
|
| 18517 |
|
|
Module is correct for synthesis.
|
| 18518 |
|
|
|
| 18519 |
|
|
Analyzing module .
|
| 18520 |
|
|
Module is correct for synthesis.
|
| 18521 |
|
|
|
| 18522 |
|
|
Analyzing module .
|
| 18523 |
|
|
SIZE = 16
|
| 18524 |
|
|
Module is correct for synthesis.
|
| 18525 |
|
|
|
| 18526 |
|
|
Analyzing module .
|
| 18527 |
|
|
Module is correct for synthesis.
|
| 18528 |
|
|
|
| 18529 |
|
|
Analyzing module .
|
| 18530 |
|
|
SIZE = 12
|
| 18531 |
|
|
Module is correct for synthesis.
|
| 18532 |
|
|
|
| 18533 |
|
|
Analyzing module .
|
| 18534 |
|
|
Module is correct for synthesis.
|
| 18535 |
|
|
|
| 18536 |
|
|
Analyzing module .
|
| 18537 |
|
|
VALUE = 0000000000000001
|
| 18538 |
|
|
Module is correct for synthesis.
|
| 18539 |
|
|
|
| 18540 |
|
|
Analyzing module .
|
| 18541 |
|
|
Module is correct for synthesis.
|
| 18542 |
|
|
|
| 18543 |
|
|
Analyzing module .
|
| 18544 |
|
|
VALUE = 1111111111111111
|
| 18545 |
|
|
Module is correct for synthesis.
|
| 18546 |
|
|
|
| 18547 |
|
|
Analyzing module .
|
| 18548 |
|
|
Module is correct for synthesis.
|
| 18549 |
|
|
|
| 18550 |
|
|
Analyzing module .
|
| 18551 |
|
|
VALUE = 0000000000000000
|
| 18552 |
|
|
Module is correct for synthesis.
|
| 18553 |
|
|
|
| 18554 |
|
|
Analyzing module .
|
| 18555 |
|
|
Module is correct for synthesis.
|
| 18556 |
|
|
|
| 18557 |
|
|
Analyzing module .
|
| 18558 |
|
|
Module is correct for synthesis.
|
| 18559 |
|
|
|
| 18560 |
|
|
Analyzing module .
|
| 18561 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 18562 |
|
|
Module is correct for synthesis.
|
| 18563 |
|
|
|
| 18564 |
|
|
Analyzing module .
|
| 18565 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 18566 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 18567 |
|
|
Module is correct for synthesis.
|
| 18568 |
|
|
|
| 18569 |
|
|
Analyzing module .
|
| 18570 |
|
|
Module is correct for synthesis.
|
| 18571 |
|
|
|
| 18572 |
|
|
Analyzing module .
|
| 18573 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18574 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18575 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18576 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18577 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18578 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18579 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18580 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18581 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18582 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18583 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18584 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18585 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18586 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 18587 |
|
|
Module is correct for synthesis.
|
| 18588 |
|
|
|
| 18589 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 18590 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 18591 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 18592 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 18593 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 18594 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 18595 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 18596 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 18597 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 18598 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 18599 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 18600 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 18601 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 18602 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 18603 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 18604 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 18605 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 18606 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 18607 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 18608 |
|
|
Analyzing module .
|
| 18609 |
|
|
Module is correct for synthesis.
|
| 18610 |
|
|
|
| 18611 |
|
|
Analyzing module .
|
| 18612 |
|
|
XTAL_CLK = 35000000
|
| 18613 |
|
|
BAUD = 9600
|
| 18614 |
|
|
CLK_DIV = 113
|
| 18615 |
|
|
CW = 8
|
| 18616 |
|
|
Module is correct for synthesis.
|
| 18617 |
|
|
|
| 18618 |
|
|
Analyzing module .
|
| 18619 |
|
|
Module is correct for synthesis.
|
| 18620 |
|
|
|
| 18621 |
|
|
Analyzing module .
|
| 18622 |
|
|
Module is correct for synthesis.
|
| 18623 |
|
|
|
| 18624 |
|
|
|
| 18625 |
|
|
=========================================================================
|
| 18626 |
|
|
* HDL Synthesis *
|
| 18627 |
|
|
=========================================================================
|
| 18628 |
|
|
|
| 18629 |
|
|
Synthesizing Unit .
|
| 18630 |
|
|
Related source file is "txmit.v".
|
| 18631 |
|
|
Found 1-bit register for signal .
|
| 18632 |
|
|
Found 1-bit register for signal .
|
| 18633 |
|
|
Found 1-bit register for signal .
|
| 18634 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 18635 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 18636 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 18637 |
|
|
Found 1-bit register for signal .
|
| 18638 |
|
|
Found 1-bit register for signal .
|
| 18639 |
|
|
Found 4-bit up counter for signal .
|
| 18640 |
|
|
Found 4-bit up counter for signal .
|
| 18641 |
|
|
Found 8-bit register for signal .
|
| 18642 |
|
|
Found 8-bit register for signal .
|
| 18643 |
|
|
Summary:
|
| 18644 |
|
|
inferred 2 Counter(s).
|
| 18645 |
|
|
inferred 21 D-type flip-flop(s).
|
| 18646 |
|
|
inferred 2 Comparator(s).
|
| 18647 |
|
|
inferred 1 Multiplexer(s).
|
| 18648 |
|
|
Unit synthesized.
|
| 18649 |
|
|
|
| 18650 |
|
|
|
| 18651 |
|
|
Synthesizing Unit .
|
| 18652 |
|
|
Related source file is "rcvr.v".
|
| 18653 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 18654 |
|
|
Found 1-bit register for signal .
|
| 18655 |
|
|
Found 1-bit register for signal .
|
| 18656 |
|
|
Found 1-bit register for signal .
|
| 18657 |
|
|
Found 8-bit tristate buffer for signal .
|
| 18658 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 18659 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 18660 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 18661 |
|
|
Found 1-bit register for signal .
|
| 18662 |
|
|
Found 1-bit register for signal .
|
| 18663 |
|
|
Found 4-bit register for signal .
|
| 18664 |
|
|
Found 4-bit up counter for signal .
|
| 18665 |
|
|
Found 8-bit register for signal .
|
| 18666 |
|
|
Found 7-bit register for signal >.
|
| 18667 |
|
|
Found 1-bit register for signal .
|
| 18668 |
|
|
Found 1-bit register for signal .
|
| 18669 |
|
|
Summary:
|
| 18670 |
|
|
inferred 1 Counter(s).
|
| 18671 |
|
|
inferred 26 D-type flip-flop(s).
|
| 18672 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 18673 |
|
|
inferred 1 Comparator(s).
|
| 18674 |
|
|
inferred 1 Multiplexer(s).
|
| 18675 |
|
|
inferred 8 Tristate(s).
|
| 18676 |
|
|
Unit synthesized.
|
| 18677 |
|
|
|
| 18678 |
|
|
|
| 18679 |
|
|
Synthesizing Unit .
|
| 18680 |
|
|
Related source file is "jkff.v".
|
| 18681 |
|
|
Found 1-bit register for signal .
|
| 18682 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 18683 |
|
|
Summary:
|
| 18684 |
|
|
inferred 1 D-type flip-flop(s).
|
| 18685 |
|
|
inferred 1 Multiplexer(s).
|
| 18686 |
|
|
Unit synthesized.
|
| 18687 |
|
|
|
| 18688 |
|
|
|
| 18689 |
|
|
Synthesizing Unit .
|
| 18690 |
|
|
Related source file is "switchsync.v".
|
| 18691 |
|
|
Found 1-bit register for signal .
|
| 18692 |
|
|
Found 1-bit register for signal .
|
| 18693 |
|
|
Summary:
|
| 18694 |
|
|
inferred 2 D-type flip-flop(s).
|
| 18695 |
|
|
Unit synthesized.
|
| 18696 |
|
|
|
| 18697 |
|
|
|
| 18698 |
|
|
Synthesizing Unit .
|
| 18699 |
|
|
Related source file is "maindcm.v".
|
| 18700 |
|
|
Unit synthesized.
|
| 18701 |
|
|
|
| 18702 |
|
|
|
| 18703 |
|
|
Synthesizing Unit .
|
| 18704 |
|
|
Related source file is "control.v".
|
| 18705 |
|
|
Found 1-bit register for signal .
|
| 18706 |
|
|
Found 1-bit register for signal .
|
| 18707 |
|
|
Found 3-bit up counter for signal .
|
| 18708 |
|
|
Summary:
|
| 18709 |
|
|
inferred 1 Counter(s).
|
| 18710 |
|
|
inferred 2 D-type flip-flop(s).
|
| 18711 |
|
|
Unit synthesized.
|
| 18712 |
|
|
|
| 18713 |
|
|
|
| 18714 |
|
|
Synthesizing Unit .
|
| 18715 |
|
|
Related source file is "misc.v".
|
| 18716 |
|
|
Found 16-bit tristate buffer for signal .
|
| 18717 |
|
|
Summary:
|
| 18718 |
|
|
inferred 16 Tristate(s).
|
| 18719 |
|
|
Unit synthesized.
|
| 18720 |
|
|
|
| 18721 |
|
|
|
| 18722 |
|
|
Synthesizing Unit .
|
| 18723 |
|
|
Related source file is "misc.v".
|
| 18724 |
|
|
Found 16-bit tristate buffer for signal .
|
| 18725 |
|
|
Summary:
|
| 18726 |
|
|
inferred 16 Tristate(s).
|
| 18727 |
|
|
Unit synthesized.
|
| 18728 |
|
|
|
| 18729 |
|
|
|
| 18730 |
|
|
Synthesizing Unit .
|
| 18731 |
|
|
Related source file is "misc.v".
|
| 18732 |
|
|
Found 16-bit tristate buffer for signal .
|
| 18733 |
|
|
Summary:
|
| 18734 |
|
|
inferred 16 Tristate(s).
|
| 18735 |
|
|
Unit synthesized.
|
| 18736 |
|
|
|
| 18737 |
|
|
|
| 18738 |
|
|
Synthesizing Unit .
|
| 18739 |
|
|
Related source file is "misc.v".
|
| 18740 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 18741 |
|
|
Found 16-bit tristate buffer for signal .
|
| 18742 |
|
|
Found 12-bit register for signal .
|
| 18743 |
|
|
Summary:
|
| 18744 |
|
|
inferred 12 D-type flip-flop(s).
|
| 18745 |
|
|
inferred 16 Tristate(s).
|
| 18746 |
|
|
Unit synthesized.
|
| 18747 |
|
|
|
| 18748 |
|
|
|
| 18749 |
|
|
Synthesizing Unit .
|
| 18750 |
|
|
Related source file is "idecode.v".
|
| 18751 |
|
|
Unit synthesized.
|
| 18752 |
|
|
|
| 18753 |
|
|
|
| 18754 |
|
|
Synthesizing Unit .
|
| 18755 |
|
|
Related source file is "control.v".
|
| 18756 |
|
|
Unit synthesized.
|
| 18757 |
|
|
|
| 18758 |
|
|
|
| 18759 |
|
|
Synthesizing Unit .
|
| 18760 |
|
|
Related source file is "alu.v".
|
| 18761 |
|
|
Found 16-bit tristate buffer for signal .
|
| 18762 |
|
|
Found 17-bit subtractor for signal <$AUX_109>.
|
| 18763 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 18764 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 18765 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 18766 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 18767 |
|
|
Summary:
|
| 18768 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 18769 |
|
|
inferred 16 Tristate(s).
|
| 18770 |
|
|
Unit synthesized.
|
| 18771 |
|
|
|
| 18772 |
|
|
|
| 18773 |
|
|
Synthesizing Unit .
|
| 18774 |
|
|
Related source file is "misc.v".
|
| 18775 |
|
|
Unit synthesized.
|
| 18776 |
|
|
|
| 18777 |
|
|
|
| 18778 |
|
|
Synthesizing Unit .
|
| 18779 |
|
|
Related source file is "misc.v".
|
| 18780 |
|
|
Unit synthesized.
|
| 18781 |
|
|
|
| 18782 |
|
|
|
| 18783 |
|
|
Synthesizing Unit .
|
| 18784 |
|
|
Related source file is "misc.v".
|
| 18785 |
|
|
Unit synthesized.
|
| 18786 |
|
|
|
| 18787 |
|
|
|
| 18788 |
|
|
Synthesizing Unit .
|
| 18789 |
|
|
Related source file is "misc.v".
|
| 18790 |
|
|
Unit synthesized.
|
| 18791 |
|
|
|
| 18792 |
|
|
|
| 18793 |
|
|
Synthesizing Unit .
|
| 18794 |
|
|
Related source file is "misc.v".
|
| 18795 |
|
|
Found 16-bit tristate buffer for signal .
|
| 18796 |
|
|
Found 16-bit register for signal .
|
| 18797 |
|
|
Summary:
|
| 18798 |
|
|
inferred 16 D-type flip-flop(s).
|
| 18799 |
|
|
inferred 16 Tristate(s).
|
| 18800 |
|
|
Unit synthesized.
|
| 18801 |
|
|
|
| 18802 |
|
|
|
| 18803 |
|
|
Synthesizing Unit .
|
| 18804 |
|
|
Related source file is "io.v".
|
| 18805 |
|
|
Found 1-bit register for signal .
|
| 18806 |
|
|
Found 1-bit register for signal .
|
| 18807 |
|
|
Found 1-bit register for signal .
|
| 18808 |
|
|
Found 1-bit register for signal .
|
| 18809 |
|
|
Found 1-bit register for signal .
|
| 18810 |
|
|
Found 1-bit register for signal .
|
| 18811 |
|
|
Found 19-bit down counter for signal .
|
| 18812 |
|
|
Found 1-bit register for signal .
|
| 18813 |
|
|
Found 1-bit xor2 for signal .
|
| 18814 |
|
|
Summary:
|
| 18815 |
|
|
inferred 1 Counter(s).
|
| 18816 |
|
|
inferred 7 D-type flip-flop(s).
|
| 18817 |
|
|
Unit synthesized.
|
| 18818 |
|
|
|
| 18819 |
|
|
|
| 18820 |
|
|
Synthesizing Unit .
|
| 18821 |
|
|
Related source file is "io.v".
|
| 18822 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 18823 |
|
|
Found 1-bit register for signal .
|
| 18824 |
|
|
Found 1-bit register for signal .
|
| 18825 |
|
|
Found 1-bit register for signal .
|
| 18826 |
|
|
Found 1-bit register for signal .
|
| 18827 |
|
|
Found 1-bit register for signal .
|
| 18828 |
|
|
Found 1-bit register for signal .
|
| 18829 |
|
|
Found 1-bit register for signal .
|
| 18830 |
|
|
Found 1-bit register for signal .
|
| 18831 |
|
|
Found 1-bit register for signal .
|
| 18832 |
|
|
Found 1-bit register for signal .
|
| 18833 |
|
|
Found 1-bit register for signal .
|
| 18834 |
|
|
Found 1-bit register for signal .
|
| 18835 |
|
|
Found 24-bit up counter for signal .
|
| 18836 |
|
|
Found 1-of-4 decoder for signal .
|
| 18837 |
|
|
Found 2-bit down counter for signal .
|
| 18838 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 18839 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 18840 |
|
|
Summary:
|
| 18841 |
|
|
inferred 1 ROM(s).
|
| 18842 |
|
|
inferred 2 Counter(s).
|
| 18843 |
|
|
inferred 12 D-type flip-flop(s).
|
| 18844 |
|
|
inferred 9 Multiplexer(s).
|
| 18845 |
|
|
inferred 1 Decoder(s).
|
| 18846 |
|
|
Unit synthesized.
|
| 18847 |
|
|
|
| 18848 |
|
|
|
| 18849 |
|
|
Synthesizing Unit .
|
| 18850 |
|
|
Related source file is "uart.v".
|
| 18851 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 18852 |
|
|
Found 1-bit register for signal .
|
| 18853 |
|
|
Found 8-bit up counter for signal .
|
| 18854 |
|
|
Found 1-bit register for signal .
|
| 18855 |
|
|
Summary:
|
| 18856 |
|
|
inferred 1 Counter(s).
|
| 18857 |
|
|
inferred 2 D-type flip-flop(s).
|
| 18858 |
|
|
inferred 1 Multiplexer(s).
|
| 18859 |
|
|
Unit synthesized.
|
| 18860 |
|
|
|
| 18861 |
|
|
|
| 18862 |
|
|
Synthesizing Unit .
|
| 18863 |
|
|
Related source file is "top.v".
|
| 18864 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 18865 |
|
|
Found 16-bit tristate buffer for signal .
|
| 18866 |
|
|
Found 1-bit register for signal .
|
| 18867 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 18868 |
|
|
Found 16-bit tristate buffer for signal .
|
| 18869 |
|
|
Found 1-bit register for signal .
|
| 18870 |
|
|
Found 1-bit register for signal .
|
| 18871 |
|
|
Found 1-bit register for signal .
|
| 18872 |
|
|
Summary:
|
| 18873 |
|
|
inferred 4 D-type flip-flop(s).
|
| 18874 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 18875 |
|
|
inferred 96 Tristate(s).
|
| 18876 |
|
|
Unit synthesized.
|
| 18877 |
|
|
|
| 18878 |
|
|
|
| 18879 |
|
|
Synthesizing Unit .
|
| 18880 |
|
|
Related source file is "FrontPanel.v".
|
| 18881 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 18882 |
|
|
Found finite state machine for signal .
|
| 18883 |
|
|
-----------------------------------------------------------------------
|
| 18884 |
|
|
| States | 6 |
|
| 18885 |
|
|
| Transitions | 6 |
|
| 18886 |
|
|
| Inputs | 0 |
|
| 18887 |
|
|
| Outputs | 12 |
|
| 18888 |
|
|
| Clock | clockin (rising_edge) |
|
| 18889 |
|
|
| Clock enable | select (positive) |
|
| 18890 |
|
|
| Reset | clear (positive) |
|
| 18891 |
|
|
| Reset type | asynchronous |
|
| 18892 |
|
|
| Reset State | 000001 |
|
| 18893 |
|
|
| Encoding | automatic |
|
| 18894 |
|
|
| Implementation | LUT |
|
| 18895 |
|
|
-----------------------------------------------------------------------
|
| 18896 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 18897 |
|
|
Found 4-bit register for signal .
|
| 18898 |
|
|
Found 16-bit register for signal .
|
| 18899 |
|
|
Summary:
|
| 18900 |
|
|
inferred 1 Finite State Machine(s).
|
| 18901 |
|
|
inferred 16 D-type flip-flop(s).
|
| 18902 |
|
|
inferred 16 Multiplexer(s).
|
| 18903 |
|
|
Unit synthesized.
|
| 18904 |
|
|
|
| 18905 |
|
|
|
| 18906 |
|
|
Synthesizing Unit .
|
| 18907 |
|
|
Related source file is "topbox.v".
|
| 18908 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 18909 |
|
|
Found 16-bit tristate buffer for signal .
|
| 18910 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 18911 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 18912 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 18913 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 18914 |
|
|
Found 4-bit register for signal .
|
| 18915 |
|
|
Found 1-bit register for signal .
|
| 18916 |
|
|
Found 1-bit register for signal .
|
| 18917 |
|
|
Found 16-bit register for signal .
|
| 18918 |
|
|
Summary:
|
| 18919 |
|
|
inferred 22 D-type flip-flop(s).
|
| 18920 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 18921 |
|
|
inferred 6 Multiplexer(s).
|
| 18922 |
|
|
inferred 48 Tristate(s).
|
| 18923 |
|
|
Unit synthesized.
|
| 18924 |
|
|
|
| 18925 |
|
|
|
| 18926 |
|
|
=========================================================================
|
| 18927 |
|
|
* Advanced HDL Synthesis *
|
| 18928 |
|
|
=========================================================================
|
| 18929 |
|
|
|
| 18930 |
|
|
Advanced RAM inference ...
|
| 18931 |
|
|
Advanced multiplier inference ...
|
| 18932 |
|
|
Advanced Registered AddSub inference ...
|
| 18933 |
|
|
Analyzing FSM for best encoding.
|
| 18934 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 18935 |
|
|
--------------------
|
| 18936 |
|
|
State | Encoding
|
| 18937 |
|
|
--------------------
|
| 18938 |
|
|
000001 | 100000
|
| 18939 |
|
|
000010 | 010000
|
| 18940 |
|
|
000100 | 001000
|
| 18941 |
|
|
001000 | 000100
|
| 18942 |
|
|
010000 | 000010
|
| 18943 |
|
|
100000 | 000001
|
| 18944 |
|
|
--------------------
|
| 18945 |
|
|
Dynamic shift register inference ...
|
| 18946 |
|
|
|
| 18947 |
|
|
=========================================================================
|
| 18948 |
|
|
HDL Synthesis Report
|
| 18949 |
|
|
|
| 18950 |
|
|
Macro Statistics
|
| 18951 |
|
|
# FSMs : 1
|
| 18952 |
|
|
# ROMs : 1
|
| 18953 |
|
|
16x7-bit ROM : 1
|
| 18954 |
|
|
# Adders/Subtractors : 5
|
| 18955 |
|
|
12-bit adder carry out : 1
|
| 18956 |
|
|
16-bit adder carry out : 1
|
| 18957 |
|
|
17-bit subtractor : 1
|
| 18958 |
|
|
4-bit adder : 2
|
| 18959 |
|
|
# Counters : 10
|
| 18960 |
|
|
19-bit down counter : 3
|
| 18961 |
|
|
2-bit down counter : 1
|
| 18962 |
|
|
24-bit up counter : 1
|
| 18963 |
|
|
3-bit up counter : 1
|
| 18964 |
|
|
4-bit up counter : 3
|
| 18965 |
|
|
8-bit up counter : 1
|
| 18966 |
|
|
# Registers : 138
|
| 18967 |
|
|
1-bit register : 125
|
| 18968 |
|
|
12-bit register : 4
|
| 18969 |
|
|
16-bit register : 4
|
| 18970 |
|
|
4-bit register : 3
|
| 18971 |
|
|
8-bit register : 2
|
| 18972 |
|
|
# Comparators : 3
|
| 18973 |
|
|
4-bit comparator greater : 2
|
| 18974 |
|
|
4-bit comparator less : 1
|
| 18975 |
|
|
# Multiplexers : 13
|
| 18976 |
|
|
1-bit 4-to-1 multiplexer : 10
|
| 18977 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 18978 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 18979 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 18980 |
|
|
# Decoders : 1
|
| 18981 |
|
|
1-of-4 decoder : 1
|
| 18982 |
|
|
# Tristates : 97
|
| 18983 |
|
|
1-bit tristate buffer : 80
|
| 18984 |
|
|
16-bit tristate buffer : 16
|
| 18985 |
|
|
8-bit tristate buffer : 1
|
| 18986 |
|
|
# Xors : 6
|
| 18987 |
|
|
1-bit xor2 : 5
|
| 18988 |
|
|
16-bit xor2 : 1
|
| 18989 |
|
|
|
| 18990 |
|
|
=========================================================================
|
| 18991 |
|
|
|
| 18992 |
|
|
=========================================================================
|
| 18993 |
|
|
* Low Level Synthesis *
|
| 18994 |
|
|
=========================================================================
|
| 18995 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 18996 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 18997 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 18998 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 18999 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 19000 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 19001 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 19002 |
|
|
|
| 19003 |
|
|
Optimizing unit ...
|
| 19004 |
|
|
|
| 19005 |
|
|
Optimizing unit ...
|
| 19006 |
|
|
|
| 19007 |
|
|
Optimizing unit ...
|
| 19008 |
|
|
|
| 19009 |
|
|
Optimizing unit ...
|
| 19010 |
|
|
|
| 19011 |
|
|
Optimizing unit ...
|
| 19012 |
|
|
|
| 19013 |
|
|
Optimizing unit ...
|
| 19014 |
|
|
|
| 19015 |
|
|
Optimizing unit ...
|
| 19016 |
|
|
|
| 19017 |
|
|
Optimizing unit ...
|
| 19018 |
|
|
|
| 19019 |
|
|
Optimizing unit ...
|
| 19020 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 19021 |
|
|
|
| 19022 |
|
|
Mapping all equations...
|
| 19023 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 19024 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 19025 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 19026 |
|
|
Building and optimizing final netlist ...
|
| 19027 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
|
| 19028 |
|
|
Forward register balancing over CPU/decoder/opdec78 of flipflops :
|
| 19029 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 19030 |
|
|
Forward register balancing over CPU/decoder/opxor1 of flipflops :
|
| 19031 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
|
| 19032 |
|
|
Forward register balancing over CPU/decoder/opand1 of flipflops :
|
| 19033 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 19034 |
|
|
Forward register balancing over CPU/decoder/opior1 of flipflops :
|
| 19035 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
|
| 19036 |
|
|
Forward register balancing over CPU/decoder/oplda1 of flipflops :
|
| 19037 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
|
| 19038 |
|
|
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
|
| 19039 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 19040 |
|
|
Forward register balancing over Ker571 of flipflops :
|
| 19041 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 19042 |
|
|
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
|
| 19043 |
|
|
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 19044 |
|
|
Forward register balancing over Ker2101 of flipflops :
|
| 19045 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 19046 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
|
| 19047 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
|
| 19048 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
|
| 19049 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 19050 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
|
| 19051 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
|
| 19052 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
|
| 19053 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 19054 |
|
|
Forward register balancing over CPU/msend9 of flipflops :
|
| 19055 |
|
|
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
|
| 19056 |
|
|
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
|
| 19057 |
|
|
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
|
| 19058 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
|
| 19059 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 19060 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
|
| 19061 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 19062 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
|
| 19063 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 19064 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
|
| 19065 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 19066 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
|
| 19067 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 19068 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
|
| 19069 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
|
| 19070 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
|
| 19071 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 19072 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
|
| 19073 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
|
| 19074 |
|
|
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
|
| 19075 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 19076 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
|
| 19077 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 19078 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
|
| 19079 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 19080 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
|
| 19081 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 19082 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
|
| 19083 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 19084 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
|
| 19085 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 19086 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
|
| 19087 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 19088 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
|
| 19089 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 19090 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
|
| 19091 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 19092 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
|
| 19093 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 19094 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
|
| 19095 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
|
| 19096 |
|
|
Forward register balancing over Ker2161_SW0 of flipflops :
|
| 19097 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 19098 |
|
|
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
|
| 19099 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 19100 |
|
|
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
|
| 19101 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
|
| 19102 |
|
|
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
|
| 19103 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 19104 |
|
|
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
|
| 19105 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 19106 |
|
|
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
|
| 19107 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 19108 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
|
| 19109 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 19110 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
|
| 19111 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 19112 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
|
| 19113 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 19114 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
|
| 19115 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 19116 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
|
| 19117 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
|
| 19118 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
|
| 19119 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 19120 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
|
| 19121 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 19122 |
|
|
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
|
| 19123 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
|
| 19124 |
|
|
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
|
| 19125 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 19126 |
|
|
Forward register balancing over Ker161_SW0 of flipflops :
|
| 19127 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 19128 |
|
|
Forward register balancing over CPU/decoder/opdec74 of flipflops :
|
| 19129 |
|
|
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
|
| 19130 |
|
|
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
|
| 19131 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 19132 |
|
|
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
|
| 19133 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 19134 |
|
|
Forward register balancing over CPU/ctl/sim/Ker71 of flipflops :
|
| 19135 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
|
| 19136 |
|
|
Forward register balancing over CPU/ctl/sim/_n00121 of flipflops :
|
| 19137 |
|
|
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
|
| 19138 |
|
|
Forward register balancing over CPU/ctl/sim/_n00111 of flipflops :
|
| 19139 |
|
|
CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2.
|
| 19140 |
|
|
Forward register balancing over CPU/ctl/sim/_n00101 of flipflops :
|
| 19141 |
|
|
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
|
| 19142 |
|
|
Forward register balancing over CPU/bus<0>__n0000<0>_N01_SW0 of flipflops :
|
| 19143 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
|
| 19144 |
|
|
Forward register balancing over CPU/decoder/opadd1 of flipflops :
|
| 19145 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 19146 |
|
|
Forward register balancing over CPU/decoder/opdec41 of flipflops :
|
| 19147 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
|
| 19148 |
|
|
Forward register balancing over CPU/decoder/opinc41 of flipflops :
|
| 19149 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
|
| 19150 |
|
|
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
|
| 19151 |
|
|
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 19152 |
|
|
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
|
| 19153 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 19154 |
|
|
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
|
| 19155 |
|
|
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 19156 |
|
|
Forward register balancing over Ker212_SW0 of flipflops :
|
| 19157 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
|
| 19158 |
|
|
Forward register balancing over CPU/decoder/opdec714 of flipflops :
|
| 19159 |
|
|
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
|
| 19160 |
|
|
Forward register balancing over CPU/ctl/sim/_n00151 of flipflops :
|
| 19161 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_1.
|
| 19162 |
|
|
Register equivalent to has been removed
|
| 19163 |
|
|
Register equivalent to has been removed
|
| 19164 |
|
|
Register equivalent to has been removed
|
| 19165 |
|
|
Register equivalent to has been removed
|
| 19166 |
|
|
Register equivalent to has been removed
|
| 19167 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
|
| 19168 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
|
| 19169 |
|
|
FlipFlop CPU/ctl/sim/_n00111_FRB has been replicated 7 time(s)
|
| 19170 |
|
|
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
|
| 19171 |
|
|
FlipFlop loadnow has been replicated 1 time(s)
|
| 19172 |
|
|
|
| 19173 |
|
|
=========================================================================
|
| 19174 |
|
|
* Final Report *
|
| 19175 |
|
|
=========================================================================
|
| 19176 |
|
|
|
| 19177 |
|
|
Device utilization summary:
|
| 19178 |
|
|
---------------------------
|
| 19179 |
|
|
|
| 19180 |
|
|
Selected Device : 3s200ft256-4
|
| 19181 |
|
|
|
| 19182 |
|
|
Number of Slices: 617 out of 1920 32%
|
| 19183 |
|
|
Number of Slice Flip Flops: 436 out of 3840 11%
|
| 19184 |
|
|
Number of 4 input LUTs: 1081 out of 3840 28%
|
| 19185 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 19186 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 19187 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 19188 |
|
|
|
| 19189 |
|
|
|
| 19190 |
|
|
=========================================================================
|
| 19191 |
|
|
TIMING REPORT
|
| 19192 |
|
|
|
| 19193 |
|
|
|
| 19194 |
|
|
Clock Information:
|
| 19195 |
|
|
------------------
|
| 19196 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 19197 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 19198 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 19199 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 436 |
|
| 19200 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 19201 |
|
|
|
| 19202 |
|
|
Timing Summary:
|
| 19203 |
|
|
---------------
|
| 19204 |
|
|
Speed Grade: -4
|
| 19205 |
|
|
|
| 19206 |
|
|
Minimum period: 13.584ns (Maximum Frequency: 73.618MHz)
|
| 19207 |
|
|
Minimum input arrival time before clock: 10.967ns
|
| 19208 |
|
|
Maximum output required time after clock: 23.172ns
|
| 19209 |
|
|
Maximum combinational path delay: 15.112ns
|
| 19210 |
|
|
|
| 19211 |
|
|
=========================================================================
|
| 19212 |
|
|
|
| 19213 |
|
|
|
| 19214 |
|
|
|
| 19215 |
|
|
|
| 19216 |
|
|
Started process "Translate".
|
| 19217 |
|
|
|
| 19218 |
|
|
|
| 19219 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 19220 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 19221 |
|
|
|
| 19222 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 19223 |
|
|
|
| 19224 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 19225 |
|
|
|
| 19226 |
|
|
Checking timing specifications ...
|
| 19227 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 19228 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 19229 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 19230 |
|
|
20.408000 nS HIGH 50.000000%
|
| 19231 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 19232 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 19233 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 19234 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 19235 |
|
|
from this group.
|
| 19236 |
|
|
Checking expanded design ...
|
| 19237 |
|
|
|
| 19238 |
|
|
NGDBUILD Design Results Summary:
|
| 19239 |
|
|
Number of errors: 0
|
| 19240 |
|
|
Number of warnings: 1
|
| 19241 |
|
|
|
| 19242 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 19243 |
|
|
|
| 19244 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 19245 |
|
|
|
| 19246 |
|
|
NGDBUILD done.
|
| 19247 |
|
|
|
| 19248 |
|
|
|
| 19249 |
|
|
|
| 19250 |
|
|
|
| 19251 |
|
|
Started process "Map".
|
| 19252 |
|
|
|
| 19253 |
|
|
Using target part "3s200ft256-4".
|
| 19254 |
|
|
Mapping design into LUTs...
|
| 19255 |
|
|
Running directed packing...
|
| 19256 |
|
|
Running delay-based LUT packing...
|
| 19257 |
|
|
Running timing-driven packing...
|
| 19258 |
|
|
|
| 19259 |
|
|
Phase 1.1
|
| 19260 |
|
|
Phase 1.1 (Checksum:98d1df) REAL time: 0 secs
|
| 19261 |
|
|
|
| 19262 |
|
|
Phase 2.31
|
| 19263 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs
|
| 19264 |
|
|
|
| 19265 |
|
|
Phase 3.2
|
| 19266 |
|
|
.
|
| 19267 |
|
|
|
| 19268 |
|
|
|
| 19269 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
|
| 19270 |
|
|
|
| 19271 |
|
|
Phase 4.4
|
| 19272 |
|
|
...............
|
| 19273 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs
|
| 19274 |
|
|
|
| 19275 |
|
|
Phase 5.28
|
| 19276 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs
|
| 19277 |
|
|
|
| 19278 |
|
|
Phase 6.8
|
| 19279 |
|
|
........................
|
| 19280 |
|
|
.......
|
| 19281 |
|
|
..........................
|
| 19282 |
|
|
...............
|
| 19283 |
|
|
...............
|
| 19284 |
|
|
Phase 6.8 (Checksum:ac06bf) REAL time: 10 secs
|
| 19285 |
|
|
|
| 19286 |
|
|
Phase 7.29
|
| 19287 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs
|
| 19288 |
|
|
|
| 19289 |
|
|
Phase 8.5
|
| 19290 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs
|
| 19291 |
|
|
|
| 19292 |
|
|
Phase 9.18
|
| 19293 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 20 secs
|
| 19294 |
|
|
|
| 19295 |
|
|
Phase 10.5
|
| 19296 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 20 secs
|
| 19297 |
|
|
|
| 19298 |
|
|
|
| 19299 |
|
|
Design Summary:
|
| 19300 |
|
|
Number of errors: 0
|
| 19301 |
|
|
Number of warnings: 11
|
| 19302 |
|
|
Logic Utilization:
|
| 19303 |
|
|
Number of Slice Flip Flops: 410 out of 3,840 10%
|
| 19304 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 19305 |
|
|
Logic Distribution:
|
| 19306 |
|
|
Number of occupied Slices: 674 out of 1,920 35%
|
| 19307 |
|
|
Number of Slices containing only related logic: 674 out of 674 100%
|
| 19308 |
|
|
Number of Slices containing unrelated logic: 0 out of 674 0%
|
| 19309 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 19310 |
|
|
Total Number 4 input LUTs: 1,135 out of 3,840 29%
|
| 19311 |
|
|
Number used as logic: 1,131
|
| 19312 |
|
|
Number used as a route-thru: 4
|
| 19313 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 19314 |
|
|
IOB Flip Flops: 26
|
| 19315 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 19316 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 19317 |
|
|
|
| 19318 |
|
|
Total equivalent gate count for design: 18,144
|
| 19319 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 19320 |
|
|
Peak Memory Usage: 133 MB
|
| 19321 |
|
|
|
| 19322 |
|
|
Mapping completed.
|
| 19323 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 19324 |
|
|
|
| 19325 |
|
|
|
| 19326 |
|
|
|
| 19327 |
|
|
|
| 19328 |
|
|
Started process "Place & Route".
|
| 19329 |
|
|
|
| 19330 |
|
|
|
| 19331 |
|
|
|
| 19332 |
|
|
|
| 19333 |
|
|
Constraints file: topbox.pcf.
|
| 19334 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 19335 |
|
|
C:/Xilinx71.
|
| 19336 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 19337 |
|
|
|
| 19338 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 19339 |
|
|
Celsius)
|
| 19340 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 19341 |
|
|
|
| 19342 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 19343 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 19344 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 19345 |
|
|
ps (24.00 Mhz).
|
| 19346 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 19347 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 19348 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 19349 |
|
|
(210.04 Mhz).
|
| 19350 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 19351 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 19352 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 19353 |
|
|
ps (24.00 Mhz).
|
| 19354 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 19355 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 19356 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 19357 |
|
|
(210.04 Mhz).
|
| 19358 |
|
|
|
| 19359 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 19360 |
|
|
|
| 19361 |
|
|
|
| 19362 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 19363 |
|
|
achieve better performance.
|
| 19364 |
|
|
|
| 19365 |
|
|
Device Utilization Summary:
|
| 19366 |
|
|
|
| 19367 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 19368 |
|
|
Number of DCMs 1 out of 4 25%
|
| 19369 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 19370 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 19371 |
|
|
|
| 19372 |
|
|
Number of Slices 674 out of 1920 35%
|
| 19373 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 19374 |
|
|
|
| 19375 |
|
|
|
| 19376 |
|
|
|
| 19377 |
|
|
Overall effort level (-ol): High (set by user)
|
| 19378 |
|
|
Router effort level (-rl): High (set by user)
|
| 19379 |
|
|
|
| 19380 |
|
|
Starting initial Timing Analysis. REAL time: 4 secs
|
| 19381 |
|
|
Finished initial Timing Analysis. REAL time: 4 secs
|
| 19382 |
|
|
|
| 19383 |
|
|
Starting Router
|
| 19384 |
|
|
|
| 19385 |
|
|
Phase 1: 4917 unrouted; REAL time: 4 secs
|
| 19386 |
|
|
|
| 19387 |
|
|
Phase 2: 4563 unrouted; REAL time: 4 secs
|
| 19388 |
|
|
|
| 19389 |
|
|
Phase 3: 2229 unrouted; REAL time: 5 secs
|
| 19390 |
|
|
|
| 19391 |
|
|
Phase 4: 2229 unrouted; (0) REAL time: 6 secs
|
| 19392 |
|
|
|
| 19393 |
|
|
Phase 5: 2229 unrouted; (0) REAL time: 6 secs
|
| 19394 |
|
|
|
| 19395 |
|
|
Phase 6: 2229 unrouted; (0) REAL time: 6 secs
|
| 19396 |
|
|
|
| 19397 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 13 secs
|
| 19398 |
|
|
|
| 19399 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 13 secs
|
| 19400 |
|
|
|
| 19401 |
|
|
|
| 19402 |
|
|
Total REAL time to Router completion: 14 secs
|
| 19403 |
|
|
Total CPU time to Router completion: 14 secs
|
| 19404 |
|
|
|
| 19405 |
|
|
Generating "PAR" statistics.
|
| 19406 |
|
|
|
| 19407 |
|
|
**************************
|
| 19408 |
|
|
Generating Clock Report
|
| 19409 |
|
|
**************************
|
| 19410 |
|
|
|
| 19411 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 19412 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 19413 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 19414 |
|
|
| clk | BUFGMUX2| No | 335 | 0.041 | 1.051 |
|
| 19415 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 19416 |
|
|
|
| 19417 |
|
|
Timing Score: 0
|
| 19418 |
|
|
|
| 19419 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 19420 |
|
|
This may be due to a setup or hold violation.
|
| 19421 |
|
|
|
| 19422 |
|
|
--------------------------------------------------------------------------------
|
| 19423 |
|
|
Constraint | Requested | Actual | Logic
|
| 19424 |
|
|
| | | Levels
|
| 19425 |
|
|
--------------------------------------------------------------------------------
|
| 19426 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 19427 |
|
|
HIGH 50% | | |
|
| 19428 |
|
|
--------------------------------------------------------------------------------
|
| 19429 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 30.346ns | 6
|
| 19430 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 19431 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 19432 |
|
|
--------------------------------------------------------------------------------
|
| 19433 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 39.146ns | 9
|
| 19434 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 19435 |
|
|
HIGH 50% | | |
|
| 19436 |
|
|
--------------------------------------------------------------------------------
|
| 19437 |
|
|
|
| 19438 |
|
|
|
| 19439 |
|
|
All constraints were met.
|
| 19440 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 19441 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 19442 |
|
|
Generating Pad Report.
|
| 19443 |
|
|
|
| 19444 |
|
|
All signals are completely routed.
|
| 19445 |
|
|
|
| 19446 |
|
|
Total REAL time to PAR completion: 15 secs
|
| 19447 |
|
|
Total CPU time to PAR completion: 15 secs
|
| 19448 |
|
|
|
| 19449 |
|
|
Peak Memory Usage: 94 MB
|
| 19450 |
|
|
|
| 19451 |
|
|
Placer: Not run.
|
| 19452 |
|
|
Routing: Completed - No errors found.
|
| 19453 |
|
|
Timing: Completed - No errors found.
|
| 19454 |
|
|
|
| 19455 |
|
|
Number of error messages: 0
|
| 19456 |
|
|
Number of warning messages: 4
|
| 19457 |
|
|
Number of info messages: 1
|
| 19458 |
|
|
|
| 19459 |
|
|
Writing design to file topbox.ncd
|
| 19460 |
|
|
|
| 19461 |
|
|
|
| 19462 |
|
|
|
| 19463 |
|
|
PAR done!
|
| 19464 |
|
|
|
| 19465 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 19466 |
|
|
|
| 19467 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 19468 |
|
|
C:/Xilinx71.
|
| 19469 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 19470 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 19471 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 19472 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 19473 |
|
|
ps (24.00 Mhz).
|
| 19474 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 19475 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 19476 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 19477 |
|
|
(210.04 Mhz).
|
| 19478 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 19479 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 19480 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 19481 |
|
|
ps (24.00 Mhz).
|
| 19482 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 19483 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 19484 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 19485 |
|
|
(210.04 Mhz).
|
| 19486 |
|
|
|
| 19487 |
|
|
Analysis completed Sat Sep 30 20:38:13 2006
|
| 19488 |
|
|
--------------------------------------------------------------------------------
|
| 19489 |
|
|
|
| 19490 |
|
|
Generating Report ...
|
| 19491 |
|
|
|
| 19492 |
|
|
Number of warnings: 4
|
| 19493 |
|
|
Total time: 3 secs
|
| 19494 |
|
|
|
| 19495 |
|
|
|
| 19496 |
|
|
|
| 19497 |
|
|
|
| 19498 |
|
|
|
| 19499 |
|
|
|
| 19500 |
|
|
|
| 19501 |
|
|
Started process "Generate Programming File".
|
| 19502 |
|
|
|
| 19503 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 19504 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 19505 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 19506 |
|
|
Interactive Data Sheet.
|
| 19507 |
|
|
|
| 19508 |
|
|
|
| 19509 |
|
|
Project Navigator Auto-Make Log File
|
| 19510 |
|
|
-------------------------------------
|
| 19511 |
|
|
|
| 19512 |
|
|
|
| 19513 |
|
|
|
| 19514 |
|
|
|
| 19515 |
|
|
|
| 19516 |
|
|
|
| 19517 |
|
|
|
| 19518 |
|
|
|
| 19519 |
|
|
|
| 19520 |
|
|
|
| 19521 |
|
|
Started process "Synthesize".
|
| 19522 |
|
|
|
| 19523 |
|
|
|
| 19524 |
|
|
=========================================================================
|
| 19525 |
|
|
* HDL Compilation *
|
| 19526 |
|
|
=========================================================================
|
| 19527 |
|
|
Compiling verilog file "io.v"
|
| 19528 |
|
|
Module compiled
|
| 19529 |
|
|
Module compiled
|
| 19530 |
|
|
Compiling verilog file "FrontPanel.v"
|
| 19531 |
|
|
Module compiled
|
| 19532 |
|
|
Compiling verilog file "misc.v"
|
| 19533 |
|
|
Module compiled
|
| 19534 |
|
|
Module compiled
|
| 19535 |
|
|
Module compiled
|
| 19536 |
|
|
Module compiled
|
| 19537 |
|
|
Module compiled
|
| 19538 |
|
|
Module compiled
|
| 19539 |
|
|
Compiling verilog file "alu.v"
|
| 19540 |
|
|
Module compiled
|
| 19541 |
|
|
Compiling verilog file "switchsync.v"
|
| 19542 |
|
|
Module compiled
|
| 19543 |
|
|
Compiling verilog file "jkff.v"
|
| 19544 |
|
|
Module compiled
|
| 19545 |
|
|
Compiling verilog file "control.v"
|
| 19546 |
|
|
Module compiled
|
| 19547 |
|
|
Module compiled
|
| 19548 |
|
|
Compiling verilog file "maindcm.v"
|
| 19549 |
|
|
Module compiled
|
| 19550 |
|
|
Compiling verilog file "idecode.v"
|
| 19551 |
|
|
Module compiled
|
| 19552 |
|
|
Compiling verilog file "top.v"
|
| 19553 |
|
|
Module compiled
|
| 19554 |
|
|
Compiling verilog file "rcvr.v"
|
| 19555 |
|
|
Module compiled
|
| 19556 |
|
|
Compiling verilog file "txmit.v"
|
| 19557 |
|
|
Module compiled
|
| 19558 |
|
|
Compiling verilog file "uart.v"
|
| 19559 |
|
|
Module compiled
|
| 19560 |
|
|
Compiling verilog file "topbox.v"
|
| 19561 |
|
|
Module compiled
|
| 19562 |
|
|
No errors in compilation
|
| 19563 |
|
|
Analysis of file <"topbox.prj"> succeeded.
|
| 19564 |
|
|
|
| 19565 |
|
|
|
| 19566 |
|
|
=========================================================================
|
| 19567 |
|
|
* HDL Analysis *
|
| 19568 |
|
|
=========================================================================
|
| 19569 |
|
|
Analyzing top module .
|
| 19570 |
|
|
Module is correct for synthesis.
|
| 19571 |
|
|
|
| 19572 |
|
|
Set property "resynthesize = true" for unit .
|
| 19573 |
|
|
Analyzing module .
|
| 19574 |
|
|
Module is correct for synthesis.
|
| 19575 |
|
|
|
| 19576 |
|
|
Analyzing module .
|
| 19577 |
|
|
pClockFrequency = 50
|
| 19578 |
|
|
pRefreshFrequency = 100
|
| 19579 |
|
|
pUpperLimit = 125000
|
| 19580 |
|
|
pDividerCounterBits = 24
|
| 19581 |
|
|
Module is correct for synthesis.
|
| 19582 |
|
|
|
| 19583 |
|
|
Analyzing module .
|
| 19584 |
|
|
pInitialValue = 0
|
| 19585 |
|
|
pTimerWidth = 19
|
| 19586 |
|
|
pInitialTimerValue = 500000
|
| 19587 |
|
|
Module is correct for synthesis.
|
| 19588 |
|
|
|
| 19589 |
|
|
Analyzing module .
|
| 19590 |
|
|
Module is correct for synthesis.
|
| 19591 |
|
|
|
| 19592 |
|
|
Analyzing module .
|
| 19593 |
|
|
SIZE = 16
|
| 19594 |
|
|
Module is correct for synthesis.
|
| 19595 |
|
|
|
| 19596 |
|
|
Analyzing module .
|
| 19597 |
|
|
Module is correct for synthesis.
|
| 19598 |
|
|
|
| 19599 |
|
|
Analyzing module .
|
| 19600 |
|
|
SIZE = 12
|
| 19601 |
|
|
Module is correct for synthesis.
|
| 19602 |
|
|
|
| 19603 |
|
|
Analyzing module .
|
| 19604 |
|
|
Module is correct for synthesis.
|
| 19605 |
|
|
|
| 19606 |
|
|
Analyzing module .
|
| 19607 |
|
|
VALUE = 0000000000000001
|
| 19608 |
|
|
Module is correct for synthesis.
|
| 19609 |
|
|
|
| 19610 |
|
|
Analyzing module .
|
| 19611 |
|
|
Module is correct for synthesis.
|
| 19612 |
|
|
|
| 19613 |
|
|
Analyzing module .
|
| 19614 |
|
|
VALUE = 1111111111111111
|
| 19615 |
|
|
Module is correct for synthesis.
|
| 19616 |
|
|
|
| 19617 |
|
|
Analyzing module .
|
| 19618 |
|
|
Module is correct for synthesis.
|
| 19619 |
|
|
|
| 19620 |
|
|
Analyzing module .
|
| 19621 |
|
|
VALUE = 0000000000000000
|
| 19622 |
|
|
Module is correct for synthesis.
|
| 19623 |
|
|
|
| 19624 |
|
|
Analyzing module .
|
| 19625 |
|
|
Module is correct for synthesis.
|
| 19626 |
|
|
|
| 19627 |
|
|
Analyzing module .
|
| 19628 |
|
|
Module is correct for synthesis.
|
| 19629 |
|
|
|
| 19630 |
|
|
Analyzing module .
|
| 19631 |
|
|
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
|
| 19632 |
|
|
Module is correct for synthesis.
|
| 19633 |
|
|
|
| 19634 |
|
|
Analyzing module .
|
| 19635 |
|
|
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
|
| 19636 |
|
|
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
|
| 19637 |
|
|
Module is correct for synthesis.
|
| 19638 |
|
|
|
| 19639 |
|
|
Analyzing module .
|
| 19640 |
|
|
Module is correct for synthesis.
|
| 19641 |
|
|
|
| 19642 |
|
|
Analyzing module .
|
| 19643 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19644 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19645 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19646 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19647 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19648 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19649 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19650 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19651 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19652 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19653 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19654 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19655 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19656 |
|
|
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property of instance set by attribute.
|
| 19657 |
|
|
Module is correct for synthesis.
|
| 19658 |
|
|
|
| 19659 |
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit .
|
| 19660 |
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit .
|
| 19661 |
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit .
|
| 19662 |
|
|
Set user-defined property "DSS_MODE = NONE" for instance in unit .
|
| 19663 |
|
|
Set user-defined property "USELOWSKEWLINES = " for signal in unit .
|
| 19664 |
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit .
|
| 19665 |
|
|
Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit .
|
| 19666 |
|
|
Set user-defined property "CLKFX_DIVIDE = 10" for instance in unit .
|
| 19667 |
|
|
Set user-defined property "CLKFX_MULTIPLY = 7" for instance in unit .
|
| 19668 |
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit .
|
| 19669 |
|
|
Set user-defined property "CLKIN_PERIOD = 20.000000" for instance in unit .
|
| 19670 |
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit .
|
| 19671 |
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit .
|
| 19672 |
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit .
|
| 19673 |
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit .
|
| 19674 |
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit .
|
| 19675 |
|
|
Set user-defined property "FACTORY_JF = C080" for instance in unit .
|
| 19676 |
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance in unit .
|
| 19677 |
|
|
Set user-defined property "STARTUP_WAIT = TRUE" for instance in unit .
|
| 19678 |
|
|
Analyzing module .
|
| 19679 |
|
|
Module is correct for synthesis.
|
| 19680 |
|
|
|
| 19681 |
|
|
Analyzing module .
|
| 19682 |
|
|
XTAL_CLK = 35000000
|
| 19683 |
|
|
BAUD = 19200
|
| 19684 |
|
|
CLK_DIV = 56
|
| 19685 |
|
|
CW = 8
|
| 19686 |
|
|
Module is correct for synthesis.
|
| 19687 |
|
|
|
| 19688 |
|
|
Analyzing module .
|
| 19689 |
|
|
Module is correct for synthesis.
|
| 19690 |
|
|
|
| 19691 |
|
|
Analyzing module .
|
| 19692 |
|
|
Module is correct for synthesis.
|
| 19693 |
|
|
|
| 19694 |
|
|
|
| 19695 |
|
|
=========================================================================
|
| 19696 |
|
|
* HDL Synthesis *
|
| 19697 |
|
|
=========================================================================
|
| 19698 |
|
|
|
| 19699 |
|
|
Synthesizing Unit .
|
| 19700 |
|
|
Related source file is "txmit.v".
|
| 19701 |
|
|
Found 1-bit register for signal .
|
| 19702 |
|
|
Found 1-bit register for signal .
|
| 19703 |
|
|
Found 1-bit register for signal .
|
| 19704 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
|
| 19705 |
|
|
Found 4-bit comparator less for signal <$n0030> created at line 81.
|
| 19706 |
|
|
Found 4-bit comparator greater for signal <$n0031> created at line 81.
|
| 19707 |
|
|
Found 1-bit register for signal .
|
| 19708 |
|
|
Found 1-bit register for signal .
|
| 19709 |
|
|
Found 4-bit up counter for signal .
|
| 19710 |
|
|
Found 4-bit up counter for signal .
|
| 19711 |
|
|
Found 8-bit register for signal .
|
| 19712 |
|
|
Found 8-bit register for signal .
|
| 19713 |
|
|
Summary:
|
| 19714 |
|
|
inferred 2 Counter(s).
|
| 19715 |
|
|
inferred 21 D-type flip-flop(s).
|
| 19716 |
|
|
inferred 2 Comparator(s).
|
| 19717 |
|
|
inferred 1 Multiplexer(s).
|
| 19718 |
|
|
Unit synthesized.
|
| 19719 |
|
|
|
| 19720 |
|
|
|
| 19721 |
|
|
Synthesizing Unit .
|
| 19722 |
|
|
Related source file is "rcvr.v".
|
| 19723 |
|
|
WARNING:Xst:646 - Signal > is assigned but never used.
|
| 19724 |
|
|
Found 1-bit register for signal .
|
| 19725 |
|
|
Found 1-bit register for signal .
|
| 19726 |
|
|
Found 1-bit register for signal .
|
| 19727 |
|
|
Found 8-bit tristate buffer for signal .
|
| 19728 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
|
| 19729 |
|
|
Found 4-bit adder for signal <$n0012> created at line 83.
|
| 19730 |
|
|
Found 4-bit comparator greater for signal <$n0019> created at line 112.
|
| 19731 |
|
|
Found 1-bit register for signal .
|
| 19732 |
|
|
Found 1-bit register for signal .
|
| 19733 |
|
|
Found 4-bit register for signal .
|
| 19734 |
|
|
Found 4-bit up counter for signal .
|
| 19735 |
|
|
Found 8-bit register for signal .
|
| 19736 |
|
|
Found 7-bit register for signal >.
|
| 19737 |
|
|
Found 1-bit register for signal .
|
| 19738 |
|
|
Found 1-bit register for signal .
|
| 19739 |
|
|
Summary:
|
| 19740 |
|
|
inferred 1 Counter(s).
|
| 19741 |
|
|
inferred 26 D-type flip-flop(s).
|
| 19742 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 19743 |
|
|
inferred 1 Comparator(s).
|
| 19744 |
|
|
inferred 1 Multiplexer(s).
|
| 19745 |
|
|
inferred 8 Tristate(s).
|
| 19746 |
|
|
Unit synthesized.
|
| 19747 |
|
|
|
| 19748 |
|
|
|
| 19749 |
|
|
Synthesizing Unit .
|
| 19750 |
|
|
Related source file is "jkff.v".
|
| 19751 |
|
|
Found 1-bit register for signal .
|
| 19752 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
|
| 19753 |
|
|
Summary:
|
| 19754 |
|
|
inferred 1 D-type flip-flop(s).
|
| 19755 |
|
|
inferred 1 Multiplexer(s).
|
| 19756 |
|
|
Unit synthesized.
|
| 19757 |
|
|
|
| 19758 |
|
|
|
| 19759 |
|
|
Synthesizing Unit .
|
| 19760 |
|
|
Related source file is "switchsync.v".
|
| 19761 |
|
|
Found 1-bit register for signal .
|
| 19762 |
|
|
Found 1-bit register for signal .
|
| 19763 |
|
|
Summary:
|
| 19764 |
|
|
inferred 2 D-type flip-flop(s).
|
| 19765 |
|
|
Unit synthesized.
|
| 19766 |
|
|
|
| 19767 |
|
|
|
| 19768 |
|
|
Synthesizing Unit .
|
| 19769 |
|
|
Related source file is "maindcm.v".
|
| 19770 |
|
|
Unit synthesized.
|
| 19771 |
|
|
|
| 19772 |
|
|
|
| 19773 |
|
|
Synthesizing Unit .
|
| 19774 |
|
|
Related source file is "control.v".
|
| 19775 |
|
|
Found 1-bit register for signal .
|
| 19776 |
|
|
Found 1-bit register for signal .
|
| 19777 |
|
|
Found 3-bit up counter for signal .
|
| 19778 |
|
|
Summary:
|
| 19779 |
|
|
inferred 1 Counter(s).
|
| 19780 |
|
|
inferred 2 D-type flip-flop(s).
|
| 19781 |
|
|
Unit synthesized.
|
| 19782 |
|
|
|
| 19783 |
|
|
|
| 19784 |
|
|
Synthesizing Unit .
|
| 19785 |
|
|
Related source file is "misc.v".
|
| 19786 |
|
|
Found 16-bit tristate buffer for signal .
|
| 19787 |
|
|
Summary:
|
| 19788 |
|
|
inferred 16 Tristate(s).
|
| 19789 |
|
|
Unit synthesized.
|
| 19790 |
|
|
|
| 19791 |
|
|
|
| 19792 |
|
|
Synthesizing Unit .
|
| 19793 |
|
|
Related source file is "misc.v".
|
| 19794 |
|
|
Found 16-bit tristate buffer for signal .
|
| 19795 |
|
|
Summary:
|
| 19796 |
|
|
inferred 16 Tristate(s).
|
| 19797 |
|
|
Unit synthesized.
|
| 19798 |
|
|
|
| 19799 |
|
|
|
| 19800 |
|
|
Synthesizing Unit .
|
| 19801 |
|
|
Related source file is "misc.v".
|
| 19802 |
|
|
Found 16-bit tristate buffer for signal .
|
| 19803 |
|
|
Summary:
|
| 19804 |
|
|
inferred 16 Tristate(s).
|
| 19805 |
|
|
Unit synthesized.
|
| 19806 |
|
|
|
| 19807 |
|
|
|
| 19808 |
|
|
Synthesizing Unit .
|
| 19809 |
|
|
Related source file is "misc.v".
|
| 19810 |
|
|
WARNING:Xst:647 - Input > is never used.
|
| 19811 |
|
|
Found 16-bit tristate buffer for signal .
|
| 19812 |
|
|
Found 12-bit register for signal .
|
| 19813 |
|
|
Summary:
|
| 19814 |
|
|
inferred 12 D-type flip-flop(s).
|
| 19815 |
|
|
inferred 16 Tristate(s).
|
| 19816 |
|
|
Unit synthesized.
|
| 19817 |
|
|
|
| 19818 |
|
|
|
| 19819 |
|
|
Synthesizing Unit .
|
| 19820 |
|
|
Related source file is "idecode.v".
|
| 19821 |
|
|
Unit synthesized.
|
| 19822 |
|
|
|
| 19823 |
|
|
|
| 19824 |
|
|
Synthesizing Unit .
|
| 19825 |
|
|
Related source file is "control.v".
|
| 19826 |
|
|
Unit synthesized.
|
| 19827 |
|
|
|
| 19828 |
|
|
|
| 19829 |
|
|
Synthesizing Unit .
|
| 19830 |
|
|
Related source file is "alu.v".
|
| 19831 |
|
|
Found 16-bit tristate buffer for signal .
|
| 19832 |
|
|
Found 17-bit subtractor for signal <$AUX_109>.
|
| 19833 |
|
|
Found 16-bit adder carry out for signal <$n0000>.
|
| 19834 |
|
|
Found 1-bit xor2 for signal <$n0042> created at line 6.
|
| 19835 |
|
|
Found 1-bit xor2 for signal <$n0043> created at line 6.
|
| 19836 |
|
|
Found 16-bit xor2 for signal <$n0046> created at line 31.
|
| 19837 |
|
|
Summary:
|
| 19838 |
|
|
inferred 2 Adder/Subtractor(s).
|
| 19839 |
|
|
inferred 16 Tristate(s).
|
| 19840 |
|
|
Unit synthesized.
|
| 19841 |
|
|
|
| 19842 |
|
|
|
| 19843 |
|
|
Synthesizing Unit .
|
| 19844 |
|
|
Related source file is "misc.v".
|
| 19845 |
|
|
Unit synthesized.
|
| 19846 |
|
|
|
| 19847 |
|
|
|
| 19848 |
|
|
Synthesizing Unit .
|
| 19849 |
|
|
Related source file is "misc.v".
|
| 19850 |
|
|
Unit synthesized.
|
| 19851 |
|
|
|
| 19852 |
|
|
|
| 19853 |
|
|
Synthesizing Unit .
|
| 19854 |
|
|
Related source file is "misc.v".
|
| 19855 |
|
|
Unit synthesized.
|
| 19856 |
|
|
|
| 19857 |
|
|
|
| 19858 |
|
|
Synthesizing Unit .
|
| 19859 |
|
|
Related source file is "misc.v".
|
| 19860 |
|
|
Unit synthesized.
|
| 19861 |
|
|
|
| 19862 |
|
|
|
| 19863 |
|
|
Synthesizing Unit .
|
| 19864 |
|
|
Related source file is "misc.v".
|
| 19865 |
|
|
Found 16-bit tristate buffer for signal .
|
| 19866 |
|
|
Found 16-bit register for signal .
|
| 19867 |
|
|
Summary:
|
| 19868 |
|
|
inferred 16 D-type flip-flop(s).
|
| 19869 |
|
|
inferred 16 Tristate(s).
|
| 19870 |
|
|
Unit synthesized.
|
| 19871 |
|
|
|
| 19872 |
|
|
|
| 19873 |
|
|
Synthesizing Unit .
|
| 19874 |
|
|
Related source file is "io.v".
|
| 19875 |
|
|
Found 1-bit register for signal .
|
| 19876 |
|
|
Found 1-bit register for signal .
|
| 19877 |
|
|
Found 1-bit register for signal .
|
| 19878 |
|
|
Found 1-bit register for signal .
|
| 19879 |
|
|
Found 1-bit register for signal .
|
| 19880 |
|
|
Found 1-bit register for signal .
|
| 19881 |
|
|
Found 19-bit down counter for signal .
|
| 19882 |
|
|
Found 1-bit register for signal .
|
| 19883 |
|
|
Found 1-bit xor2 for signal .
|
| 19884 |
|
|
Summary:
|
| 19885 |
|
|
inferred 1 Counter(s).
|
| 19886 |
|
|
inferred 7 D-type flip-flop(s).
|
| 19887 |
|
|
Unit synthesized.
|
| 19888 |
|
|
|
| 19889 |
|
|
|
| 19890 |
|
|
Synthesizing Unit .
|
| 19891 |
|
|
Related source file is "io.v".
|
| 19892 |
|
|
Found 16x7-bit ROM for signal <$n0005>.
|
| 19893 |
|
|
Found 1-bit register for signal .
|
| 19894 |
|
|
Found 1-bit register for signal .
|
| 19895 |
|
|
Found 1-bit register for signal .
|
| 19896 |
|
|
Found 1-bit register for signal .
|
| 19897 |
|
|
Found 1-bit register for signal .
|
| 19898 |
|
|
Found 1-bit register for signal .
|
| 19899 |
|
|
Found 1-bit register for signal .
|
| 19900 |
|
|
Found 1-bit register for signal .
|
| 19901 |
|
|
Found 1-bit register for signal .
|
| 19902 |
|
|
Found 1-bit register for signal .
|
| 19903 |
|
|
Found 1-bit register for signal .
|
| 19904 |
|
|
Found 1-bit register for signal .
|
| 19905 |
|
|
Found 24-bit up counter for signal .
|
| 19906 |
|
|
Found 1-of-4 decoder for signal .
|
| 19907 |
|
|
Found 2-bit down counter for signal .
|
| 19908 |
|
|
Found 8-bit 4-to-1 multiplexer for signal .
|
| 19909 |
|
|
Found 1-bit 4-to-1 multiplexer for signal .
|
| 19910 |
|
|
Summary:
|
| 19911 |
|
|
inferred 1 ROM(s).
|
| 19912 |
|
|
inferred 2 Counter(s).
|
| 19913 |
|
|
inferred 12 D-type flip-flop(s).
|
| 19914 |
|
|
inferred 9 Multiplexer(s).
|
| 19915 |
|
|
inferred 1 Decoder(s).
|
| 19916 |
|
|
Unit synthesized.
|
| 19917 |
|
|
|
| 19918 |
|
|
|
| 19919 |
|
|
Synthesizing Unit .
|
| 19920 |
|
|
Related source file is "uart.v".
|
| 19921 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
|
| 19922 |
|
|
Found 1-bit register for signal .
|
| 19923 |
|
|
Found 8-bit up counter for signal .
|
| 19924 |
|
|
Found 1-bit register for signal .
|
| 19925 |
|
|
Summary:
|
| 19926 |
|
|
inferred 1 Counter(s).
|
| 19927 |
|
|
inferred 2 D-type flip-flop(s).
|
| 19928 |
|
|
inferred 1 Multiplexer(s).
|
| 19929 |
|
|
Unit synthesized.
|
| 19930 |
|
|
|
| 19931 |
|
|
|
| 19932 |
|
|
Synthesizing Unit .
|
| 19933 |
|
|
Related source file is "top.v".
|
| 19934 |
|
|
WARNING:Xst:1780 - Signal > is never used or assigned.
|
| 19935 |
|
|
Found 16-bit tristate buffer for signal .
|
| 19936 |
|
|
Found 1-bit register for signal .
|
| 19937 |
|
|
Found 12-bit adder carry out for signal <$n0015> created at line 197.
|
| 19938 |
|
|
Found 16-bit tristate buffer for signal .
|
| 19939 |
|
|
Found 1-bit register for signal .
|
| 19940 |
|
|
Found 1-bit register for signal .
|
| 19941 |
|
|
Found 1-bit register for signal .
|
| 19942 |
|
|
Summary:
|
| 19943 |
|
|
inferred 4 D-type flip-flop(s).
|
| 19944 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 19945 |
|
|
inferred 96 Tristate(s).
|
| 19946 |
|
|
Unit synthesized.
|
| 19947 |
|
|
|
| 19948 |
|
|
|
| 19949 |
|
|
Synthesizing Unit .
|
| 19950 |
|
|
Related source file is "FrontPanel.v".
|
| 19951 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned.
|
| 19952 |
|
|
Found finite state machine for signal .
|
| 19953 |
|
|
-----------------------------------------------------------------------
|
| 19954 |
|
|
| States | 6 |
|
| 19955 |
|
|
| Transitions | 6 |
|
| 19956 |
|
|
| Inputs | 0 |
|
| 19957 |
|
|
| Outputs | 12 |
|
| 19958 |
|
|
| Clock | clockin (rising_edge) |
|
| 19959 |
|
|
| Clock enable | select (positive) |
|
| 19960 |
|
|
| Reset | clear (positive) |
|
| 19961 |
|
|
| Reset type | asynchronous |
|
| 19962 |
|
|
| Reset State | 000001 |
|
| 19963 |
|
|
| Encoding | automatic |
|
| 19964 |
|
|
| Implementation | LUT |
|
| 19965 |
|
|
-----------------------------------------------------------------------
|
| 19966 |
|
|
Found 16-bit 4-to-1 multiplexer for signal .
|
| 19967 |
|
|
Found 4-bit register for signal .
|
| 19968 |
|
|
Found 16-bit register for signal .
|
| 19969 |
|
|
Summary:
|
| 19970 |
|
|
inferred 1 Finite State Machine(s).
|
| 19971 |
|
|
inferred 16 D-type flip-flop(s).
|
| 19972 |
|
|
inferred 16 Multiplexer(s).
|
| 19973 |
|
|
Unit synthesized.
|
| 19974 |
|
|
|
| 19975 |
|
|
|
| 19976 |
|
|
Synthesizing Unit .
|
| 19977 |
|
|
Related source file is "topbox.v".
|
| 19978 |
|
|
WARNING:Xst:646 - Signal is assigned but never used.
|
| 19979 |
|
|
Found 16-bit tristate buffer for signal .
|
| 19980 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
|
| 19981 |
|
|
Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
|
| 19982 |
|
|
Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
|
| 19983 |
|
|
Found 4-bit adder for signal <$n0012> created at line 75.
|
| 19984 |
|
|
Found 4-bit register for signal .
|
| 19985 |
|
|
Found 1-bit register for signal .
|
| 19986 |
|
|
Found 1-bit register for signal .
|
| 19987 |
|
|
Found 16-bit register for signal .
|
| 19988 |
|
|
Summary:
|
| 19989 |
|
|
inferred 22 D-type flip-flop(s).
|
| 19990 |
|
|
inferred 1 Adder/Subtractor(s).
|
| 19991 |
|
|
inferred 6 Multiplexer(s).
|
| 19992 |
|
|
inferred 48 Tristate(s).
|
| 19993 |
|
|
Unit synthesized.
|
| 19994 |
|
|
|
| 19995 |
|
|
|
| 19996 |
|
|
=========================================================================
|
| 19997 |
|
|
* Advanced HDL Synthesis *
|
| 19998 |
|
|
=========================================================================
|
| 19999 |
|
|
|
| 20000 |
|
|
Advanced RAM inference ...
|
| 20001 |
|
|
Advanced multiplier inference ...
|
| 20002 |
|
|
Advanced Registered AddSub inference ...
|
| 20003 |
|
|
Analyzing FSM for best encoding.
|
| 20004 |
|
|
Optimizing FSM on signal with speed1 encoding.
|
| 20005 |
|
|
--------------------
|
| 20006 |
|
|
State | Encoding
|
| 20007 |
|
|
--------------------
|
| 20008 |
|
|
000001 | 100000
|
| 20009 |
|
|
000010 | 010000
|
| 20010 |
|
|
000100 | 001000
|
| 20011 |
|
|
001000 | 000100
|
| 20012 |
|
|
010000 | 000010
|
| 20013 |
|
|
100000 | 000001
|
| 20014 |
|
|
--------------------
|
| 20015 |
|
|
Dynamic shift register inference ...
|
| 20016 |
|
|
|
| 20017 |
|
|
=========================================================================
|
| 20018 |
|
|
HDL Synthesis Report
|
| 20019 |
|
|
|
| 20020 |
|
|
Macro Statistics
|
| 20021 |
|
|
# FSMs : 1
|
| 20022 |
|
|
# ROMs : 1
|
| 20023 |
|
|
16x7-bit ROM : 1
|
| 20024 |
|
|
# Adders/Subtractors : 5
|
| 20025 |
|
|
12-bit adder carry out : 1
|
| 20026 |
|
|
16-bit adder carry out : 1
|
| 20027 |
|
|
17-bit subtractor : 1
|
| 20028 |
|
|
4-bit adder : 2
|
| 20029 |
|
|
# Counters : 10
|
| 20030 |
|
|
19-bit down counter : 3
|
| 20031 |
|
|
2-bit down counter : 1
|
| 20032 |
|
|
24-bit up counter : 1
|
| 20033 |
|
|
3-bit up counter : 1
|
| 20034 |
|
|
4-bit up counter : 3
|
| 20035 |
|
|
8-bit up counter : 1
|
| 20036 |
|
|
# Registers : 138
|
| 20037 |
|
|
1-bit register : 125
|
| 20038 |
|
|
12-bit register : 4
|
| 20039 |
|
|
16-bit register : 4
|
| 20040 |
|
|
4-bit register : 3
|
| 20041 |
|
|
8-bit register : 2
|
| 20042 |
|
|
# Comparators : 3
|
| 20043 |
|
|
4-bit comparator greater : 2
|
| 20044 |
|
|
4-bit comparator less : 1
|
| 20045 |
|
|
# Multiplexers : 13
|
| 20046 |
|
|
1-bit 4-to-1 multiplexer : 10
|
| 20047 |
|
|
16-bit 4-to-1 multiplexer : 1
|
| 20048 |
|
|
4-bit 4-to-1 multiplexer : 1
|
| 20049 |
|
|
8-bit 4-to-1 multiplexer : 1
|
| 20050 |
|
|
# Decoders : 1
|
| 20051 |
|
|
1-of-4 decoder : 1
|
| 20052 |
|
|
# Tristates : 97
|
| 20053 |
|
|
1-bit tristate buffer : 80
|
| 20054 |
|
|
16-bit tristate buffer : 16
|
| 20055 |
|
|
8-bit tristate buffer : 1
|
| 20056 |
|
|
# Xors : 6
|
| 20057 |
|
|
1-bit xor2 : 5
|
| 20058 |
|
|
16-bit xor2 : 1
|
| 20059 |
|
|
|
| 20060 |
|
|
=========================================================================
|
| 20061 |
|
|
|
| 20062 |
|
|
=========================================================================
|
| 20063 |
|
|
* Low Level Synthesis *
|
| 20064 |
|
|
=========================================================================
|
| 20065 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 20066 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 20067 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 20068 |
|
|
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
|
| 20069 |
|
|
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 20070 |
|
|
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
|
| 20071 |
|
|
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
|
| 20072 |
|
|
|
| 20073 |
|
|
Optimizing unit ...
|
| 20074 |
|
|
|
| 20075 |
|
|
Optimizing unit ...
|
| 20076 |
|
|
|
| 20077 |
|
|
Optimizing unit ...
|
| 20078 |
|
|
|
| 20079 |
|
|
Optimizing unit ...
|
| 20080 |
|
|
|
| 20081 |
|
|
Optimizing unit ...
|
| 20082 |
|
|
|
| 20083 |
|
|
Optimizing unit ...
|
| 20084 |
|
|
|
| 20085 |
|
|
Optimizing unit ...
|
| 20086 |
|
|
|
| 20087 |
|
|
Optimizing unit ...
|
| 20088 |
|
|
|
| 20089 |
|
|
Optimizing unit ...
|
| 20090 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.
|
| 20091 |
|
|
|
| 20092 |
|
|
Mapping all equations...
|
| 20093 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 20094 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 20095 |
|
|
WARNING:Xst:1291 - FF/Latch is unconnected in block .
|
| 20096 |
|
|
Building and optimizing final netlist ...
|
| 20097 |
|
|
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
|
| 20098 |
|
|
Forward register balancing over CPU/decoder/opdec78 of flipflops :
|
| 20099 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 20100 |
|
|
Forward register balancing over CPU/decoder/opxor1 of flipflops :
|
| 20101 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
|
| 20102 |
|
|
Forward register balancing over CPU/decoder/opand1 of flipflops :
|
| 20103 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 20104 |
|
|
Forward register balancing over CPU/decoder/opior1 of flipflops :
|
| 20105 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
|
| 20106 |
|
|
Forward register balancing over CPU/decoder/oplda1 of flipflops :
|
| 20107 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
|
| 20108 |
|
|
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
|
| 20109 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
|
| 20110 |
|
|
Forward register balancing over Ker571 of flipflops :
|
| 20111 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 20112 |
|
|
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
|
| 20113 |
|
|
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 20114 |
|
|
Forward register balancing over Ker2101 of flipflops :
|
| 20115 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 20116 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
|
| 20117 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
|
| 20118 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
|
| 20119 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 20120 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
|
| 20121 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
|
| 20122 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
|
| 20123 |
|
|
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 20124 |
|
|
Forward register balancing over CPU/msend9 of flipflops :
|
| 20125 |
|
|
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
|
| 20126 |
|
|
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
|
| 20127 |
|
|
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
|
| 20128 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
|
| 20129 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 20130 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
|
| 20131 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 20132 |
|
|
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
|
| 20133 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 20134 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
|
| 20135 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 20136 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
|
| 20137 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
|
| 20138 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
|
| 20139 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
|
| 20140 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
|
| 20141 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 20142 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
|
| 20143 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
|
| 20144 |
|
|
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
|
| 20145 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 20146 |
|
|
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
|
| 20147 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
|
| 20148 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
|
| 20149 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 20150 |
|
|
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
|
| 20151 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
|
| 20152 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
|
| 20153 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 20154 |
|
|
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
|
| 20155 |
|
|
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
|
| 20156 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
|
| 20157 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 20158 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
|
| 20159 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 20160 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
|
| 20161 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 20162 |
|
|
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
|
| 20163 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
|
| 20164 |
|
|
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
|
| 20165 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
|
| 20166 |
|
|
Forward register balancing over Ker2161_SW0 of flipflops :
|
| 20167 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 20168 |
|
|
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
|
| 20169 |
|
|
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 20170 |
|
|
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
|
| 20171 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
|
| 20172 |
|
|
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
|
| 20173 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 20174 |
|
|
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
|
| 20175 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 20176 |
|
|
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
|
| 20177 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
|
| 20178 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
|
| 20179 |
|
|
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 20180 |
|
|
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
|
| 20181 |
|
|
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
|
| 20182 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
|
| 20183 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 20184 |
|
|
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
|
| 20185 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 20186 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
|
| 20187 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
|
| 20188 |
|
|
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
|
| 20189 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 20190 |
|
|
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
|
| 20191 |
|
|
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
|
| 20192 |
|
|
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
|
| 20193 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
|
| 20194 |
|
|
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
|
| 20195 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
|
| 20196 |
|
|
Forward register balancing over Ker161_SW0 of flipflops :
|
| 20197 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
|
| 20198 |
|
|
Forward register balancing over CPU/decoder/opdec74 of flipflops :
|
| 20199 |
|
|
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
|
| 20200 |
|
|
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
|
| 20201 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
|
| 20202 |
|
|
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
|
| 20203 |
|
|
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
|
| 20204 |
|
|
Forward register balancing over CPU/ctl/sim/Ker71 of flipflops :
|
| 20205 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
|
| 20206 |
|
|
Forward register balancing over CPU/ctl/sim/_n00121 of flipflops :
|
| 20207 |
|
|
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
|
| 20208 |
|
|
Forward register balancing over CPU/ctl/sim/_n00111 of flipflops :
|
| 20209 |
|
|
CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2.
|
| 20210 |
|
|
Forward register balancing over CPU/ctl/sim/_n00101 of flipflops :
|
| 20211 |
|
|
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
|
| 20212 |
|
|
Forward register balancing over CPU/bus<0>__n0000<0>_N01_SW0 of flipflops :
|
| 20213 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
|
| 20214 |
|
|
Forward register balancing over CPU/decoder/opadd1 of flipflops :
|
| 20215 |
|
|
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
|
| 20216 |
|
|
Forward register balancing over CPU/decoder/opdec41 of flipflops :
|
| 20217 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
|
| 20218 |
|
|
Forward register balancing over CPU/decoder/opinc41 of flipflops :
|
| 20219 |
|
|
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
|
| 20220 |
|
|
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
|
| 20221 |
|
|
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
|
| 20222 |
|
|
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
|
| 20223 |
|
|
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
|
| 20224 |
|
|
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
|
| 20225 |
|
|
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
|
| 20226 |
|
|
Forward register balancing over Ker212_SW0 of flipflops :
|
| 20227 |
|
|
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
|
| 20228 |
|
|
Forward register balancing over CPU/decoder/opdec714 of flipflops :
|
| 20229 |
|
|
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
|
| 20230 |
|
|
Forward register balancing over CPU/ctl/sim/_n00151 of flipflops :
|
| 20231 |
|
|
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_1.
|
| 20232 |
|
|
Register equivalent to has been removed
|
| 20233 |
|
|
Register equivalent to has been removed
|
| 20234 |
|
|
Register equivalent to has been removed
|
| 20235 |
|
|
Register equivalent to has been removed
|
| 20236 |
|
|
Register equivalent to has been removed
|
| 20237 |
|
|
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
|
| 20238 |
|
|
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
|
| 20239 |
|
|
FlipFlop CPU/ctl/sim/_n00111_FRB has been replicated 7 time(s)
|
| 20240 |
|
|
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
|
| 20241 |
|
|
FlipFlop loadnow has been replicated 1 time(s)
|
| 20242 |
|
|
|
| 20243 |
|
|
=========================================================================
|
| 20244 |
|
|
* Final Report *
|
| 20245 |
|
|
=========================================================================
|
| 20246 |
|
|
|
| 20247 |
|
|
Device utilization summary:
|
| 20248 |
|
|
---------------------------
|
| 20249 |
|
|
|
| 20250 |
|
|
Selected Device : 3s200ft256-4
|
| 20251 |
|
|
|
| 20252 |
|
|
Number of Slices: 617 out of 1920 32%
|
| 20253 |
|
|
Number of Slice Flip Flops: 436 out of 3840 11%
|
| 20254 |
|
|
Number of 4 input LUTs: 1082 out of 3840 28%
|
| 20255 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 20256 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 20257 |
|
|
Number of DCM_ADVs: 1 out of 4 25%
|
| 20258 |
|
|
|
| 20259 |
|
|
|
| 20260 |
|
|
=========================================================================
|
| 20261 |
|
|
TIMING REPORT
|
| 20262 |
|
|
|
| 20263 |
|
|
|
| 20264 |
|
|
Clock Information:
|
| 20265 |
|
|
------------------
|
| 20266 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 20267 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 20268 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 20269 |
|
|
clkin | CPU/ctl/clockgen/DCM_INST:CLKFX| 436 |
|
| 20270 |
|
|
-----------------------------------+--------------------------------+-------+
|
| 20271 |
|
|
|
| 20272 |
|
|
Timing Summary:
|
| 20273 |
|
|
---------------
|
| 20274 |
|
|
Speed Grade: -4
|
| 20275 |
|
|
|
| 20276 |
|
|
Minimum period: 13.584ns (Maximum Frequency: 73.618MHz)
|
| 20277 |
|
|
Minimum input arrival time before clock: 10.967ns
|
| 20278 |
|
|
Maximum output required time after clock: 23.172ns
|
| 20279 |
|
|
Maximum combinational path delay: 15.112ns
|
| 20280 |
|
|
|
| 20281 |
|
|
=========================================================================
|
| 20282 |
|
|
|
| 20283 |
|
|
|
| 20284 |
|
|
|
| 20285 |
|
|
|
| 20286 |
|
|
Started process "Translate".
|
| 20287 |
|
|
|
| 20288 |
|
|
|
| 20289 |
|
|
Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
|
| 20290 |
|
|
xc3s200-ft256-4 topbox.ngc topbox.ngd
|
| 20291 |
|
|
|
| 20292 |
|
|
Reading NGO file 'C:/blue71/topbox.ngc' ...
|
| 20293 |
|
|
|
| 20294 |
|
|
Applying constraints in "tobox.ucf" to the design...
|
| 20295 |
|
|
|
| 20296 |
|
|
Checking timing specifications ...
|
| 20297 |
|
|
CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
|
| 20298 |
|
|
TS_clkin*0.700000 HIGH 50.000000%
|
| 20299 |
|
|
CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
|
| 20300 |
|
|
20.408000 nS HIGH 50.000000%
|
| 20301 |
|
|
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
|
| 20302 |
|
|
TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
|
| 20303 |
|
|
The timing analyzer will ignore the pads for this specification. You might
|
| 20304 |
|
|
want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
|
| 20305 |
|
|
from this group.
|
| 20306 |
|
|
Checking expanded design ...
|
| 20307 |
|
|
|
| 20308 |
|
|
NGDBUILD Design Results Summary:
|
| 20309 |
|
|
Number of errors: 0
|
| 20310 |
|
|
Number of warnings: 1
|
| 20311 |
|
|
|
| 20312 |
|
|
Writing NGD file "topbox.ngd" ...
|
| 20313 |
|
|
|
| 20314 |
|
|
Writing NGDBUILD log file "topbox.bld"...
|
| 20315 |
|
|
|
| 20316 |
|
|
NGDBUILD done.
|
| 20317 |
|
|
|
| 20318 |
|
|
|
| 20319 |
|
|
|
| 20320 |
|
|
|
| 20321 |
|
|
Started process "Map".
|
| 20322 |
|
|
|
| 20323 |
|
|
Using target part "3s200ft256-4".
|
| 20324 |
|
|
Mapping design into LUTs...
|
| 20325 |
|
|
Running directed packing...
|
| 20326 |
|
|
Running delay-based LUT packing...
|
| 20327 |
|
|
Running timing-driven packing...
|
| 20328 |
|
|
|
| 20329 |
|
|
Phase 1.1
|
| 20330 |
|
|
Phase 1.1 (Checksum:98d1ef) REAL time: 0 secs
|
| 20331 |
|
|
|
| 20332 |
|
|
Phase 2.31
|
| 20333 |
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs
|
| 20334 |
|
|
|
| 20335 |
|
|
Phase 3.2
|
| 20336 |
|
|
.
|
| 20337 |
|
|
|
| 20338 |
|
|
|
| 20339 |
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
|
| 20340 |
|
|
|
| 20341 |
|
|
Phase 4.4
|
| 20342 |
|
|
..............
|
| 20343 |
|
|
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs
|
| 20344 |
|
|
|
| 20345 |
|
|
Phase 5.28
|
| 20346 |
|
|
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs
|
| 20347 |
|
|
|
| 20348 |
|
|
Phase 6.8
|
| 20349 |
|
|
.....................
|
| 20350 |
|
|
........
|
| 20351 |
|
|
........................................
|
| 20352 |
|
|
...............
|
| 20353 |
|
|
...............
|
| 20354 |
|
|
Phase 6.8 (Checksum:ab675f) REAL time: 11 secs
|
| 20355 |
|
|
|
| 20356 |
|
|
Phase 7.29
|
| 20357 |
|
|
Phase 7.29 (Checksum:42c1d79) REAL time: 11 secs
|
| 20358 |
|
|
|
| 20359 |
|
|
Phase 8.5
|
| 20360 |
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 11 secs
|
| 20361 |
|
|
|
| 20362 |
|
|
Phase 9.18
|
| 20363 |
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 21 secs
|
| 20364 |
|
|
|
| 20365 |
|
|
Phase 10.5
|
| 20366 |
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 21 secs
|
| 20367 |
|
|
|
| 20368 |
|
|
|
| 20369 |
|
|
Design Summary:
|
| 20370 |
|
|
Number of errors: 0
|
| 20371 |
|
|
Number of warnings: 11
|
| 20372 |
|
|
Logic Utilization:
|
| 20373 |
|
|
Number of Slice Flip Flops: 410 out of 3,840 10%
|
| 20374 |
|
|
Number of 4 input LUTs: 1,131 out of 3,840 29%
|
| 20375 |
|
|
Logic Distribution:
|
| 20376 |
|
|
Number of occupied Slices: 679 out of 1,920 35%
|
| 20377 |
|
|
Number of Slices containing only related logic: 679 out of 679 100%
|
| 20378 |
|
|
Number of Slices containing unrelated logic: 0 out of 679 0%
|
| 20379 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 20380 |
|
|
Total Number 4 input LUTs: 1,136 out of 3,840 29%
|
| 20381 |
|
|
Number used as logic: 1,131
|
| 20382 |
|
|
Number used as a route-thru: 5
|
| 20383 |
|
|
Number of bonded IOBs: 74 out of 173 42%
|
| 20384 |
|
|
IOB Flip Flops: 26
|
| 20385 |
|
|
Number of GCLKs: 2 out of 8 25%
|
| 20386 |
|
|
Number of DCMs: 1 out of 4 25%
|
| 20387 |
|
|
|
| 20388 |
|
|
Total equivalent gate count for design: 18,144
|
| 20389 |
|
|
Additional JTAG gate count for IOBs: 3,552
|
| 20390 |
|
|
Peak Memory Usage: 133 MB
|
| 20391 |
|
|
|
| 20392 |
|
|
Mapping completed.
|
| 20393 |
|
|
See MAP report file "topbox_map.mrp" for details.
|
| 20394 |
|
|
|
| 20395 |
|
|
|
| 20396 |
|
|
|
| 20397 |
|
|
|
| 20398 |
|
|
Started process "Place & Route".
|
| 20399 |
|
|
|
| 20400 |
|
|
|
| 20401 |
|
|
|
| 20402 |
|
|
|
| 20403 |
|
|
Constraints file: topbox.pcf.
|
| 20404 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 20405 |
|
|
C:/Xilinx71.
|
| 20406 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 20407 |
|
|
|
| 20408 |
|
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
|
| 20409 |
|
|
Celsius)
|
| 20410 |
|
|
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
|
| 20411 |
|
|
|
| 20412 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 20413 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 20414 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 20415 |
|
|
ps (24.00 Mhz).
|
| 20416 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 20417 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 20418 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 20419 |
|
|
(210.04 Mhz).
|
| 20420 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 20421 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 20422 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 20423 |
|
|
ps (24.00 Mhz).
|
| 20424 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 20425 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 20426 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 20427 |
|
|
(210.04 Mhz).
|
| 20428 |
|
|
|
| 20429 |
|
|
Device speed data version: "PRODUCTION 1.35 2005-01-22".
|
| 20430 |
|
|
|
| 20431 |
|
|
|
| 20432 |
|
|
INFO:Par:253 - The Map -timing placement will be retained since it is likely to
|
| 20433 |
|
|
achieve better performance.
|
| 20434 |
|
|
|
| 20435 |
|
|
Device Utilization Summary:
|
| 20436 |
|
|
|
| 20437 |
|
|
Number of BUFGMUXs 2 out of 8 25%
|
| 20438 |
|
|
Number of DCMs 1 out of 4 25%
|
| 20439 |
|
|
Number of External IOBs 74 out of 173 42%
|
| 20440 |
|
|
Number of LOCed IOBs 74 out of 74 100%
|
| 20441 |
|
|
|
| 20442 |
|
|
Number of Slices 679 out of 1920 35%
|
| 20443 |
|
|
Number of SLICEMs 0 out of 960 0%
|
| 20444 |
|
|
|
| 20445 |
|
|
|
| 20446 |
|
|
|
| 20447 |
|
|
Overall effort level (-ol): High (set by user)
|
| 20448 |
|
|
Router effort level (-rl): High (set by user)
|
| 20449 |
|
|
|
| 20450 |
|
|
Starting initial Timing Analysis. REAL time: 5 secs
|
| 20451 |
|
|
Finished initial Timing Analysis. REAL time: 5 secs
|
| 20452 |
|
|
|
| 20453 |
|
|
Starting Router
|
| 20454 |
|
|
|
| 20455 |
|
|
Phase 1: 4917 unrouted; REAL time: 5 secs
|
| 20456 |
|
|
|
| 20457 |
|
|
Phase 2: 4563 unrouted; REAL time: 5 secs
|
| 20458 |
|
|
|
| 20459 |
|
|
Phase 3: 2325 unrouted; REAL time: 6 secs
|
| 20460 |
|
|
|
| 20461 |
|
|
Phase 4: 2325 unrouted; (0) REAL time: 6 secs
|
| 20462 |
|
|
|
| 20463 |
|
|
Phase 5: 2325 unrouted; (0) REAL time: 7 secs
|
| 20464 |
|
|
|
| 20465 |
|
|
Phase 6: 2325 unrouted; (0) REAL time: 7 secs
|
| 20466 |
|
|
|
| 20467 |
|
|
Phase 7: 0 unrouted; (0) REAL time: 15 secs
|
| 20468 |
|
|
|
| 20469 |
|
|
Phase 8: 0 unrouted; (0) REAL time: 16 secs
|
| 20470 |
|
|
|
| 20471 |
|
|
|
| 20472 |
|
|
Total REAL time to Router completion: 17 secs
|
| 20473 |
|
|
Total CPU time to Router completion: 16 secs
|
| 20474 |
|
|
|
| 20475 |
|
|
Generating "PAR" statistics.
|
| 20476 |
|
|
|
| 20477 |
|
|
**************************
|
| 20478 |
|
|
Generating Clock Report
|
| 20479 |
|
|
**************************
|
| 20480 |
|
|
|
| 20481 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 20482 |
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
| 20483 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 20484 |
|
|
| clk | BUFGMUX2| No | 336 | 0.041 | 1.051 |
|
| 20485 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
| 20486 |
|
|
|
| 20487 |
|
|
Timing Score: 0
|
| 20488 |
|
|
|
| 20489 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
| 20490 |
|
|
This may be due to a setup or hold violation.
|
| 20491 |
|
|
|
| 20492 |
|
|
--------------------------------------------------------------------------------
|
| 20493 |
|
|
Constraint | Requested | Actual | Logic
|
| 20494 |
|
|
| | | Levels
|
| 20495 |
|
|
--------------------------------------------------------------------------------
|
| 20496 |
|
|
TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz | N/A | N/A | N/A
|
| 20497 |
|
|
HIGH 50% | | |
|
| 20498 |
|
|
--------------------------------------------------------------------------------
|
| 20499 |
|
|
TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns | 27.694ns | 5
|
| 20500 |
|
|
MEGRP "CPU_ctl_clockgen_CLKFX_BUF" | | |
|
| 20501 |
|
|
TS_clkin * 0.7 HIGH 50% | | |
|
| 20502 |
|
|
--------------------------------------------------------------------------------
|
| 20503 |
|
|
TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns | 40.530ns | 10
|
| 20504 |
|
|
_wclk" TS_clkin * 0.7 PHASE 20.408 ns | | |
|
| 20505 |
|
|
HIGH 50% | | |
|
| 20506 |
|
|
--------------------------------------------------------------------------------
|
| 20507 |
|
|
|
| 20508 |
|
|
|
| 20509 |
|
|
All constraints were met.
|
| 20510 |
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
| 20511 |
|
|
constraint does not cover any paths or that it has no requested value.
|
| 20512 |
|
|
Generating Pad Report.
|
| 20513 |
|
|
|
| 20514 |
|
|
All signals are completely routed.
|
| 20515 |
|
|
|
| 20516 |
|
|
Total REAL time to PAR completion: 19 secs
|
| 20517 |
|
|
Total CPU time to PAR completion: 18 secs
|
| 20518 |
|
|
|
| 20519 |
|
|
Peak Memory Usage: 95 MB
|
| 20520 |
|
|
|
| 20521 |
|
|
Placer: Not run.
|
| 20522 |
|
|
Routing: Completed - No errors found.
|
| 20523 |
|
|
Timing: Completed - No errors found.
|
| 20524 |
|
|
|
| 20525 |
|
|
Number of error messages: 0
|
| 20526 |
|
|
Number of warning messages: 4
|
| 20527 |
|
|
Number of info messages: 1
|
| 20528 |
|
|
|
| 20529 |
|
|
Writing design to file topbox.ncd
|
| 20530 |
|
|
|
| 20531 |
|
|
|
| 20532 |
|
|
|
| 20533 |
|
|
PAR done!
|
| 20534 |
|
|
|
| 20535 |
|
|
Started process "Generate Post-Place & Route Static Timing".
|
| 20536 |
|
|
|
| 20537 |
|
|
Loading device for application Rf_Device from file '3s200.nph' in environment
|
| 20538 |
|
|
C:/Xilinx71.
|
| 20539 |
|
|
"topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
|
| 20540 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
|
| 20541 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 20542 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 20543 |
|
|
ps (24.00 Mhz).
|
| 20544 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
|
| 20545 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 20546 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 20547 |
|
|
(210.04 Mhz).
|
| 20548 |
|
|
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 20549 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 20550 |
|
|
(24.50 Mhz). This violates the minimum period (maximum frequency) of 41666
|
| 20551 |
|
|
ps (24.00 Mhz).
|
| 20552 |
|
|
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
|
| 20553 |
|
|
CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
|
| 20554 |
|
|
(24.50 Mhz). This violates the maximum period (minimum frequency) of 4761 ps
|
| 20555 |
|
|
(210.04 Mhz).
|
| 20556 |
|
|
|
| 20557 |
|
|
Analysis completed Sat Sep 30 20:50:01 2006
|
| 20558 |
|
|
--------------------------------------------------------------------------------
|
| 20559 |
|
|
|
| 20560 |
|
|
Generating Report ...
|
| 20561 |
|
|
|
| 20562 |
|
|
Number of warnings: 4
|
| 20563 |
|
|
Total time: 3 secs
|
| 20564 |
|
|
|
| 20565 |
|
|
|
| 20566 |
|
|
|
| 20567 |
|
|
|
| 20568 |
|
|
|
| 20569 |
|
|
|
| 20570 |
|
|
|
| 20571 |
|
|
Started process "Generate Programming File".
|
| 20572 |
|
|
|
| 20573 |
|
|
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
|
| 20574 |
|
|
with the CLKFX and CLKFX180 outputs of the DCM comp
|
| 20575 |
|
|
CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
|
| 20576 |
|
|
Interactive Data Sheet.
|
| 20577 |
|
|
|
