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wd5gnr |
##### >>> UCF File for Xilinx Spartan-3 FPGA Board <<< #####
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### Created by Spartan-3 UCF Generator on 12/28/2005 at 12:26
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### Spartan-3 Clock Oscillator:
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NET clkin LOC=T9; # CLK - 50MHz oscillator
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### Spartan-3 Pushbutton Switches:
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NET pb0 LOC=L14; # BTN3 (active high)
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NET pb1 LOC=L13; # BTN2 (active high)
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NET pb2 LOC=M14; # BTN1 (active high)
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NET pb3 LOC=M13; # BTN0 (active high)
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### Spartan-3 Slide Switches:
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NET sw[7] LOC=K13; # SW7 (active high when up)
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NET sw[6] LOC=K14; # SW6 (active high when up)
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NET sw[5] LOC=J13; # SW5 (active high when up)
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NET sw[4] LOC=J14; # SW4 (active high when up)
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NET sw[3] LOC=H13; # SW3 (active high when up)
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NET sw[2] LOC=H14; # SW2 (active high when up)
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NET sw[1] LOC=G12; # SW1 (active high when up)
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NET sw[0] LOC=F12; # SW0 (active high when up)
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### Spartan-3 Discrete LEDs:
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NET led[7] LOC=P11; # LD7 (active high)
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NET led[6] LOC=P12; # LD6 (active high)
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NET led[5] LOC=N12; # LD5 (active high)
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NET led[4] LOC=P13; # LD4 (active high)
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NET led[3] LOC=N14; # LD3 (active high)
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NET led[2] LOC=L12; # LD2 (active high)
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NET led[1] LOC=P14; # LD1 (active high)
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NET led[0] LOC=K12; # LD0 (active high)
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### Spartan-3 7-Segment LED: digit enables:
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NET digsel[3] LOC=E13; # left digit (active low)
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NET digsel[2] LOC=F14; # middle left digit (active low)
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NET digsel[1] LOC=G14; # middle right digit (active low)
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NET digsel[0] LOC=D14; # right digit (active low)
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### Spartan-3 7-Segment LED: segment enables:
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NET display[0] LOC=E14; # LED display segment a (active low)
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NET display[1] LOC=G13; # LED display segment b (active low)
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NET display[2] LOC=N15; # LED display segment c (active low)
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NET display[3] LOC=P15; # LED display segment d (active low)
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NET display[4] LOC=R16; # LED display segment e (active low)
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NET display[5] LOC=F13; # LED display segment f (active low)
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NET display[6] LOC=N16; # LED display segment g (active low)
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NET dp LOC=P16; # LED display decimal point (active low)
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CONFIG PROHIBIT=T13;
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CONFIG PROHIBIT=R13;
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CONFIG PROHIBIT=N10;
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CONFIG PROHIBIT=T14;
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CONFIG PROHIBIT=M16;
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CONFIG PROHIBIT=M15;
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CONFIG PROHIBIT=R12;
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CONFIG PROHIBIT=T12;
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CONFIG PROHIBIT=R11;
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CONFIG PROHIBIT=R9;
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CONFIG PROHIBIT=T10;
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### Spartan-3 SRAM:Enables for IC10:
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NET xmce LOC=P7; # CE1 - chip enable (active low)
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NET xmub LOC=T4; # UB1 - upper byte enable (active low)
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NET xmlb LOC=P6; # LB1 - lower byte enable (active low)
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CONFIG PROHIBIT=N5;
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CONFIG PROHIBIT=R4;
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CONFIG PROHIBIT=P5;
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### Spartan-3 SRAM:Enables for both IC10 and IC11:
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NET xmsend LOC=K4; # OE - output enable (active low)
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NET xmwrite LOC=G3; # WE - write enable (active low)
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### Spartan-3 SRAM:Address for both IC10 and IC11:
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NET xmaddress[17] LOC=L3; # A17
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NET xmaddress[16] LOC=K5; # A16
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NET xmaddress[15] LOC=K3; # A15
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NET xmaddress[14] LOC=J3; # A14
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NET xmaddress[13] LOC=J4; # A13
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NET xmaddress[12] LOC=H4; # A12
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NET xmaddress[11] LOC=H3; # A11
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NET xmaddress[10] LOC=G5; # A10
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NET xmaddress[9] LOC=E4; # A9
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NET xmaddress[8] LOC=E3; # A8
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NET xmaddress[7] LOC=F4; # A7
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NET xmaddress[6] LOC=F3; # A6
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NET xmaddress[5] LOC=G4; # A5
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NET xmaddress[4] LOC=L4; # A4
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NET xmaddress[3] LOC=M3; # A3
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NET xmaddress[2] LOC=M4; # A2
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NET xmaddress[1] LOC=N3; # A1
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NET xmaddress[0] LOC=L5; # A0
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### Spartan-3 SRAM:Data for IC10:
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NET xmdata[15] LOC=R1; # D15
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NET xmdata[14] LOC=P1; # D14
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NET xmdata[13] LOC=L2; # D13
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NET xmdata[12] LOC=J2; # D12
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NET xmdata[11] LOC=H1; # D11
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NET xmdata[10] LOC=F2; # D10
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NET xmdata[9] LOC=P8; # D9
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NET xmdata[8] LOC=D3; # D8
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NET xmdata[7] LOC=B1; # D7
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NET xmdata[6] LOC=C1; # D6
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NET xmdata[5] LOC=C2; # D5
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NET xmdata[4] LOC=R5; # D4
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NET xmdata[3] LOC=T5; # D3
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NET xmdata[2] LOC=R6; # D2
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NET xmdata[1] LOC=T8; # D1
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NET xmdata[0] LOC=N7; # D0
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CONFIG PROHIBIT=N1;
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CONFIG PROHIBIT=M1;
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CONFIG PROHIBIT=K2;
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CONFIG PROHIBIT=C3;
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CONFIG PROHIBIT=F5;
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CONFIG PROHIBIT=G1;
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CONFIG PROHIBIT=E2;
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CONFIG PROHIBIT=D2;
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CONFIG PROHIBIT=D1;
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CONFIG PROHIBIT=E1;
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CONFIG PROHIBIT=G2;
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CONFIG PROHIBIT=J1;
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CONFIG PROHIBIT=K1;
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CONFIG PROHIBIT=M2;
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CONFIG PROHIBIT=N2;
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CONFIG PROHIBIT=P2;
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