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$date

    Fri Dec  9 00:29:55 2005

$end

$version

    GPLCVER_2.11a of 07/05/05

$end

$timescale

    1 ns

$end

$scope module one $end

$var wire      16 )    dout [15:0] $end

$var wire       1 *    send $end

$upscope $end

$scope module register $end

$var wire       1 +    clk $end

$var wire      16 ,    din [15:0] $end

$var wire      16 -    dout [15:0] $end

$var reg      16 .    regvalue [15:0] $end

$var wire       1 /    send $end

$var wire       1 0    write $end

$upscope $end

$scope module t_and $end

$var reg       1 1    a $end

$var reg       1 2    b $end

$var wire       1 3    q $end

$scope module U0 $end

$var wire       1 &    a $end

$var wire       1 '    b $end

$var wire       1 (    z $end

$scope module uint $end

$var wire       1 !    a $end

$var wire       1 "    b $end

$var wire       1 #    c $end

$var wire       1 $    d $end

$var wire       1 %    z $end

$upscope $end

$upscope $end

$upscope $end

$enddefinitions $end

#0

$dumpvars

0!

0"

1#

1$

z%

0&

0'

z(

bx )

z*

z+

bz ,

bx -

b0 .

z/

z0

01

02

z3

$end

#10

1!

1&

11

#20

13

1(

1%

1"

1'

12

#25

z3

z(

z%

0!

0&

01

#50