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wd5gnr |
#ChipScope Core Inserter Project File Version 3.0
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#Sat Oct 07 01:19:06 CDT 2006
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Project.device.designInputFile=C\:\\blue8\\topbox_cs.ngc
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Project.device.designOutputFile=C\:\\blue8\\topbox_cs.ngc
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Project.device.deviceFamily=6
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Project.device.enableRPMs=true
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Project.device.outputDirectory=C\:\\blue8\\_ngo
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Project.device.useSRL16=true
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Project.filter.dimension=19
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Project.filter<0>=iomem
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Project.filter<10>=xmadd
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Project.filter<11>=*sw*
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Project.filter<12>=xmaddress
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Project.filter<13>=*cpw*
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Project.filter<14>=CPU/PC*
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Project.filter<15>=*cp*
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Project.filter<16>=CPU/cp*
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Project.filter<17>=CPU*
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Project.filter<18>=CPU
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Project.filter<1>=*ent*
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Project.filter<2>=*load*
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Project.filter<3>=
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Project.filter<4>=CPU/*
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Project.filter<5>=*mab*
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Project.filter<6>=*mabus*
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Project.filter<7>=*ma*
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Project.filter<8>=*xm*
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Project.filter<9>=*xmadd*
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Project.icon.boundaryScanChain=0
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Project.icon.disableBUFGInsertion=false
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Project.icon.enableExtTriggerIn=false
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Project.icon.enableExtTriggerOut=false
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Project.icon.triggerInPinName=
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Project.icon.triggerOutPinName=
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Project.unit.dimension=1
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Project.unit<0>.clockChannel=clk
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Project.unit<0>.clockEdge=Rising
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Project.unit<0>.dataChannel<0>=CPU/bus<15>
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Project.unit<0>.dataChannel<10>=CPU/bus<5>
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Project.unit<0>.dataChannel<11>=CPU/bus<4>
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Project.unit<0>.dataChannel<12>=CPU/bus<3>
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Project.unit<0>.dataChannel<13>=CPU/bus<2>
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Project.unit<0>.dataChannel<14>=CPU/bus<1>
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Project.unit<0>.dataChannel<15>=CPU/bus<0>
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Project.unit<0>.dataChannel<16>=sw_7_IBUF
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Project.unit<0>.dataChannel<17>=sw_6_IBUF
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Project.unit<0>.dataChannel<18>=sw_5_IBUF
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Project.unit<0>.dataChannel<19>=sw_4_IBUF
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Project.unit<0>.dataChannel<1>=CPU/bus<14>
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Project.unit<0>.dataChannel<20>=sw_3_IBUF
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Project.unit<0>.dataChannel<21>=sw_2_IBUF
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Project.unit<0>.dataChannel<22>=sw_1_IBUF
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Project.unit<0>.dataChannel<23>=sw_0_IBUF
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Project.unit<0>.dataChannel<24>=iomem
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Project.unit<0>.dataChannel<25>=panel/switches<7>
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Project.unit<0>.dataChannel<26>=panel/switches<6>
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Project.unit<0>.dataChannel<27>=panel/switches<5>
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Project.unit<0>.dataChannel<28>=panel/switches<4>
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Project.unit<0>.dataChannel<29>=panel/switches<3>
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Project.unit<0>.dataChannel<2>=CPU/bus<13>
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Project.unit<0>.dataChannel<30>=panel/switches<2>
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Project.unit<0>.dataChannel<31>=panel/switches<1>
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Project.unit<0>.dataChannel<32>=panel/switches<0>
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Project.unit<0>.dataChannel<33>=iomem
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Project.unit<0>.dataChannel<34>=cpusend
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Project.unit<0>.dataChannel<35>=cpuwrite
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Project.unit<0>.dataChannel<3>=CPU/bus<12>
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Project.unit<0>.dataChannel<4>=CPU/bus<11>
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Project.unit<0>.dataChannel<5>=CPU/bus<10>
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Project.unit<0>.dataChannel<6>=CPU/bus<9>
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Project.unit<0>.dataChannel<7>=CPU/bus<8>
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Project.unit<0>.dataChannel<8>=CPU/bus<7>
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Project.unit<0>.dataChannel<9>=CPU/bus<6>
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Project.unit<0>.dataDepth=512
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Project.unit<0>.dataEqualsTrigger=false
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Project.unit<0>.dataPortWidth=36
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Project.unit<0>.enableGaps=false
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Project.unit<0>.enableStorageQualification=true
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Project.unit<0>.enableTimestamps=false
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Project.unit<0>.timestampDepth=0
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Project.unit<0>.timestampWidth=0
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Project.unit<0>.triggerChannel<0><0>=iomem
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Project.unit<0>.triggerConditionCountWidth=0
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Project.unit<0>.triggerMatchCount<0>=1
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Project.unit<0>.triggerMatchCountWidth<0><0>=0
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Project.unit<0>.triggerMatchType<0><0>=0
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Project.unit<0>.triggerPortCount=1
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Project.unit<0>.triggerPortIsData<0>=true
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Project.unit<0>.triggerPortWidth<0>=1
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Project.unit<0>.triggerSequencerLevels=16
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Project.unit<0>.triggerSequencerType=1
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Project.unit<0>.type=ilapro
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