OpenCores
URL https://opencores.org/ocsvn/blue/blue/trunk

Subversion Repositories blue

[/] [blue/] [trunk/] [blue8/] [control1.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 wd5gnr
/*
2
    This file is part of Blue8.
3
 
4
    Foobar is free software: you can redistribute it and/or modify
5
    it under the terms of the GNU Lesser General Public License as published by
6
    the Free Software Foundation, either version 3 of the License, or
7
    (at your option) any later version.
8
 
9
    Foobar is distributed in the hope that it will be useful,
10
    but WITHOUT ANY WARRANTY; without even the implied warranty of
11
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
    GNU Lesser General Public License for more details.
13
 
14
    You should have received a copy of the GNU Lesser General Public License
15
    along with Blue8.  If not, see <http://www.gnu.org/licenses/>.
16
 
17
    Blue8 by Al Williams alw@al-williams.com
18
*/
19
 
20
`timescale 1ns / 1ps
21
`default_nettype none
22
//////////////////////////////////////////////////////////////////////////////////
23
// Company: 
24
// Engineer: 
25
// 
26
// Create Date:    00:37:29 10/08/2006 
27
// Design Name: 
28
// Module Name:    control1 
29
// Project Name: 
30
// Target Devices: 
31
// Tool versions: 
32
// Description: 
33
//
34
// Dependencies: 
35
//
36
// Revision: 
37
// Revision 0.01 - File Created
38
// Additional Comments: 
39
//
40
//////////////////////////////////////////////////////////////////////////////////
41
 
42
module control(input wire clkinput, input wire extstart, input wire extstop, input wire extexam,
43
   input wire extdeposit, input wire ihlt, input wire aluov, output wire [8:1] cp,
44
        output wire [8:1] cpw, input wire extreset, output wire reset,
45
        output wire sw2bus, output wire loadpc1, input wire extloadpc, output wire exout, output wire depout,
46
        output wire running, output wire clkout, input wire abortcycle);
47
        wire wclk;
48
        controlclk sim(extstart,extstop,extexam,extdeposit,ihlt,aluov,cp,cpw,extreset,reset,
49
        sw2bus,loadpc1,extloadpc,exout,depout,running,clkout,wclk, abortcycle);
50
 
51
// Instantiate the DCM
52
maindcm clockgen (
53
    .CLKIN_IN(clkinput),
54
    .RST_IN(1'b0),
55
    .CLKFX_OUT(clkout),
56
    .CLKFX180_OUT(wclk)
57
    );
58
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.