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[/] [blue/] [trunk/] [blue8/] [dla.cdc] - Blame information for rev 4

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Line No. Rev Author Line
1 2 wd5gnr 
#ChipScope Core Inserter Project File Version 3.0
2 
#Mon Oct 09 17:44:37 CDT 2006
3 
Project.device.designInputFile=C\:\\blue8\\topbox_cs.ngc
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Project.device.designOutputFile=C\:\\blue8\\topbox_cs.ngc
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Project.device.deviceFamily=6
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Project.device.enableRPMs=true
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Project.device.outputDirectory=C\:\\blue8\\_ngo
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Project.device.useSRL16=true
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Project.filter.dimension=2
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Project.filter<0>=*run*
11 
Project.filter<1>=
12 
Project.icon.boundaryScanChain=0
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Project.icon.disableBUFGInsertion=false
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Project.icon.enableExtTriggerIn=false
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Project.icon.enableExtTriggerOut=false
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Project.icon.triggerInPinName=
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Project.icon.triggerOutPinName=
18 
Project.unit.dimension=1
19 
Project.unit<0>.clockChannel=clk
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Project.unit<0>.clockEdge=Rising
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Project.unit<0>.dataChannel<0>=CPU/pc/areg/regvalue<0>
22 
Project.unit<0>.dataChannel<10>=CPU/pc/areg/regvalue<10>
23 
Project.unit<0>.dataChannel<11>=CPU/pc/areg/regvalue<11>
24 
Project.unit<0>.dataChannel<12>=CPU/acc/regvalue<0>
25 
Project.unit<0>.dataChannel<13>=CPU/acc/regvalue<1>
26 
Project.unit<0>.dataChannel<14>=CPU/acc/regvalue<2>
27 
Project.unit<0>.dataChannel<15>=CPU/acc/regvalue<3>
28 
Project.unit<0>.dataChannel<16>=CPU/acc/regvalue<4>
29 
Project.unit<0>.dataChannel<17>=CPU/acc/regvalue<5>
30 
Project.unit<0>.dataChannel<18>=CPU/acc/regvalue<6>
31 
Project.unit<0>.dataChannel<19>=CPU/acc/regvalue<7>
32 
Project.unit<0>.dataChannel<1>=CPU/pc/areg/regvalue<1>
33 
Project.unit<0>.dataChannel<20>=CPU/acc/regvalue<8>
34 
Project.unit<0>.dataChannel<21>=CPU/acc/regvalue<9>
35 
Project.unit<0>.dataChannel<22>=CPU/acc/regvalue<10>
36 
Project.unit<0>.dataChannel<23>=CPU/acc/regvalue<11>
37 
Project.unit<0>.dataChannel<24>=CPU/acc/regvalue<12>
38 
Project.unit<0>.dataChannel<25>=CPU/acc/regvalue<13>
39 
Project.unit<0>.dataChannel<26>=CPU/acc/regvalue<14>
40 
Project.unit<0>.dataChannel<27>=CPU/acc/regvalue<15>
41 
Project.unit<0>.dataChannel<28>=CPU/IR/regvalue<0>
42 
Project.unit<0>.dataChannel<29>=CPU/IR/regvalue<1>
43 
Project.unit<0>.dataChannel<2>=CPU/pc/areg/regvalue<2>
44 
Project.unit<0>.dataChannel<30>=CPU/IR/regvalue<2>
45 
Project.unit<0>.dataChannel<31>=CPU/IR/regvalue<3>
46 
Project.unit<0>.dataChannel<32>=CPU/IR/regvalue<4>
47 
Project.unit<0>.dataChannel<33>=CPU/IR/regvalue<5>
48 
Project.unit<0>.dataChannel<34>=CPU/IR/regvalue<6>
49 
Project.unit<0>.dataChannel<35>=CPU/IR/regvalue<7>
50 
Project.unit<0>.dataChannel<36>=CPU/IR/regvalue<8>
51 
Project.unit<0>.dataChannel<37>=CPU/IR/regvalue<9>
52 
Project.unit<0>.dataChannel<38>=CPU/IR/regvalue<10>
53 
Project.unit<0>.dataChannel<39>=CPU/IR/regvalue<11>
54 
Project.unit<0>.dataChannel<3>=CPU/pc/areg/regvalue<3>
55 
Project.unit<0>.dataChannel<40>=CPU/IR/regvalue<12>
56 
Project.unit<0>.dataChannel<41>=CPU/IR/regvalue<13>
57 
Project.unit<0>.dataChannel<42>=CPU/IR/regvalue<14>
58 
Project.unit<0>.dataChannel<43>=CPU/IR/regvalue<15>
59 
Project.unit<0>.dataChannel<4>=CPU/pc/areg/regvalue<4>
60 
Project.unit<0>.dataChannel<5>=CPU/pc/areg/regvalue<5>
61 
Project.unit<0>.dataChannel<6>=CPU/pc/areg/regvalue<6>
62 
Project.unit<0>.dataChannel<7>=CPU/pc/areg/regvalue<7>
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Project.unit<0>.dataChannel<8>=CPU/pc/areg/regvalue<8>
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Project.unit<0>.dataChannel<9>=CPU/pc/areg/regvalue<9>
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Project.unit<0>.dataDepth=512
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Project.unit<0>.dataEqualsTrigger=false
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Project.unit<0>.dataPortWidth=44
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Project.unit<0>.enableGaps=false
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Project.unit<0>.enableStorageQualification=true
70 
Project.unit<0>.enableTimestamps=false
71 
Project.unit<0>.timestampDepth=0
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Project.unit<0>.timestampWidth=0
73 
Project.unit<0>.triggerChannel<0><0>=CPU/pc/areg/regvalue<0>
74 
Project.unit<0>.triggerChannel<0><10>=CPU/pc/areg/regvalue<10>
75 
Project.unit<0>.triggerChannel<0><11>=CPU/pc/areg/regvalue<11>
76 
Project.unit<0>.triggerChannel<0><1>=CPU/pc/areg/regvalue<1>
77 
Project.unit<0>.triggerChannel<0><2>=CPU/pc/areg/regvalue<2>
78 
Project.unit<0>.triggerChannel<0><3>=CPU/pc/areg/regvalue<3>
79 
Project.unit<0>.triggerChannel<0><4>=CPU/pc/areg/regvalue<4>
80 
Project.unit<0>.triggerChannel<0><5>=CPU/pc/areg/regvalue<5>
81 
Project.unit<0>.triggerChannel<0><6>=CPU/pc/areg/regvalue<6>
82 
Project.unit<0>.triggerChannel<0><7>=CPU/pc/areg/regvalue<7>
83 
Project.unit<0>.triggerChannel<0><8>=CPU/pc/areg/regvalue<8>
84 
Project.unit<0>.triggerChannel<0><9>=CPU/pc/areg/regvalue<9>
85 
Project.unit<0>.triggerChannel<1><0>=CPU/ctl/sim/RUN/q
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Project.unit<0>.triggerConditionCountWidth=0
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Project.unit<0>.triggerMatchCount<0>=1
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Project.unit<0>.triggerMatchCount<1>=1
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Project.unit<0>.triggerMatchCountWidth<0><0>=0
90 
Project.unit<0>.triggerMatchCountWidth<1><0>=0
91 
Project.unit<0>.triggerMatchType<0><0>=0
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Project.unit<0>.triggerMatchType<1><0>=0
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Project.unit<0>.triggerPortCount=2
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Project.unit<0>.triggerPortIsData<0>=true
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Project.unit<0>.triggerPortIsData<1>=true
96 
Project.unit<0>.triggerPortWidth<0>=12
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Project.unit<0>.triggerPortWidth<1>=1
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Project.unit<0>.triggerSequencerLevels=16
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Project.unit<0>.triggerSequencerType=1
100 
Project.unit<0>.type=ilapro

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