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[/] [blue/] [trunk/] [blue8/] [rcvr.v] - Blame information for rev 4

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1 2 wd5gnr
/*
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    This file is part of Blue8.
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    Foobar is free software: you can redistribute it and/or modify
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    it under the terms of the GNU Lesser General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    Foobar is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU Lesser General Public License for more details.
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    You should have received a copy of the GNU Lesser General Public License
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    along with Blue8.  If not, see <http://www.gnu.org/licenses/>.
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    Blue8 by Al Williams alw@al-williams.com
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*/
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 `default_nettype none
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// async receiver -- Williams
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module rcvr (input wire clk,input wire clke,input wire rst,input wire rxd,
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  output [7:0] dout, output reg data_ready, input wire rdn,output reg framing_error, output reg overrun_error);
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//input clk;      // main clock coming in
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//input clke;   // 16x baud rate clock enable
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//input rst;      // reset
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//input rxd;   // serial input
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//output [7:0] dout;  // output bus
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//output data_ready;    // high when data is ready  
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//input rdn;          // put data on dout when high
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//output framing_error;  // high if frame error occurs
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//output overrun_error;  // detects overrun
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//reg overrun_error;
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reg rxd1;        // these two used to sync incoming data
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reg rxd2;
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reg clk1xe;   // clock enable for 1x clock
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reg clk1x_enable;     // generate the 1x receive clock (that is, character reception in progress)
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reg [3:0] clkdiv=0;  // divide 16x clock to 1x clock
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reg [7:0] rsr;            // shift register
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reg [7:0] rbr;            // buffer register
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reg [3:0] no_bits_rcvd;  // counter
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assign dout = (rdn & !rst) ? rbr : 8'bz;   // data bus output
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always @(posedge clk or posedge rst)     // synchronize incoming signal
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begin
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if (rst)
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begin
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  rxd1 <= 1'b1;
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  rxd2 <= 1'b1;
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end
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else
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if (clke)
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begin
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  rxd1 <= rxd;
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  rxd2 <= rxd1;
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end
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end
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always @(posedge clk or posedge rst)                            // go to 1x clock  until 9 (include stop) bits read
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begin
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if (rst)
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  clk1x_enable <= 1'b0;
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else if (clke)
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  begin
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    if (!rxd2 & !rxd1 & !rxd)                              // detect start bit
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       clk1x_enable <= 1'b1;                                                      // turn on clk1x
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    if (no_bits_rcvd == 4'b1010)                                  // or if done (no_bits_rcvd only increments during rcv)
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       clk1x_enable <= 1'b0;                                                      // turn off
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  end
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end
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always @(posedge clk or posedge rst)         // if rdn is 1 then clear data ready, set it when all bits read
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 begin                                                                                            // note, the dout assign "uses" rdn
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  if (rst)
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     data_ready = 1'b0;
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  else
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  begin
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    if (rdn) data_ready = 1'b0;
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    if (clke)
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           if (no_bits_rcvd == 4'b1010)
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        data_ready = 1'b1;
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  end
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end
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always @(posedge clk or posedge rst)        // generate 1x rate clock
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begin
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  if (rst)
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  begin
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    clkdiv <= 4'b0000;
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  end
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  else
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  begin
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    if (clke)
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           if (clk1x_enable)
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                begin
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            clkdiv<=clkdiv+1;
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      end
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           else
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                begin
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            clkdiv<=4'b1000;   // ensure correct delay after start bit
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      end
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  end
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end
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always @(posedge clk or posedge rst)            // generate 1x clock enable
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begin
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 if (rst) clk1xe=1'b0;
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 else
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   if (clke & clk1x_enable & clkdiv==4'b1111) clk1xe=1'b1; else clk1xe=1'b0;
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end
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always @(posedge clk or posedge rst)                      // depending on number of bits, take actions
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if (rst)
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begin
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  rsr = 8'b0;
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  rbr = 8'b0;
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  framing_error = 1'b0;
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  overrun_error = 1'b0;
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end
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else if (clk1xe)
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begin
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   if (no_bits_rcvd >= 4'b0000 && no_bits_rcvd <= 4'b1000)        // some # of bits until 8 bits
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   begin
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     rsr[6:0]=rsr[7:1];
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     rsr[7] = rxd2;         // shift bits in LSB first
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     if (no_bits_rcvd==4'b1000)
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            begin
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                   if (data_ready)
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                          overrun_error=1'b1;
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         else
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                          begin
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                          overrun_error=1'b0;
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                     rbr=rsr;     // copy shift register to data register
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           end
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       end
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                 if ((no_bits_rcvd == 4'b1000) && (rxd2 != 1'b1))                // check for framing error
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         framing_error = 1'b1;
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       else
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         framing_error = 1'b0;
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   end
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end
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always @(posedge clk or posedge rst)                     // count bits while 1x clock is running
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if (rst)
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  no_bits_rcvd = 4'b0000;
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else
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  begin
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  if (!clk1x_enable)                                                     // and reset count when 1x clock turns off
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    no_bits_rcvd = 4'b0000;
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  else
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     if (clk1xe) no_bits_rcvd = no_bits_rcvd + 1;
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 end
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endmodule
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