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[/] [blue/] [trunk/] [blue8/] [topbox.v] - Blame information for rev 4

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1 2 wd5gnr
/*
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    This file is part of Blue8.
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    Foobar is free software: you can redistribute it and/or modify
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    it under the terms of the GNU Lesser General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    Foobar is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU Lesser General Public License for more details.
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    You should have received a copy of the GNU Lesser General Public License
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    along with Blue8.  If not, see <http://www.gnu.org/licenses/>.
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    Blue8 by Al Williams alw@al-williams.com
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*/
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer:
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//
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// Create Date:    10:26:07 12/28/05
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// Design Name:    
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// Module Name:    topbox
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// Project Name:   
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// Target Device:  
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// Tool versions:  
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// Description:
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//
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// Dependencies:
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// 
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// 
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////////////////////////////////////////////////////////////////////////////////
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`default_nettype         none
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module topbox(input clkin, input pb0, input pb1, input pb2, input pb3, input [7:0] sw,
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output [7:0] led, output [6:0] display, output dp, output[3:0] digsel,
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                         output wire [17:0] xmaddress, inout wire [15:0] xmdata, output wire xmwrite,
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                                 output wire xmsend, output wire xmce, output wire xmub, output wire xmlb,
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                                 output wire serialout, input wire serialin);
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wire clk;
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wire clear, start, stop, lpc, exam, dep, xrun;
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wire [15:0] ir;
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wire [15:0] ac;
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wire [11:0] pc;
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wire [15:0] swreg;
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wire cpuwrite, cpusend;
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wire ser_avail;
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wire ser_tbe, ser_tse;
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wire ser_ferr, ser_oerr;
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wire [7:0] serialrx;
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wire Q;
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wire iomem;
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assign iomem=xmaddress[17:4]==14'h0FF;
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assign xmce=~((cpusend|cpuwrite)& ~iomem);  // enable on all reads and writes except those in I/O block
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assign xmub=1'b0;
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assign xmlb=1'b0;
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assign xmaddress[17:12]=6'b0;
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assign xmwrite=~cpuwrite;
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assign xmsend=~cpusend;
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// start RS232 loader
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reg loadlow;
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reg loadnow;
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reg [15:0] swregx;
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reg [3:0] loaddelay;
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always @(posedge clk or posedge clear)
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begin
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if (clear)
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  begin
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  loadlow<=1'b0;
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  loadnow<=1'b0;
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  loaddelay<=4'b0000;  // hold swregx long enough for load cycle
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  end
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else if (led[2] || led[4]) begin loadlow<=1'b0; loadnow<=1'b0; loaddelay<=4'b0000; end  // reset if not in load mode
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else if (led[3] & ~led[7])  // must be in load and not in running mode
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  begin
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        if (ser_avail & ~loadlow) begin swregx[15:8]<=serialrx; loadlow<=1; end
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                else if (ser_avail & loadlow) begin swregx[7:0]<=serialrx; loadlow<=1'b0; loadnow<=1'b1; end
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                else if (loadnow && loaddelay==4'b1000)
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                  begin
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                    loadnow<=1'b0;
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                         loaddelay<=4'b0000;
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        end else if (loadnow)
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                    loaddelay<=loaddelay+1;
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     end
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end
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// end loader
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wire loadsw;
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wire readuart, writeuart, readio, writeio;
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assign readio=cpusend & iomem;
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assign writeio=cpuwrite & iomem;
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assign readuart=readio & xmaddress[3:0]==4'hf;
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assign writeuart=writeio & xmaddress[3:0]==4'hf;
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assign loadsw=cpuwrite & (xmaddress[3:0]==4'h0) & iomem;
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assign xmdata=(readio & (xmaddress[3:0]==4'h0))? swreg : 16'bz;
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assign xmdata=(readio & (xmaddress[3:0]==4'h1))? { pb3, 7'h0, sw }:16'bz;
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// Note that a change in tactics means that pb3 is known as pb0 in the front panel!
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// pb2 is pb1 etc. (ought to change it).
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FrontPanel panel(clk, pb3, pb2, pb1, pb0, sw, led, display, dp, digsel,
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   clear, start, stop, lpc, exam, dep, xrun, swreg, ir, ac,  pc, Q, loadsw, xmdata);
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blue CPU(clear,clkin, ac, start,
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              stop,  exam,   dep|loadnow, pc,
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                                  loadnow?swregx:swreg, lpc, ir,xrun,xmaddress[11:0],xmdata,cpuwrite,cpusend,clk, Q);
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assign xmdata= (readuart) ? { ser_avail, 7'b0000000, serialrx  } : 16'bz;
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assign xmdata= (readio & (xmaddress[3:0]==4'he)) ? {  ser_tbe, ser_tse, ser_ferr, ser_oerr ,ser_avail, 11'b0 } : 16'bz;
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defparam serialport.BAUD=57600;
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defparam serialport.XTAL_CLK = 36000000;
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uart serialport (       clk, clear, serialin, serialout, xmdata[7:0],
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                                serialrx,ser_avail,readuart|(led[3]&~led[7]&ser_avail&~loadnow),ser_tbe,ser_tse,
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                                writeuart ,ser_ferr,ser_oerr);
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endmodule

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