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[/] [blue/] [trunk/] [blue8/] [txmit.v] - Blame information for rev 4

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1 2 wd5gnr
/*
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    This file is part of Blue8.
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    Foobar is free software: you can redistribute it and/or modify
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    it under the terms of the GNU Lesser General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    Foobar is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU Lesser General Public License for more details.
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    You should have received a copy of the GNU Lesser General Public License
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    along with Blue8.  If not, see <http://www.gnu.org/licenses/>.
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    Blue8 by Al Williams alw@al-williams.com
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*/
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// Async transmitter -- Williams
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`default_nettype none
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module txmit (input wire clk,input wire clke,input wire rst,output reg sdo,input wire [7:0] din,
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output reg tbre,output reg tsre,input write);
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//input clk;            // system clock
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//input clke;           // 16x baud rate clock enable
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//input rst;     // reset
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//output sdo;    // output data
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//output tbre;   // transmit buffer empty
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//output tsre;   // transmit shift reg. empty
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//input [7:0] din;      // data bus in
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//input write;  // load tbr
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reg clk1x_enable;  // 1x clock enable flag (character in progress)
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reg [7:0] tsr;     // shift register
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reg [7:0] tbr;            // buffer register
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reg[3:0] clkdiv;   // used to divide 16x clock to 1x clock
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reg [3:0] no_bits_sent;  // track # of bits sent
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reg clk1xe;        // 1x clock enable
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always @(posedge clk or posedge rst)      // manage data coming in from the system
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begin
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  if (rst)
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  begin
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    tbre<=1'b1;
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         clk1x_enable<=1'b0;
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         tbr=8'b0;
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  end
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  else
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  begin
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    if (clk1xe)
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         begin
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      if (no_bits_sent == 4'b0010) tbre<=1'b1;            // at count 2, tbr is empty again
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      else if (no_bits_sent==4'b1011)  clk1x_enable<=1'b0;    // done!
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    end
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  if (clke & no_bits_sent==4'b0000 & ~tbre) clk1x_enable<=1'b1;  // send buffered
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  if (write & tbre)  // if writing and buffer is empty, start process
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  begin
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    clk1x_enable<=1'b1;  // start right away, unless already 1 at which point nop               
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         tbre<=1'b0;
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         tbr=din;
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  end
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  end
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 end
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always @(posedge clk or posedge rst)             // generate 1x rate clock
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begin
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if (rst)
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  clkdiv = 4'b0;
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else if (clke && clk1x_enable)
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  clkdiv = clkdiv + 1;
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else if (~clk1x_enable) clkdiv=4'b0;
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end
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always @(posedge clk or posedge rst)            // generate 1x clock enable
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begin
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 if (rst) clk1xe=1'b0;
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 else
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   if (clke & clk1x_enable & clkdiv==4'b0111) clk1xe=1'b1; else clk1xe=1'b0;
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end
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always @(posedge clk or posedge rst)    // main state machine
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if (rst)
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begin
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sdo <= 1'b1;
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tsre <= 1'b1;
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tsr <= 9'b0;
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end
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  else if (clk1xe)
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  begin
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    if (no_bits_sent == 4'b0001)  // start, so load shift register
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    begin
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      tsr[7:0] <= tbr;
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                sdo<=1'b0;   // start bit
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      tsre <= 1'b0;
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    end
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    else if ((no_bits_sent >= 4'b0010) && (no_bits_sent <= 4'b1010))
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    begin
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      tsr[6:0] <= tsr[7:1];
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      tsr[7] <= 1'b1;       // shift in stop bits
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      sdo <= tsr[0];
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           if (no_bits_sent==4'b1010) tsre<=1'b1;       // last bit, shift reg empty just stop bit
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    end
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end
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always @(posedge clk or posedge rst)     // manage the # of bits sent
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begin
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  if (rst)
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    no_bits_sent = 4'b0000;
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  else if (clk1xe)
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    begin
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    if (no_bits_sent==4'b1011)
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      no_bits_sent = 4'b0000;
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    else
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      no_bits_sent = no_bits_sent + 1;
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    end
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end
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endmodule
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