OpenCores
URL https://opencores.org/ocsvn/bluespec-h264/bluespec-h264/trunk

Subversion Repositories bluespec-h264

[/] [bluespec-h264/] [trunk/] [src/] [mkMemED_bram.bsv] - Blame information for rev 100

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 83 jamey.hick
 
2
// The MIT License
3
 
4
// Copyright (c) 2006-2007 Massachusetts Institute of Technology
5
 
6
// Permission is hereby granted, free of charge, to any person obtaining a copy
7
// of this software and associated documentation files (the "Software"), to deal
8
// in the Software without restriction, including without limitation the rights
9
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
// copies of the Software, and to permit persons to whom the Software is
11
// furnished to do so, subject to the following conditions:
12
 
13
// The above copyright notice and this permission notice shall be included in
14
// all copies or substantial portions of the Software.
15
 
16
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
// THE SOFTWARE.
23
 
24 2 jamey.hick
//**********************************************************************
25 27 jamey.hick
// Memory for Entropy Decoder
26 2 jamey.hick
//----------------------------------------------------------------------
27
//
28
//
29
//
30
 
31
package mkMemED;
32
 
33
import H264Types::*;
34
import IMemED::*;
35
import GetPut::*;
36
import ClientServer::*;
37
import FIFO::*;
38
import BRAM::*;
39
 
40
 
41
//----------------------------------------------------------------------
42
// Main module
43
//----------------------------------------------------------------------
44
 
45
module mkMemED(IMemED#(index_size,data_size))
46
   provisos (Bits#(MemReq#(index_size,data_size),mReqLen),
47
             Bits#(MemResp#(data_size),mRespLen));
48
 
49
  //-----------------------------------------------------------
50
  // State
51
 
52
   BRAM#(Bit#(index_size),Bit#(data_size)) bramfile <- mkBRAM_Full();
53
 
54
   FIFO#(MemReq#(index_size,data_size)) reqQ  <- mkFIFO();
55
   FIFO#(MemResp#(data_size))  respQ <- mkFIFO();
56
 
57
   rule storing ( reqQ.first() matches tagged StoreReq { addr:.addrt,data:.datat} );
58
      bramfile.write(addrt,datat);
59
      reqQ.deq();
60
   endrule
61
 
62
   rule reading ( reqQ.first() matches tagged LoadReq .addrt );
63
      bramfile.read_req(addrt);
64
      reqQ.deq();
65
   endrule
66
 
67
   rule readresp ( True );
68
      let temp <- bramfile.read_resp;
69
      respQ.enq( LoadResp temp );
70
   endrule
71
 
72
   interface Server mem_server;
73
      interface Put request  = fifoToPut(reqQ);
74
      interface Get response = fifoToGet(respQ);
75
   endinterface
76
 
77
 
78
endmodule
79
 
80
endpackage

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.