OpenCores
URL https://opencores.org/ocsvn/bluespec-h264/bluespec-h264/trunk

Subversion Repositories bluespec-h264

[/] [bluespec-h264/] [trunk/] [src_fpga/] [BRAM.bsv] - Blame information for rev 100

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 83 jamey.hick
 
2
// The MIT License
3
 
4
// Copyright (c) 2006-2007 Massachusetts Institute of Technology
5
 
6
// Permission is hereby granted, free of charge, to any person obtaining a copy
7
// of this software and associated documentation files (the "Software"), to deal
8
// in the Software without restriction, including without limitation the rights
9
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
// copies of the Software, and to permit persons to whom the Software is
11
// furnished to do so, subject to the following conditions:
12
 
13
// The above copyright notice and this permission notice shall be included in
14
// all copies or substantial portions of the Software.
15
 
16
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
// THE SOFTWARE.
23
 
24 3 jamey.hick
import FIFO::*;
25
 
26
//One RAM.
27
interface BRAM#(type idx_type, type data_type);
28
 
29
  method Action read_req(idx_type idx);
30
 
31
  method ActionValue#(data_type) read_resp();
32
 
33
  method Action write(idx_type idx, data_type data);
34
 
35
endinterface
36
 
37
 
38
//Two RAMs.
39
interface BRAM_2#(type idx_type, type data_type);
40
 
41
  method Action read_req1(idx_type idx);
42
  method Action read_req2(idx_type idx);
43
 
44
  method ActionValue#(data_type) read_resp1();
45
  method ActionValue#(data_type) read_resp2();
46
 
47
  method Action write(idx_type idx, data_type data);
48
 
49
endinterface
50
 
51
//Three RAMs.
52
interface BRAM_3#(type idx_type, type data_type);
53
 
54
  method Action read_req1(idx_type idx);
55
  method Action read_req2(idx_type idx);
56
  method Action read_req3(idx_type idx);
57
 
58
  method ActionValue#(data_type) read_resp1();
59
  method ActionValue#(data_type) read_resp2();
60
  method ActionValue#(data_type) read_resp3();
61
 
62
  method Action write(idx_type idx, data_type data);
63
 
64
endinterface
65
 
66
 
67
module mkBRAM#(Integer low, Integer high)
68
  //interface:
69
              (BRAM#(idx_type, data_type))
70
  provisos
71
          (Bits#(idx_type, idx),
72
           Bits#(data_type, data),
73
           Literal#(idx_type));
74
 
75
  BRAM#(idx_type, data_type) m <- (valueof(data) == 0) ?
76
                                  mkBRAM_Zero() :
77
                                  mkBRAM_NonZero(low, high);
78
 
79
  return m;
80
endmodule
81
 
82
import "BVI" BRAM = module mkBRAM_NonZero#(Integer low, Integer high)
83
  //interface:
84
              (BRAM#(idx_type, data_type))
85
  provisos
86
          (Bits#(idx_type, idx),
87
           Bits#(data_type, data),
88
           Literal#(idx_type));
89
 
90
  default_clock clk(CLK);
91
 
92
  parameter addr_width = valueof(idx);
93
  parameter data_width = valueof(data);
94
  parameter lo = low;
95
  parameter hi = high;
96
 
97
  method DOUT read_resp() ready(DOUT_RDY) enable(DOUT_EN);
98
 
99
  method read_req(RD_ADDR) ready(RD_RDY) enable(RD_EN);
100
  method write(WR_ADDR, WR_VAL) enable(WR_EN);
101
 
102
  schedule read_req  CF (read_resp, write);
103
  schedule read_resp CF (read_req, write);
104
  schedule write     CF (read_req, read_resp);
105
 
106
  schedule read_req  C read_req;
107
  schedule read_resp C read_resp;
108
  schedule write     C write;
109
 
110
endmodule
111
 
112
module mkBRAM_Zero
113
  //interface:
114
              (BRAM#(idx_type, data_type))
115
  provisos
116
          (Bits#(idx_type, idx),
117
           Bits#(data_type, data),
118
           Literal#(idx_type));
119
 
120
  FIFO#(data_type) q <- mkFIFO();
121
 
122
  method Action read_req(idx_type i);
123
     q.enq(?);
124
  endmethod
125
 
126
  method Action write(idx_type i, data_type d);
127
    noAction;
128
  endmethod
129
 
130
  method ActionValue#(data_type) read_resp();
131
    q.deq();
132
    return q.first();
133
  endmethod
134
 
135
endmodule
136
 
137
module mkBRAM_Full
138
  //interface:
139
              (BRAM#(idx_type, data_type))
140
  provisos
141
          (Bits#(idx_type, idx),
142
           Bits#(data_type, data),
143
           Literal#(idx_type));
144
 
145
 
146
  BRAM#(idx_type, data_type) br <- mkBRAM(0, valueof(TExp#(idx)) - 1);
147
 
148
  return br;
149
 
150
endmodule
151
module mkBRAM_2#(Integer low, Integer high)
152
  //interface:
153
              (BRAM_2#(idx_type, data_type))
154
  provisos
155
          (Bits#(idx_type, idx),
156
           Bits#(data_type, data),
157
           Literal#(idx_type));
158
 
159
  BRAM#(idx_type, data_type) br1 <- mkBRAM(low, high);
160
  BRAM#(idx_type, data_type) br2 <- mkBRAM(low, high);
161
 
162
  method read_req1(idx) = br1.read_req(idx);
163
  method read_req2(idx) = br2.read_req(idx);
164
 
165
  method read_resp1() = br1.read_resp();
166
  method read_resp2() = br2.read_resp();
167
 
168
  method Action write(idx_type idx, data_type data);
169
 
170
    br1.write(idx, data);
171
    br2.write(idx, data);
172
 
173
  endmethod
174
 
175
endmodule
176
 
177
module mkBRAM_2_Full
178
  //interface:
179
              (BRAM_2#(idx_type, data_type))
180
  provisos
181
          (Bits#(idx_type, idx),
182
           Bits#(data_type, data),
183
           Literal#(idx_type));
184
 
185
 
186
  BRAM_2#(idx_type, data_type) br <- mkBRAM_2(0, valueof(TExp#(idx)) - 1);
187
 
188
  return br;
189
 
190
endmodule
191
 
192
module mkBRAM_3#(Integer low, Integer high)
193
  //interface:
194
              (BRAM_3#(idx_type, data_type))
195
  provisos
196
          (Bits#(idx_type, idx),
197
           Bits#(data_type, data),
198
           Literal#(idx_type));
199
 
200
  BRAM#(idx_type, data_type) br1 <- mkBRAM(low, high);
201
  BRAM#(idx_type, data_type) br2 <- mkBRAM(low, high);
202
  BRAM#(idx_type, data_type) br3 <- mkBRAM(low, high);
203
 
204
  method read_req1(idx) = br1.read_req(idx);
205
  method read_req2(idx) = br2.read_req(idx);
206
  method read_req3(idx) = br3.read_req(idx);
207
 
208
  method read_resp1() = br1.read_resp();
209
  method read_resp2() = br2.read_resp();
210
  method read_resp3() = br3.read_resp();
211
 
212
  method Action write(idx_type idx, data_type data);
213
 
214
    br1.write(idx, data);
215
    br2.write(idx, data);
216
    br3.write(idx, data);
217
 
218
  endmethod
219
 
220
endmodule
221
 
222
 
223
module mkBRAM_3_Full
224
  //interface:
225
              (BRAM_3#(idx_type, data_type))
226
  provisos
227
          (Bits#(idx_type, idx),
228
           Bits#(data_type, data),
229
           Literal#(idx_type));
230
 
231
 
232
  BRAM_3#(idx_type, data_type) br <- mkBRAM_3(0, valueof(TExp#(idx)) - 1);
233
 
234
  return br;
235
 
236
endmodule
237
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.