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Subversion Repositories bluespec-h264

[/] [bluespec-h264/] [trunk/] [src_fpga/] [BlueSRAM.bsv] - Blame information for rev 100

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// The MIT License
 
// Copyright (c) 2006-2007 Massachusetts Institute of Technology
 
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
 
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
 
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
 
import FIFO::*;
import mkSatCounter::*;
import RegFile::*;
 
interface BlueSRAM#(type idx_type, type data_type);
 
  method Action read_req(idx_type idx);
 
  method ActionValue#(data_type) read_resp();
 
  method Action write(idx_type idx, data_type data);
 
 
  method Bit#(18) address_out();
  method Bit#(32) data_out();
  method Action data_in(Bit#(32) data);
  method Bit#(1) data_tri();
  method Bit#(4) we_bytes_out();
  method Bit#(1) we_out();
  method Bit#(1) ce_out();
  method Bit#(1) oe_out();
  method Bit#(1) cen_out();
  method Bit#(1) adv_ld_out();
endinterface
 
 
 
 
module mkBlueSRAM#(Integer low, Integer high)
  //interface:
              (BlueSRAM#(idx_type, data_type))
  provisos
          (Bits#(idx_type, idx),
           Bitwise#(idx_type),
           Add#(idx, xxx, 18),
           Add#(data, yyy, 32),
           Bits#(data_type, data),
           Bitwise#(data_type),
           Literal#(data_type),
           Literal#(idx_type),
           Bounded#(idx_type),
           Eq#(data_type));
 
  BlueSRAM#(idx_type, data_type) m <- (valueof(data) == 0) ?
                                   mkBlueSRAM_Zero() :
                                   mkBlueSRAM_NonZero(low, high);
 
  return m;
endmodule
 
 
typedef enum {
  READ_REQ,
  WRITE_REQ,
  NOP
}
  RequestType
    deriving(Bits, Eq);
 
 
module mkBlueSRAM_NonZero#(Integer low, Integer high)
  //interface:
              (BlueSRAM#(idx_type, data_type))
  provisos
          (Bits#(idx_type, idx),
           Add#(idx, xxx, 18),
           Add#(data, yyy, 32),
           Bitwise#(idx_type),
           Bits#(data_type, data),
           Bitwise#(data_type),
           Literal#(data_type),
           Literal#(idx_type),
           Bounded#(idx_type),
           Eq#(data_type));
  FIFO#(data_type) output_fifo <- mkLFIFO();
  SatCounter#(2) counter <- mkSatCounter(2);
  RWire#(RequestType) req_type_wire <- mkRWire();
  RWire#(idx_type)    idx_type_wire <- mkRWire();
  RWire#(data_type)   data_type_wire <- mkRWire();
  RWire#(Bit#(0))     read_req_called <- mkRWire();
  RWire#(Bit#(0))     read_resp_called <- mkRWire();
  Reg#(RequestType)   op_command_pipelined <- mkReg(NOP);
  Reg#(RequestType)   op_command_active <- mkReg(NOP);
  Reg#(data_type)     write_data_pipelined <- mkReg(0);
  Reg#(data_type)     write_data_active <- mkReg(0);
 
  rule process_req;
    op_command_active <= op_command_pipelined;
    write_data_active <= write_data_pipelined;
    if(req_type_wire.wget matches tagged Valid .req)
      begin
        if(idx_type_wire.wget matches tagged Valid .idx)
          begin
            if(data_type_wire.wget matches tagged Valid .val)
              begin
                op_command_pipelined <= req;
                write_data_pipelined <= val;
              end
            else
              begin
                op_command_pipelined <= req;
              end
          end
      end
    else
      begin
        // If we had neither request, we should insert a NOP.
        op_command_pipelined <= NOP;
      end
  endrule
 
  rule adjust_counter;
    if(read_resp_called.wget matches tagged Valid .x)
      begin
        if(read_req_called.wget matches tagged Invalid)
          begin
            counter.up();
          end
      end
    else
      begin
        if(read_req_called.wget matches tagged Valid .y)
          begin
            counter.down();
          end
      end
  endrule
 
 
  method ActionValue#(data_type) read_resp();
    $display("MemClient BlueSRAM: dequeueing: %h", output_fifo.first());
    read_resp_called.wset(0);
    output_fifo.deq();
    return output_fifo.first();
  endmethod
 
  method Action read_req(idx_type idx) if (isValid(read_resp_called.wget) || (counter.value > 0));
    $display("MemClient BlueSRAM: ReadReq idx: %h", idx);
    read_req_called.wset(0);
    req_type_wire.wset(READ_REQ);
    idx_type_wire.wset(idx);
  endmethod
 
  method Action write(idx_type idx, data_type data);
    $display("MemClient BlueSRAM: Write idx: %h data:%h", idx, data);
    req_type_wire.wset(WRITE_REQ);
    idx_type_wire.wset(idx);
    data_type_wire.wset(data);
  endmethod
 
  // All of these are physical wires and therefore always enabled/ready
  method Bit#(18) address_out();
    if(idx_type_wire.wget matches tagged Valid .idx)
      begin
        Bit#(18) out_addr = 0;
        out_addr = zeroExtend(pack(idx));
        return out_addr;
      end
    else
      begin
        return 0;
      end
  endmethod
 
  method Bit#(32) data_out();
    Bit#(32) data = zeroExtend(pack(write_data_active));
    return data;
  endmethod
 
  method Action data_in(Bit#(32) data);
    if(op_command_active == READ_REQ)
      begin
        data_type internal_data = unpack(truncate(data));
        output_fifo.enq(internal_data);
      end
  endmethod
 
  method data_tri();
    if(op_command_active != WRITE_REQ)
      begin
        return ~0;
      end
    else
      begin
        return 0;
      end
  endmethod
 
  method we_bytes_out();
    if(req_type_wire.wget matches tagged Valid .req)
      begin
        if(req != WRITE_REQ)
          begin
            return ~0;
          end
        else
          begin
            return 0;
          end
      end
    else
      begin
        return ~0;
      end
  endmethod
 
  method we_out();
    if(req_type_wire.wget matches tagged Valid .req)
      begin
        if(req != WRITE_REQ)
          begin
            return ~0;
          end
        else
          begin
            return 0;
          end
      end
    else
      begin
        return ~0;
      end
  endmethod
 
  method ce_out();
    return 0;
  endmethod
 
  method oe_out();
    return 0;
  endmethod
 
  method cen_out();
    return 0;
  endmethod
 
  method adv_ld_out();
    return 0;
  endmethod
 
endmodule
 
module mkBlueSRAM_Zero
  //interface:
              (BlueSRAM#(idx_type, data_type))
    provisos
          (Bits#(idx_type, idx),
           Bitwise#(idx_type),
           Bits#(data_type, data),
           Bitwise#(data_type),
           Literal#(data_type),
           Literal#(idx_type));
 
  FIFO#(data_type) q <- mkSizedFIFO(4);
 
  method Action read_req(idx_type i);
     q.enq(?);
  endmethod
 
  method Action write(idx_type i, data_type d);
    noAction;
  endmethod
 
  method ActionValue#(data_type) read_resp();
    q.deq();
    return q.first();
  endmethod
 
  method Bit#(18) address_out();
    return ~0;
  endmethod
 
  method Bit#(32) data_out();
    return ~0;
  endmethod
 
  method Action data_in(Bit#(32) data);
    noAction;
  endmethod
 
  method Bit#(1) data_tri();
    return ~0;
  endmethod
 
  method Bit#(4) we_bytes_out();
    return ~0;
  endmethod
 
  method Bit#(1) we_out();
    return ~0;
  endmethod
 
  method Bit#(1) ce_out();
    return ~0;
  endmethod
 
  method Bit#(1) oe_out();
    return ~0;
  endmethod
 
  method Bit#(1) cen_out();
    return ~0;
  endmethod
 
  method Bit#(1) adv_ld_out();
    return ~0;
  endmethod
endmodule
 
 
module mkBlueSRAM_Full
  //interface:
              (BlueSRAM#(idx_type, data_type))
  provisos
          (Bits#(idx_type, idx),
           Bitwise#(idx_type),
           Bits#(data_type, data),
           Add#(idx, xxx, 18),
           Add#(data, yyy, 32),
           Bitwise#(data_type),
           Literal#(data_type),
           Literal#(idx_type),
           Bounded#(idx_type),
           Eq#(data_type));
 
  BlueSRAM#(idx_type, data_type) br <- mkBlueSRAM(0, valueof(TExp#(idx)) - 1);
 
  return br;
 
endmodule
 

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Subversion Repositories bluespec-h264

[/] [bluespec-h264/] [trunk/] [src_fpga/] [BlueSRAM.bsv] - Blame information for rev 100

Line No.	Rev	Author	Line
1	83	jamey.hick
2			`// The MIT License`
3
4			`// Copyright (c) 2006-2007 Massachusetts Institute of Technology`
5
6			`// Permission is hereby granted, free of charge, to any person obtaining a copy`
7			`// of this software and associated documentation files (the "Software"), to deal`
8			`// in the Software without restriction, including without limitation the rights`
9			`// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell`
10			`// copies of the Software, and to permit persons to whom the Software is`
11			`// furnished to do so, subject to the following conditions:`
12
13			`// The above copyright notice and this permission notice shall be included in`
14			`// all copies or substantial portions of the Software.`
15
16			`// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
17			`// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
18			`// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
19			`// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
20			`// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
21			`// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN`
22			`// THE SOFTWARE.`
23
24	3	jamey.hick	`import FIFO::*;`
25			`import mkSatCounter::*;`
26			`import RegFile::*;`
27
28			`interface BlueSRAM#(type idx_type, type data_type);`
29
30			`method Action read_req(idx_type idx);`
31
32			`method ActionValue#(data_type) read_resp();`
33
34			`method Action write(idx_type idx, data_type data);`
35
36
37			`method Bit#(18) address_out();`
38			`method Bit#(32) data_out();`
39			`method Action data_in(Bit#(32) data);`
40			`method Bit#(1) data_tri();`
41			`method Bit#(4) we_bytes_out();`
42			`method Bit#(1) we_out();`
43			`method Bit#(1) ce_out();`
44			`method Bit#(1) oe_out();`
45			`method Bit#(1) cen_out();`
46			`method Bit#(1) adv_ld_out();`
47			`endinterface`
48
49
50
51
52			`module mkBlueSRAM#(Integer low, Integer high)`
53			`//interface:`
54			`(BlueSRAM#(idx_type, data_type))`
55			`provisos`
56			`(Bits#(idx_type, idx),`
57			`Bitwise#(idx_type),`
58			`Add#(idx, xxx, 18),`
59			`Add#(data, yyy, 32),`
60			`Bits#(data_type, data),`
61			`Bitwise#(data_type),`
62			`Literal#(data_type),`
63			`Literal#(idx_type),`
64			`Bounded#(idx_type),`
65			`Eq#(data_type));`
66
67			`BlueSRAM#(idx_type, data_type) m <- (valueof(data) == 0) ?`
68			`mkBlueSRAM_Zero() :`
69			`mkBlueSRAM_NonZero(low, high);`
70
71			`return m;`
72			`endmodule`
73
74
75			`typedef enum {`
76			`READ_REQ,`
77			`WRITE_REQ,`
78			`NOP`
79			`}`
80			`RequestType`
81			`deriving(Bits, Eq);`
82
83
84			`module mkBlueSRAM_NonZero#(Integer low, Integer high)`
85			`//interface:`
86			`(BlueSRAM#(idx_type, data_type))`
87			`provisos`
88			`(Bits#(idx_type, idx),`
89			`Add#(idx, xxx, 18),`
90			`Add#(data, yyy, 32),`
91			`Bitwise#(idx_type),`
92			`Bits#(data_type, data),`
93			`Bitwise#(data_type),`
94			`Literal#(data_type),`
95			`Literal#(idx_type),`
96			`Bounded#(idx_type),`
97			`Eq#(data_type));`
98			`FIFO#(data_type) output_fifo <- mkLFIFO();`
99			`SatCounter#(2) counter <- mkSatCounter(2);`
100			`RWire#(RequestType) req_type_wire <- mkRWire();`
101			`RWire#(idx_type) idx_type_wire <- mkRWire();`
102			`RWire#(data_type) data_type_wire <- mkRWire();`
103			`RWire#(Bit#(0)) read_req_called <- mkRWire();`
104			`RWire#(Bit#(0)) read_resp_called <- mkRWire();`
105			`Reg#(RequestType) op_command_pipelined <- mkReg(NOP);`
106			`Reg#(RequestType) op_command_active <- mkReg(NOP);`
107			`Reg#(data_type) write_data_pipelined <- mkReg(0);`
108			`Reg#(data_type) write_data_active <- mkReg(0);`
109
110			`rule process_req;`
111			`op_command_active <= op_command_pipelined;`
112			`write_data_active <= write_data_pipelined;`
113			`if(req_type_wire.wget matches tagged Valid .req)`
114			`begin`
115			`if(idx_type_wire.wget matches tagged Valid .idx)`
116			`begin`
117			`if(data_type_wire.wget matches tagged Valid .val)`
118			`begin`
119			`op_command_pipelined <= req;`
120			`write_data_pipelined <= val;`
121			`end`
122			`else`
123			`begin`
124			`op_command_pipelined <= req;`
125			`end`
126			`end`
127			`end`
128			`else`
129			`begin`
130			`// If we had neither request, we should insert a NOP.`
131			`op_command_pipelined <= NOP;`
132			`end`
133			`endrule`
134
135			`rule adjust_counter;`
136			`if(read_resp_called.wget matches tagged Valid .x)`
137			`begin`
138			`if(read_req_called.wget matches tagged Invalid)`
139			`begin`
140			`counter.up();`
141			`end`
142			`end`
143			`else`
144			`begin`
145			`if(read_req_called.wget matches tagged Valid .y)`
146			`begin`
147			`counter.down();`
148			`end`
149			`end`
150			`endrule`
151
152
153			`method ActionValue#(data_type) read_resp();`
154			`$display("MemClient BlueSRAM: dequeueing: %h", output_fifo.first());`
155			`read_resp_called.wset(0);`
156			`output_fifo.deq();`
157			`return output_fifo.first();`
158			`endmethod`
159
160			`method Action read_req(idx_type idx) if (isValid(read_resp_called.wget) \|\| (counter.value > 0));`
161			`$display("MemClient BlueSRAM: ReadReq idx: %h", idx);`
162			`read_req_called.wset(0);`
163			`req_type_wire.wset(READ_REQ);`
164			`idx_type_wire.wset(idx);`
165			`endmethod`
166
167			`method Action write(idx_type idx, data_type data);`
168			`$display("MemClient BlueSRAM: Write idx: %h data:%h", idx, data);`
169			`req_type_wire.wset(WRITE_REQ);`
170			`idx_type_wire.wset(idx);`
171			`data_type_wire.wset(data);`
172			`endmethod`
173
174			`// All of these are physical wires and therefore always enabled/ready`
175			`method Bit#(18) address_out();`
176			`if(idx_type_wire.wget matches tagged Valid .idx)`
177			`begin`
178			`Bit#(18) out_addr = 0;`
179			`out_addr = zeroExtend(pack(idx));`
180			`return out_addr;`
181			`end`
182			`else`
183			`begin`
184			`return 0;`
185			`end`
186			`endmethod`
187
188			`method Bit#(32) data_out();`
189			`Bit#(32) data = zeroExtend(pack(write_data_active));`
190			`return data;`
191			`endmethod`
192
193			`method Action data_in(Bit#(32) data);`
194			`if(op_command_active == READ_REQ)`
195			`begin`
196			`data_type internal_data = unpack(truncate(data));`
197			`output_fifo.enq(internal_data);`
198			`end`
199			`endmethod`
200
201			`method data_tri();`
202			`if(op_command_active != WRITE_REQ)`
203			`begin`
204			`return ~0;`
205			`end`
206			`else`
207			`begin`
208			`return 0;`
209			`end`
210			`endmethod`
211
212			`method we_bytes_out();`
213			`if(req_type_wire.wget matches tagged Valid .req)`
214			`begin`
215			`if(req != WRITE_REQ)`
216			`begin`
217			`return ~0;`
218			`end`
219			`else`
220			`begin`
221			`return 0;`
222			`end`
223			`end`
224			`else`
225			`begin`
226			`return ~0;`
227			`end`
228			`endmethod`
229
230			`method we_out();`
231			`if(req_type_wire.wget matches tagged Valid .req)`
232			`begin`
233			`if(req != WRITE_REQ)`
234			`begin`
235			`return ~0;`
236			`end`
237			`else`
238			`begin`
239			`return 0;`
240			`end`
241			`end`
242			`else`
243			`begin`
244			`return ~0;`
245			`end`
246			`endmethod`
247
248			`method ce_out();`
249			`return 0;`
250			`endmethod`
251
252			`method oe_out();`
253			`return 0;`
254			`endmethod`
255
256			`method cen_out();`
257			`return 0;`
258			`endmethod`
259
260			`method adv_ld_out();`
261			`return 0;`
262			`endmethod`
263
264			`endmodule`
265
266			`module mkBlueSRAM_Zero`
267			`//interface:`
268			`(BlueSRAM#(idx_type, data_type))`
269			`provisos`
270			`(Bits#(idx_type, idx),`
271			`Bitwise#(idx_type),`
272			`Bits#(data_type, data),`
273			`Bitwise#(data_type),`
274			`Literal#(data_type),`
275			`Literal#(idx_type));`
276
277			`FIFO#(data_type) q <- mkSizedFIFO(4);`
278
279			`method Action read_req(idx_type i);`
280			`q.enq(?);`
281			`endmethod`
282
283			`method Action write(idx_type i, data_type d);`
284			`noAction;`
285			`endmethod`
286
287			`method ActionValue#(data_type) read_resp();`
288			`q.deq();`
289			`return q.first();`
290			`endmethod`
291
292			`method Bit#(18) address_out();`
293			`return ~0;`
294			`endmethod`
295
296			`method Bit#(32) data_out();`
297			`return ~0;`
298			`endmethod`
299
300			`method Action data_in(Bit#(32) data);`
301			`noAction;`
302			`endmethod`
303
304			`method Bit#(1) data_tri();`
305			`return ~0;`
306			`endmethod`
307
308			`method Bit#(4) we_bytes_out();`
309			`return ~0;`
310			`endmethod`
311
312			`method Bit#(1) we_out();`
313			`return ~0;`
314			`endmethod`
315
316			`method Bit#(1) ce_out();`
317			`return ~0;`
318			`endmethod`
319
320			`method Bit#(1) oe_out();`
321			`return ~0;`
322			`endmethod`
323
324			`method Bit#(1) cen_out();`
325			`return ~0;`
326			`endmethod`
327
328			`method Bit#(1) adv_ld_out();`
329			`return ~0;`
330			`endmethod`
331			`endmodule`
332
333
334			`module mkBlueSRAM_Full`
335			`//interface:`
336			`(BlueSRAM#(idx_type, data_type))`
337			`provisos`
338			`(Bits#(idx_type, idx),`
339			`Bitwise#(idx_type),`
340			`Bits#(data_type, data),`
341			`Add#(idx, xxx, 18),`
342			`Add#(data, yyy, 32),`
343			`Bitwise#(data_type),`
344			`Literal#(data_type),`
345			`Literal#(idx_type),`
346			`Bounded#(idx_type),`
347			`Eq#(data_type));`
348
349			`BlueSRAM#(idx_type, data_type) br <- mkBlueSRAM(0, valueof(TExp#(idx)) - 1);`
350
351			`return br;`
352
353			`endmodule`
354