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[/] [bluespec-h264/] [trunk/] [src_fpga/] [SRAMEmulator.bsv] - Blame information for rev 100

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1 83 jamey.hick
 
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// The MIT License
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// Copyright (c) 2006-2007 Massachusetts Institute of Technology
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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24 3 jamey.hick
import RegFile::*;
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import ISRAMWires::*;
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interface ISRAMEmulator;
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endinterface
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module mkSRAMEmulator#(ISRAMWires wires) (ISRAMEmulator);
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  RegFile#(Bit#(18), Bit#(32))  arr <- mkRegFileFull();
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  Reg#(Bit#(18)) addr_p <- mkReg(0);
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  Reg#(Bit#(18)) addr_pp <- mkReg(0);
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  Reg#(Bit#(1))  we_p <- mkReg(0);
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  Reg#(Bit#(1))  we_pp <- mkReg(0);
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  rule tick;
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    Bit#(18) addr_pt = wires.address_out();
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    Bit#(32) data_Ot = wires.data_O();
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    wires.data_I(arr.sub(addr_pp));
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    addr_p <= addr_pt;
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    addr_pp <= addr_p;
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    we_p <= wires.we_out();
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    we_pp <= we_p;
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    if(we_pp == 1)
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      begin
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        //$display("MemClient SRAM Emulator: index %h reading %h", addr_pp, arr.sub(addr_pp));
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      end
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    else
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      begin
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        //$display("MemClient SRAM Emulator: index %h writing %h", addr_pp, data_Ot);
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        arr.upd(addr_pp, data_Ot);
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      end
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  endrule
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endmodule
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