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jamey.hick |
#=======================================================================
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# 6.375 Makefile for bsc-compile
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#-----------------------------------------------------------------------
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jamey.hick |
# $Id: Makefile,v 1.3 2008-06-26 17:52:59 jamey.hicks Exp $
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jamey.hick |
#
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default : all
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basedir = ../
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#--------------------------------------------------------------------
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# Sources
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#--------------------------------------------------------------------
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# Library components
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bsvclibdir = $(MIT6375_HOME)/install/bsvclib
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bsvclibsrcs = \
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# Bluespec sources
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toplevel_module = mkTestBench
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srcdir = $(basedir)
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srcmem = ../../../MemController
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bsvsrcs = \
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$(srcdir)/BRAM.bsv \
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$(srcdir)/H264Types.bsv \
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$(srcdir)/ExpGolomb.bsv \
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$(srcdir)/CAVLC.bsv \
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$(srcdir)/IH264.bsv \
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$(srcdir)/IInputGen.bsv \
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$(srcdir)/INalUnwrap.bsv \
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$(srcdir)/IEntropyDec.bsv \
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$(srcdir)/ICalc_nC.bsv \
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$(srcdir)/IMemED.bsv \
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$(srcdir)/IFPGAInterface.bsv \
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$(srcdir)/IEDKBRAM.bsv \
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$(srcdir)/IVgaController.bsv \
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$(srcdir)/IInverseTrans.bsv \
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$(srcdir)/IPrediction.bsv \
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$(srcdir)/IDeblockFilter.bsv \
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$(srcdir)/IBufferControl.bsv \
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$(srcdir)/IFinalOutput.bsv \
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$(srcdir)/mkH264.bsv \
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$(srcdir)/mkInputGen.bsv \
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$(srcdir)/mkNalUnwrap.bsv \
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$(srcdir)/mkEntropyDec.bsv \
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$(srcdir)/mkCalc_nC.bsv \
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$(srcdir)/mkMemED.bsv \
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$(srcdir)/mkInverseTrans.bsv \
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$(srcdir)/mkPrediction.bsv \
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$(srcdir)/mkDeblockFilter.bsv \
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$(srcdir)/mkBufferControl.bsv \
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$(srcdir)/mkFinalOutput.bsv \
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$(srcdir)/mkTH.bsv \
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$(srcdir)/mkTestBench.bsv \
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$(srcdir)/mkVgaController.bsv \
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$(srcdir)/MemControllerTypes.bsv \
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$(srcdir)/IMemClient.bsv \
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$(srcdir)/IMemClientBackend.bsv \
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$(srcdir)/IMemController.bsv \
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$(srcdir)/IMemScheduler.bsv \
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$(srcdir)/mkMemClient.bsv \
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$(srcdir)/mkBRAMMemController.bsv \
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$(srcdir)/mkRoundRobinMemScheduler.bsv \
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$(srcdir)/mkPriorityRoundRobinMemScheduler.bsv \
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$(srcdir)/BRAM.bsv \
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$(srcdir)/FIFO_2.bsv \
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$(srcdir)/mkSatCounter.bsv \
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$(srcdir)/SRAM.bsv \
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$(srcdir)/mkSRAMMemController.bsv \
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$(srcdir)/ISRAMWires.bsv \
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$(srcdir)/IInterpolator.bsv \
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$(srcdir)/mkInterpolator.bsv \
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$(srcdir)/mkFrameBuffer.bsv \
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$(srcdir)/IFrameBuffer.bsv \
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$(srcdir)/BlueBRAM.bsv \
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$(srcdir)/SRAMEmulator.bsv \
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$(srcdir)/BlueSRAM.bsv \
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$(srcdir)/IFPGA_FIFO.bsv \
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$(srcdir)/mkSizedFIFO_fpga.bsv \
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#--------------------------------------------------------------------
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# Build rules
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#--------------------------------------------------------------------
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BSC_COMP = bsc
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#BSC_OPTS = -u -show-module-use - -keep-fires -aggressive-conditions \
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# -relax-method-earliness -relax-method-urgency -v
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7 |
jamey.hick |
BSC_OPTS = +RTS -K40000k --RTS -u -v -verilog -aggressive-conditions
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4 |
jamey.hick |
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# Copy over the bluespec source
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$(notdir $(bsvsrcs)) : % : $(srcdir)/%
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cp $< .
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$(notdir $(bsvclibsrcs)) : % : $(bsvclibdir)/%
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cp $< .
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# Run the bluespec compiler
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bsv_TH_vsrc = $(toplevel_module).v
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$(bsv_TH_vsrc) $(bsv_lib_use) : $(notdir $(bsvsrcs) $(bsvclibsrcs))
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$(BSC_COMP) $(BSC_OPTS) -g $(toplevel_module) $(toplevel_module).bsv > out.log
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compile : $(toplevel_module).v
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# Create a schedule file
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schedule_rpt = schedule.rpt
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$(schedule_rpt) : $(notdir $(bsvsrcs) $(bsvclibsrcs))
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rm -rf *.v
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$(BSC_COMP) $(BSC_OPTS) -show-schedule -show-rule-rel \* \* -g $(toplevel_module) \
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$(toplevel_module).bsv >& $(schedule_rpt)
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junk += $(notdir $(bsvsrcs)) $(notdir $(bsvclibsrcs)) \
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$(schedule_rpt) *.use *.bi *.bo *.v bsc.log
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#--------------------------------------------------------------------
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# Default make target
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#--------------------------------------------------------------------
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all : compile
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#--------------------------------------------------------------------
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# Clean up
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#--------------------------------------------------------------------
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clean :
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rm -rf $(junk) *~ \#*
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