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[/] [bluespec-h264/] [trunk/] [src_fpga/] [mkTestBench.bsv] - Blame information for rev 3

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Line No. Rev Author Line
1 3 jamey.hick
 
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//**********************************************************************
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// Top level test-bench.  Mimics BRAM interface.
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//----------------------------------------------------------------------
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//
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//
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package mkTestBench;
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import RegFile::*;
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import IFPGAInterface::*;
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import IEDKBRAM::*;
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import mkTH::*;
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import ISRAMWires::*;
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import SRAMEmulator::*;
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`define INPUT_SIZE 5298616
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interface DoubleSRAM;
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  interface ISRAMWires sram_controller1;
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  interface ISRAMWires sram_controller2;
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endinterface
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module mkTestBench();
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  IFPGAInterface h264 <- mkth();
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  ISRAMEmulator sram1 <- mkSRAMEmulator(h264.sram_controller);
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  ISRAMEmulator sram2 <- mkSRAMEmulator(h264.sram_controller2);
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  RegFile#(Bit#(32), Bit#(8)) rfile <- mkRegFileLoad("./ww2.8.hex", 0, `INPUT_SIZE-1);
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  Reg#(Bit#(32))  data_remaining <- mkReg(`INPUT_SIZE);
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  Reg#(Bit#(32))  base_offset   <- mkReg(0);
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  Reg#(Bit#(32))  index <- mkReg(0);
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  rule read (h264.bram_controller.wen_output() == 0);
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    index <= h264.bram_controller.addr_output();
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    if(((index & ~3) == 32'hffc) || ((index & ~3) == 32'h1ffc))
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      begin
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        if(base_offset < `INPUT_SIZE)
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         begin
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          Bit#(16) data_slice = (data_remaining > 1024) ? 1024 : truncate(data_remaining);
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          h264.bram_controller.data_input(zeroExtend({data_slice,8'hff}));
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         end
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        else
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         begin
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          h264.bram_controller.data_input(0);
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         end
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      end
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    else
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      begin
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       h264.bram_controller.data_input({rfile.sub(base_offset + (index  & (~32'h1003))+0), rfile.sub(base_offset + (index  & (~32'h1003)) + 1), rfile.sub(base_offset + (index  & (~32'h1003)) + 2), rfile.sub(base_offset + (index  & (~32'h1003)) + 3)});
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      end
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  endrule
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  rule write (h264.bram_controller.wen_output() != 0);
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    h264.bram_controller.data_input(0);
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    base_offset <= base_offset + 1024;
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    data_remaining <= data_remaining - 1024;
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  endrule
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  //interface ISRAMWires sram_controller1 =  h264.sram_controller;
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  //interface ISRAMWires sram_controller2 =  h264.sram_controller2;
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endmodule
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endpackage

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