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kfleming |
import Vector::*;
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import ActionSeq::*;
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import FIFOF::*;
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import FIFO::*;
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import GetPut::*;
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import ClientServer::*;
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import Register::*;
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interface ControlReg#(type addr_t, type data_t);
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method addr_t getAddr();
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method Action write(data_t x1);
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method ActionValue#(data_t) read();
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endinterface
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// function makeControlRegFromRAM(TBDRegisterMap regNum, HSTDEC_OCP_RAM_module_addr_t inc,
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// FIFO#(HSTDEC_OCP_RAM_module_addr_t));
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// begin
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// ControlReg#(HSTDEC_OCP_RAM_addr_t, HSTDEC_OCP_RAM_data_t) cr =
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// interface ControlReg
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// method HSTDEC_OCP_RAM_addr_t getAddr();
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// return zeroExtend(pack(regNum));
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// endmethod
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// method Action write(HSTDEC_OCP_RAM_data_t data);
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// begin
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// tbdRegs.hstRamAddr <= tbdRegs.hstRamAddr + inc;
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// (determineMemory(curTBD,tbdRegs)).writeReq.put(tuple2(truncate(tbdRegs.hstRamAddr),data));
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// end
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// endmethod
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// method ActionValue#(HSTDEC_OCP_RAM_data_t) read();
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// begin
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// let mem = (determineMemory(curTBD,tbdRegs));
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// debugModule(hstdecDebug, $display("HSTDEC Pushing read request"));
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// mem.readReq.put(truncate(tbdRegs.hstRamAddr));
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// state <= Read;
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// read_inc_fifo.enq(inc);
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// return ?;
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// end
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// endmethod
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// endinterface;
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// return cr;
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// end
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// rule complete_read;
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// let inc = read_inc_fifo.first; read_inc_fifo.deq;
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// let mem = (determineMemory(curTBD,tbdRegs));
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// tbdRegs.hstRamAddr <= tbdRegs.hstRamAddr + signExtend(inc);
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// let data <- mem.readResp().get();
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// resp_fifo.enq(data);
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// endrule
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// endfunction
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// function ControlReg#(addrT, dataT) mkControlReg(addrT addr,
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// function regDataT get(),
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// function Action put(regDataT))
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// provisos (Bits#(regDataT, regDataSz),
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// Bits#(dataT, dataSz),
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// Add#(regDataSz,aaa,dataSz));
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// ControlReg#(addrT, dataT) cr =
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// interface ControlReg;
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// method addrT getAddr();
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// return addr;
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// endmethod
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// method Action write(dataT data);
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// let foo <- put(unpack(truncate(pack(data))));
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// endmethod
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// method ActionValue#(dataT) read();
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// let data <- get();
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// return unpack(zeroExtend(pack(data)));
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// endmethod
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// endinterface;
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// return cr;
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// endfunction
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function ControlReg#(addrT, dataT) mkControlRegFromReg(addrT addr,
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Reg#(dataT) r)
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provisos (//Bits#(regDataT, regDataSz),
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Bits#(dataT, dataSz)
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//Add#(regDataSz,aaa,dataSz)
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);
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ControlReg#(addrT, dataT) cr =
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interface ControlReg;
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method addrT getAddr();
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return addr;
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endmethod
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method Action write(dataT data);
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r._write(data);
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endmethod
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method ActionValue#(dataT) read();
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let data = r._read();
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return data;
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endmethod
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endinterface;
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return cr;
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endfunction
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function ControlReg#(addrT, dataT) mkControlRegFromGet(addrT addr,
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Get#(dataT) get)
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provisos (Bits#(dataT, dataSz));
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ControlReg#(addrT, dataT) cr =
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interface ControlReg;
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method addrT getAddr();
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return addr;
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endmethod
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method Action write(dataT data);
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// no write method
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endmethod
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method ActionValue#(dataT) read();
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let data <- get.get();
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return data;
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endmethod
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endinterface;
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return cr;
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endfunction
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function ControlReg#(addrT, dataT) mkControlRegFromGetPut(addrT addr,
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Get#(dataT) get,
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Put#(dataT) put)
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provisos (Bits#(dataT, dataSz));
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ControlReg#(addrT, dataT) cr =
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interface ControlReg;
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method addrT getAddr();
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return addr;
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endmethod
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method Action write(dataT data);
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put.put(data);
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endmethod
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method ActionValue#(dataT) read();
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let data <- get.get();
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return data;
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endmethod
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endinterface;
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return cr;
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endfunction
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function ControlReg#(addrT, dataT) mkControlRegFromServer(addrT addr,
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Server#(dataT, dataT) server)
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provisos (Bits#(dataT, dataSz));
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ControlReg#(addrT, dataT) cr =
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interface ControlReg;
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method addrT getAddr();
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return addr;
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endmethod
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method Action write(dataT data);
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server.request.put(data);
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endmethod
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method ActionValue#(dataT) read();
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let data <- server.response.get();
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return data;
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endmethod
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endinterface;
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return cr;
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endfunction
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function Vector#(n, ControlReg#(addrT, dataT))
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addControlReg(Vector#(n, ControlReg#(addrT, dataT)) crvec,
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regNumT regNum,
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ControlReg#(addrT, dataT) cr)
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provisos (Bits#(regNumT, regNumSz),
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Bits#(addrT, addrSz),
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Bits#(dataT, ramDataSz),
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Add#(regNumSz,aaa,addrSz));
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crvec[zeroExtend(pack(regNum))] = cr;
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return crvec;
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endfunction
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function Vector#(n, ControlReg#(addrT, dataT))
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addControlRegFromReg(Vector#(n, ControlReg#(addrT, dataT)) crvec,
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regNumT regNum,
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Reg#(dataT) r)
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provisos (Bits#(regNumT, regNumSz),
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Bits#(addrT, addrSz),
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Bits#(dataT, ramDataSz),
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Add#(regNumSz,aaa,addrSz)
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);
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ControlReg#(addrT, dataT) cr =
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mkControlRegFromReg(unpack(zeroExtend(pack(regNum))), r);
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crvec[zeroExtend(pack(regNum))] = cr;
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return crvec;
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endfunction
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function Vector#(n, ControlReg#(addrT, dataT))
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addControlRegFromGet(Vector#(n, ControlReg#(addrT, dataT)) crvec,
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regNumT regNum,
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Get#(dataT) g)
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provisos (Bits#(dataT, ramDataSz),
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Bits#(regNumT, regNumSz),
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Bits#(addrT, addrSz),
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Add#(regNumSz,aaa,addrSz));
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ControlReg#(addrT, dataT) cr =
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mkControlRegFromGet(unpack(zeroExtend(pack(regNum))), g);
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crvec[zeroExtend(pack(regNum))] = cr;
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return crvec;
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endfunction
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function Vector#(n, ControlReg#(addrT, dataT))
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addControlRegFromGetPut(Vector#(n, ControlReg#(addrT, dataT)) crvec,
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regNumT regNum,
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Get#(dataT) g,
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Put#(dataT) p)
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provisos (Bits#(dataT, ramDataSz),
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Bits#(regNumT, regNumSz),
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Bits#(addrT, addrSz),
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Add#(regNumSz,aaa,addrSz));
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ControlReg#(addrT, dataT) cr =
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mkControlRegFromGetPut(unpack(zeroExtend(pack(regNum))), g, p);
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crvec[pack(regNum)] = cr;
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return crvec;
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endfunction
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function ControlReg#(addrT, dataT) widenControlReg(ControlReg#(nAddrT, nDataT) ncr)
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provisos (Bits#(addrT, addrSz),
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Bits#(dataT, dataSz),
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Bits#(nAddrT, nAddrSz),
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Bits#(nDataT, nDataSz),
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Add#(nDataSz,ddd,dataSz),
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Add#(nAddrSz,aaa,addrSz));
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ControlReg#(addrT, dataT) cr =
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interface ControlReg;
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method addrT getAddr();
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return unpack(zeroExtend(pack(ncr.getAddr())));
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endmethod
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method Action write(dataT data);
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ncr.write(unpack(truncate(pack(data))));
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endmethod
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method ActionValue#(dataT) read();
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let data <- ncr.read();
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return unpack(zeroExtend(pack(data)));
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endmethod
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endinterface;
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return cr;
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endfunction
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