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//////////////////////////////////////////////////////////////////////
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//// ////
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//// clock_detect_tb.v ////
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//// ////
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//// This file is part of the boundaries opencores effort. ////
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//// <http://www.opencores.org/cores/boundaries/> ////
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//// ////
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//// Module Description: ////
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//// Clock detect testbench. ////
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//// ////
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//// To Do: ////
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//// Done. ////
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//// ////
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//// Author(s): ////
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//// - Shannon Hill ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: clock_detect_tb.v,v 1.1 2004-07-07 12:39:14 esquehill Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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`timescale 1ns/1ps
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module clock_detect_tb();
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reg clk0_i;
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reg clk1_i;
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reg clk2_i;
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reg clk3_i;
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reg rst0_i;
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wire alive1;
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wire alive2;
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wire alive3;
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initial
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begin
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clk0_i <= 0;
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clk1_i <= 0;
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clk2_i <= 0;
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clk3_i <= 0;
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rst0_i <= 1;
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#10;
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rst0_i <= 0;
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#5000;
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if( alive1 & alive2 & ~alive3 ) $display("OK");
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else $display("BAD");
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$finish;
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end
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always #5 clk0_i <= ~clk0_i; // 10 ns
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always #150 clk1_i <= ~clk1_i;
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always #160 clk2_i <= ~clk2_i;
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always #170 clk3_i <= ~clk3_i;
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/* clock_detect AUTO_TEMPLATE (
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.rst_i (rst0_i),
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.clk_i (clk0_i),
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.sclk_i (clk1_i),
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.alive_o (alive1),
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); */
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clock_detect #(4) u_d1 ( /*AUTOINST*/
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// Outputs
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.alive_o (alive1), // Templated
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// Inputs
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.rst_i (rst0_i), // Templated
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.clk_i (clk0_i), // Templated
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.sclk_i (clk1_i)); // Templated
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/* clock_detect AUTO_TEMPLATE (
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.rst_i (rst0_i),
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.clk_i (clk0_i),
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.sclk_i (clk2_i),
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.alive_o (alive2),
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); */
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clock_detect #(4) u_d2 ( /*AUTOINST*/
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// Outputs
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.alive_o (alive2), // Templated
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// Inputs
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.rst_i (rst0_i), // Templated
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.clk_i (clk0_i), // Templated
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.sclk_i (clk2_i)); // Templated
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/* clock_detect AUTO_TEMPLATE (
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.rst_i (rst0_i),
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.clk_i (clk0_i),
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.sclk_i (clk3_i),
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.alive_o (alive3),
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); */
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clock_detect #(4) u_d3 ( /*AUTOINST*/
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// Outputs
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.alive_o (alive3), // Templated
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// Inputs
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.rst_i (rst0_i), // Templated
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.clk_i (clk0_i), // Templated
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.sclk_i (clk3_i)); // Templated
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endmodule
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