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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// clock_switch_tb.v                                            ////
////                                                              ////
//// This file is part of the boundaries opencores effort.        ////
//// <http://www.opencores.org/cores/boundaries/>                 ////
////                                                              ////
//// Module Description:                                          ////
////                                                              ////
//// Clock switcher testbench.                                    ////
////                                                              ////
//// To Do:                                                       ////
//// Done.                                                        ////
////                                                              ////
//// Author(s):                                                   ////
//// - Shannon Hill                                               ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: clock_switch_tb.v,v 1.1 2004-07-07 12:39:14 esquehill Exp $
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
`timescale 1ns/1ps
 
module clock_switch_tb();
 
reg       clock;
reg       clk0_i;
reg       clk1_i;
reg       clk2_i;
reg       clk3_i;
reg       clk4_i;
reg       clk5_i;
reg       clk6_i;
reg       clk7_i;
 
reg       rst0_i;
reg       rst1_i;
reg       rst2_i;
reg       rst3_i;
reg       rst4_i;
reg       rst5_i;
reg       rst6_i;
reg       rst7_i;
 
reg       enable;
reg [2:0] select;
 
real  launch_b2;
real  launch_b3;
real  launch_b4;
real  launch_b8;
 
real  actual_b2;
real  actual_b3;
real  actual_b4;
real  actual_b8;
 
real  expect_b2;
real  expect_b3;
real  expect_b4;
real  expect_b8;
 
integer passes;
 
initial
begin
 
 passes    = 0;
 
 launch_b2 = 0.0;
 launch_b3 = 0.0;
 launch_b4 = 0.0;
 launch_b8 = 0.0;
 
 actual_b2 = 0.0;
 actual_b3 = 0.0;
 actual_b4 = 0.0;
 actual_b8 = 0.0;
 
 clock    <= 0;
 
 clk0_i   <= 0;
 clk1_i   <= 0;
 clk2_i   <= 0;
 clk3_i   <= 0;
 clk4_i   <= 0;
 clk5_i   <= 0;
 clk6_i   <= 0;
 clk7_i   <= 0;
 
 rst0_i   <= 1;
 rst1_i   <= 1;
 rst2_i   <= 1;
 rst3_i   <= 1;
 rst4_i   <= 1;
 rst5_i   <= 1;
 rst6_i   <= 1;
 rst7_i   <= 1;
 
 enable   <= 1;
 select   <= 1;
 
#10;
 rst0_i   <= 0;
 rst1_i   <= 0;
 rst2_i   <= 0;
 rst3_i   <= 0;
 rst4_i   <= 0;
 rst5_i   <= 0;
 rst6_i   <= 0;
 rst7_i   <= 0;
end
 
always #50     clock  <= ~clock;
 
parameter C0P = 3.00;
parameter C1P = 4.00;
parameter C2P = 5.00;
parameter C3P = 6.00;
parameter C4P = 7.00;
parameter C5P = 8.00;
parameter C6P = 9.00;
parameter C7P = 10.00;
 
always #(C0P/2.0) clk0_i <= ~clk0_i;
always #(C1P/2.0) clk1_i <= ~clk1_i;
always #(C2P/2.0) clk2_i <= ~clk2_i;
always #(C3P/2.0) clk3_i <= ~clk3_i;
always #(C4P/2.0) clk4_i <= ~clk4_i;
always #(C5P/2.0) clk5_i <= ~clk5_i;
always #(C6P/2.0) clk6_i <= ~clk6_i;
always #(C7P/2.0) clk7_i <= ~clk7_i;
 
wire  clock_b2;
wire  clock_b3;
wire  clock_b4;
wire  clock_b8;
 
always @( posedge clock_b2 )
begin
 actual_b2 = $realtime - launch_b2;
 launch_b2 = $realtime;
end
 
always @( posedge clock_b3 )
begin
 actual_b3 = $realtime - launch_b3;
 launch_b3 = $realtime;
end
 
always @( posedge clock_b4 )
begin
 actual_b4 = $realtime - launch_b4;
 launch_b4 = $realtime;
end
 
always @( posedge clock_b8 )
begin
 actual_b8 = $realtime - launch_b8;
 launch_b8 = $realtime;
end
 
always @( posedge clock )
begin
 
    case( select[0] )
    1'b0: expect_b2 = C0P;
    1'b1: expect_b2 = C1P;
    endcase
 
    case( select[1:0] )
    2'b00: expect_b3 = C0P;
    2'b01: expect_b3 = C1P;
    2'b10: expect_b3 = C2P;
    2'b11: expect_b3 = C2P;
    endcase
 
    case( select[1:0] )
    2'b00: expect_b4 = C0P;
    2'b01: expect_b4 = C1P;
    2'b10: expect_b4 = C2P;
    2'b11: expect_b4 = C3P;
    endcase
 
    case( select[2:0] )
    3'b000: expect_b8 = C0P;
    3'b001: expect_b8 = C1P;
    3'b010: expect_b8 = C2P;
    3'b011: expect_b8 = C3P;
    3'b100: expect_b8 = C4P;
    3'b101: expect_b8 = C5P;
    3'b110: expect_b8 = C6P;
    3'b111: expect_b8 = C7P;
    endcase
 
    if( (launch_b2 > 0.0) & (expect_b2 != actual_b2))
    begin
     $display( "%d: expect_b2=%f, actual_b2=%f", $time, expect_b2, actual_b2);
     $stop;
    end
 
    if( (launch_b3 > 0.0) & (expect_b3 != actual_b3))
    begin
     $display( "%d: expect_b3=%f, actual_b3=%f", $time, expect_b3, actual_b3);
     $stop;
    end
 
    if( (launch_b4 > 0.0) & (expect_b4 != actual_b4))
    begin
     $display( "%d: expect_b4=%f, actual_b4=%f", $time, expect_b4, actual_b4);
     $stop;
    end
 
    if( (launch_b8 > 0.0) & (expect_b8 != actual_b8))
    begin
     $display( "%d: expect_b8=%f, actual_b8=%f", $time, expect_b8, actual_b8);
     $stop;
    end
 
    select <= select + 1;
 
    passes  = passes + 1;
 
    if( passes > 256 )
    begin
        $display("OK");
        $finish;
    end
end
 
/* clock_switch2_basic AUTO_TEMPLATE (
.select    (select[0]),
.clk_o     (clock_b2),
); */
 
clock_switch2_basic u_b2 ( /*AUTOINST*/
                          // Outputs
                          .clk_o        (clock_b2),              // Templated
                          // Inputs
                          .rst0_i       (rst0_i),
                          .clk0_i       (clk0_i),
                          .rst1_i       (rst1_i),
                          .clk1_i       (clk1_i),
                          .enable       (enable),
                          .select       (select[0]));             // Templated
 
/* clock_switch3_basic AUTO_TEMPLATE (
.select    (select[1:0]),
.clk_o     (clock_b3),
); */
 
clock_switch3_basic u_b3 ( /*AUTOINST*/
                          // Outputs
                          .clk_o        (clock_b3),              // Templated
                          // Inputs
                          .rst0_i       (rst0_i),
                          .clk0_i       (clk0_i),
                          .rst1_i       (rst1_i),
                          .clk1_i       (clk1_i),
                          .rst2_i       (rst2_i),
                          .clk2_i       (clk2_i),
                          .enable       (enable),
                          .select       (select[1:0]));           // Templated
 
/* clock_switch4_basic AUTO_TEMPLATE (
.select     (select[1:0]),
.clk_o      (clock_b4),
); */
 
clock_switch4_basic u_b4 ( /*AUTOINST*/
                          // Outputs
                          .clk_o        (clock_b4),              // Templated
                          // Inputs
                          .rst0_i       (rst0_i),
                          .clk0_i       (clk0_i),
                          .rst1_i       (rst1_i),
                          .clk1_i       (clk1_i),
                          .rst2_i       (rst2_i),
                          .clk2_i       (clk2_i),
                          .rst3_i       (rst3_i),
                          .clk3_i       (clk3_i),
                          .enable       (enable),
                          .select       (select[1:0]));           // Templated
 
/* clock_switch8_basic AUTO_TEMPLATE (
.select     (select[2:0]),
.clk_o      (clock_b8),
); */
 
clock_switch8_basic u_b8 ( /*AUTOINST*/
                          // Outputs
                          .clk_o        (clock_b8),              // Templated
                          // Inputs
                          .rst0_i       (rst0_i),
                          .clk0_i       (clk0_i),
                          .rst1_i       (rst1_i),
                          .clk1_i       (clk1_i),
                          .rst2_i       (rst2_i),
                          .clk2_i       (clk2_i),
                          .rst3_i       (rst3_i),
                          .clk3_i       (clk3_i),
                          .rst4_i       (rst4_i),
                          .clk4_i       (clk4_i),
                          .rst5_i       (rst5_i),
                          .clk5_i       (clk5_i),
                          .rst6_i       (rst6_i),
                          .clk6_i       (clk6_i),
                          .rst7_i       (rst7_i),
                          .clk7_i       (clk7_i),
                          .enable       (enable),
                          .select       (select[2:0]));           // Templated
 
reg     notify;
initial notify = 0;
 
always @( posedge notify ) $stop;
 
specify
specparam c_width = 1.50;  // is C0P/2.0
 
// check for narrow pulses
$width( negedge clock_b2, c_width, 0, notify );
$width( posedge clock_b2, c_width, 0, notify );
 
$width( negedge clock_b3, c_width, 0, notify );
$width( posedge clock_b3, c_width, 0, notify );
 
$width( negedge clock_b4, c_width, 0, notify );
$width( posedge clock_b4, c_width, 0, notify );
 
$width( negedge clock_b8, c_width, 0, notify );
$width( posedge clock_b8, c_width, 0, notify );
 
endspecify
 
endmodule

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[/] [boundaries/] [trunk/] [bench/] [verilog/] [clock_switch_tb.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	esquehill	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// clock_switch_tb.v ////`
4			`//// ////`
5			`//// This file is part of the boundaries opencores effort. ////`
6			`//// <http://www.opencores.org/cores/boundaries/> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`//// ////`
10			`//// Clock switcher testbench. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Done. ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Shannon Hill ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from <http://www.opencores.org/lgpl.shtml> ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// $Id: clock_switch_tb.v,v 1.1 2004-07-07 12:39:14 esquehill Exp $`
46			`//`
47			`// CVS Revision History`
48			`//`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`//`
52
53			`timescale 1ns/1ps
54
55			`module clock_switch_tb();`
56
57			`reg clock;`
58			`reg clk0_i;`
59			`reg clk1_i;`
60			`reg clk2_i;`
61			`reg clk3_i;`
62			`reg clk4_i;`
63			`reg clk5_i;`
64			`reg clk6_i;`
65			`reg clk7_i;`
66
67			`reg rst0_i;`
68			`reg rst1_i;`
69			`reg rst2_i;`
70			`reg rst3_i;`
71			`reg rst4_i;`
72			`reg rst5_i;`
73			`reg rst6_i;`
74			`reg rst7_i;`
75
76			`reg enable;`
77			`reg [2:0] select;`
78
79			`real launch_b2;`
80			`real launch_b3;`
81			`real launch_b4;`
82			`real launch_b8;`
83
84			`real actual_b2;`
85			`real actual_b3;`
86			`real actual_b4;`
87			`real actual_b8;`
88
89			`real expect_b2;`
90			`real expect_b3;`
91			`real expect_b4;`
92			`real expect_b8;`
93
94			`integer passes;`
95
96			`initial`
97			`begin`
98
99			`passes = 0;`
100
101			`launch_b2 = 0.0;`
102			`launch_b3 = 0.0;`
103			`launch_b4 = 0.0;`
104			`launch_b8 = 0.0;`
105
106			`actual_b2 = 0.0;`
107			`actual_b3 = 0.0;`
108			`actual_b4 = 0.0;`
109			`actual_b8 = 0.0;`
110
111			`clock <= 0;`
112
113			`clk0_i <= 0;`
114			`clk1_i <= 0;`
115			`clk2_i <= 0;`
116			`clk3_i <= 0;`
117			`clk4_i <= 0;`
118			`clk5_i <= 0;`
119			`clk6_i <= 0;`
120			`clk7_i <= 0;`
121
122			`rst0_i <= 1;`
123			`rst1_i <= 1;`
124			`rst2_i <= 1;`
125			`rst3_i <= 1;`
126			`rst4_i <= 1;`
127			`rst5_i <= 1;`
128			`rst6_i <= 1;`
129			`rst7_i <= 1;`
130
131			`enable <= 1;`
132			`select <= 1;`
133
134			`#10;`
135			`rst0_i <= 0;`
136			`rst1_i <= 0;`
137			`rst2_i <= 0;`
138			`rst3_i <= 0;`
139			`rst4_i <= 0;`
140			`rst5_i <= 0;`
141			`rst6_i <= 0;`
142			`rst7_i <= 0;`
143			`end`
144
145			`always #50 clock <= ~clock;`
146
147			`parameter C0P = 3.00;`
148			`parameter C1P = 4.00;`
149			`parameter C2P = 5.00;`
150			`parameter C3P = 6.00;`
151			`parameter C4P = 7.00;`
152			`parameter C5P = 8.00;`
153			`parameter C6P = 9.00;`
154			`parameter C7P = 10.00;`
155
156			`always #(C0P/2.0) clk0_i <= ~clk0_i;`
157			`always #(C1P/2.0) clk1_i <= ~clk1_i;`
158			`always #(C2P/2.0) clk2_i <= ~clk2_i;`
159			`always #(C3P/2.0) clk3_i <= ~clk3_i;`
160			`always #(C4P/2.0) clk4_i <= ~clk4_i;`
161			`always #(C5P/2.0) clk5_i <= ~clk5_i;`
162			`always #(C6P/2.0) clk6_i <= ~clk6_i;`
163			`always #(C7P/2.0) clk7_i <= ~clk7_i;`
164
165			`wire clock_b2;`
166			`wire clock_b3;`
167			`wire clock_b4;`
168			`wire clock_b8;`
169
170			`always @( posedge clock_b2 )`
171			`begin`
172			`actual_b2 = $realtime - launch_b2;`
173			`launch_b2 = $realtime;`
174			`end`
175
176			`always @( posedge clock_b3 )`
177			`begin`
178			`actual_b3 = $realtime - launch_b3;`
179			`launch_b3 = $realtime;`
180			`end`
181
182			`always @( posedge clock_b4 )`
183			`begin`
184			`actual_b4 = $realtime - launch_b4;`
185			`launch_b4 = $realtime;`
186			`end`
187
188			`always @( posedge clock_b8 )`
189			`begin`
190			`actual_b8 = $realtime - launch_b8;`
191			`launch_b8 = $realtime;`
192			`end`
193
194			`always @( posedge clock )`
195			`begin`
196
197			`case( select[0] )`
198			`1'b0: expect_b2 = C0P;`
199			`1'b1: expect_b2 = C1P;`
200			`endcase`
201
202			`case( select[1:0] )`
203			`2'b00: expect_b3 = C0P;`
204			`2'b01: expect_b3 = C1P;`
205			`2'b10: expect_b3 = C2P;`
206			`2'b11: expect_b3 = C2P;`
207			`endcase`
208
209			`case( select[1:0] )`
210			`2'b00: expect_b4 = C0P;`
211			`2'b01: expect_b4 = C1P;`
212			`2'b10: expect_b4 = C2P;`
213			`2'b11: expect_b4 = C3P;`
214			`endcase`
215
216			`case( select[2:0] )`
217			`3'b000: expect_b8 = C0P;`
218			`3'b001: expect_b8 = C1P;`
219			`3'b010: expect_b8 = C2P;`
220			`3'b011: expect_b8 = C3P;`
221			`3'b100: expect_b8 = C4P;`
222			`3'b101: expect_b8 = C5P;`
223			`3'b110: expect_b8 = C6P;`
224			`3'b111: expect_b8 = C7P;`
225			`endcase`
226
227			`if( (launch_b2 > 0.0) & (expect_b2 != actual_b2))`
228			`begin`
229			`$display( "%d: expect_b2=%f, actual_b2=%f", $time, expect_b2, actual_b2);`
230			`$stop;`
231			`end`
232
233			`if( (launch_b3 > 0.0) & (expect_b3 != actual_b3))`
234			`begin`
235			`$display( "%d: expect_b3=%f, actual_b3=%f", $time, expect_b3, actual_b3);`
236			`$stop;`
237			`end`
238
239			`if( (launch_b4 > 0.0) & (expect_b4 != actual_b4))`
240			`begin`
241			`$display( "%d: expect_b4=%f, actual_b4=%f", $time, expect_b4, actual_b4);`
242			`$stop;`
243			`end`
244
245			`if( (launch_b8 > 0.0) & (expect_b8 != actual_b8))`
246			`begin`
247			`$display( "%d: expect_b8=%f, actual_b8=%f", $time, expect_b8, actual_b8);`
248			`$stop;`
249			`end`
250
251			`select <= select + 1;`
252
253			`passes = passes + 1;`
254
255			`if( passes > 256 )`
256			`begin`
257			`$display("OK");`
258			`$finish;`
259			`end`
260			`end`
261
262			`/* clock_switch2_basic AUTO_TEMPLATE (`
263			`.select (select[0]),`
264			`.clk_o (clock_b2),`
265			`); */`
266
267			`clock_switch2_basic u_b2 ( /AUTOINST/`
268			`// Outputs`
269			`.clk_o (clock_b2), // Templated`
270			`// Inputs`
271			`.rst0_i (rst0_i),`
272			`.clk0_i (clk0_i),`
273			`.rst1_i (rst1_i),`
274			`.clk1_i (clk1_i),`
275			`.enable (enable),`
276			`.select (select[0])); // Templated`
277
278			`/* clock_switch3_basic AUTO_TEMPLATE (`
279			`.select (select[1:0]),`
280			`.clk_o (clock_b3),`
281			`); */`
282
283			`clock_switch3_basic u_b3 ( /AUTOINST/`
284			`// Outputs`
285			`.clk_o (clock_b3), // Templated`
286			`// Inputs`
287			`.rst0_i (rst0_i),`
288			`.clk0_i (clk0_i),`
289			`.rst1_i (rst1_i),`
290			`.clk1_i (clk1_i),`
291			`.rst2_i (rst2_i),`
292			`.clk2_i (clk2_i),`
293			`.enable (enable),`
294			`.select (select[1:0])); // Templated`
295
296			`/* clock_switch4_basic AUTO_TEMPLATE (`
297			`.select (select[1:0]),`
298			`.clk_o (clock_b4),`
299			`); */`
300
301			`clock_switch4_basic u_b4 ( /AUTOINST/`
302			`// Outputs`
303			`.clk_o (clock_b4), // Templated`
304			`// Inputs`
305			`.rst0_i (rst0_i),`
306			`.clk0_i (clk0_i),`
307			`.rst1_i (rst1_i),`
308			`.clk1_i (clk1_i),`
309			`.rst2_i (rst2_i),`
310			`.clk2_i (clk2_i),`
311			`.rst3_i (rst3_i),`
312			`.clk3_i (clk3_i),`
313			`.enable (enable),`
314			`.select (select[1:0])); // Templated`
315
316			`/* clock_switch8_basic AUTO_TEMPLATE (`
317			`.select (select[2:0]),`
318			`.clk_o (clock_b8),`
319			`); */`
320
321			`clock_switch8_basic u_b8 ( /AUTOINST/`
322			`// Outputs`
323			`.clk_o (clock_b8), // Templated`
324			`// Inputs`
325			`.rst0_i (rst0_i),`
326			`.clk0_i (clk0_i),`
327			`.rst1_i (rst1_i),`
328			`.clk1_i (clk1_i),`
329			`.rst2_i (rst2_i),`
330			`.clk2_i (clk2_i),`
331			`.rst3_i (rst3_i),`
332			`.clk3_i (clk3_i),`
333			`.rst4_i (rst4_i),`
334			`.clk4_i (clk4_i),`
335			`.rst5_i (rst5_i),`
336			`.clk5_i (clk5_i),`
337			`.rst6_i (rst6_i),`
338			`.clk6_i (clk6_i),`
339			`.rst7_i (rst7_i),`
340			`.clk7_i (clk7_i),`
341			`.enable (enable),`
342			`.select (select[2:0])); // Templated`
343
344			`reg notify;`
345			`initial notify = 0;`
346
347			`always @( posedge notify ) $stop;`
348
349			`specify`
350			`specparam c_width = 1.50; // is C0P/2.0`
351
352			`// check for narrow pulses`
353			`$width( negedge clock_b2, c_width, 0, notify );`
354			`$width( posedge clock_b2, c_width, 0, notify );`
355
356			`$width( negedge clock_b3, c_width, 0, notify );`
357			`$width( posedge clock_b3, c_width, 0, notify );`
358
359			`$width( negedge clock_b4, c_width, 0, notify );`
360			`$width( posedge clock_b4, c_width, 0, notify );`
361
362			`$width( negedge clock_b8, c_width, 0, notify );`
363			`$width( posedge clock_b8, c_width, 0, notify );`
364
365			`endspecify`
366
367			`endmodule`