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//////////////////////////////////////////////////////////////////////
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//// ////
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//// bc_fifo_basic.v ////
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//// ////
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//// This file is part of the boundaries opencores effort. ////
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//// <http://www.opencores.org/cores/boundaries/> ////
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//// ////
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//// Module Description: ////
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//// ////
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//// Asynchronous Boundary Crossing FIFO ////
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//// ////
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//// 2 Parameters: Address Width, Data Width ////
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//// Data storage is internally inferred. ////
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//// Protected against read-while-empty and write-while-full ////
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//// The minimum address width (AW) is 2. ////
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//// ////
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//// To Do: ////
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//// Verify in silicon. ////
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//// ////
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//// Author(s): ////
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//// - Shannon Hill ////
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//// (based on the generic_fifo_dc_gray design from ////
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//// Rudolf Usselmann. This variant infers its own ////
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//// data storage, defends itself against write-while-full ////
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//// and read-while-empty, and forces its output data to 0 ////
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//// when empty.) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: bc_fifo_basic.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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module bc_fifo_basic( /*AUTOARG*/
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// Outputs
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get_do, get_have, put_need,
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// Inputs
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put_rst_i, get_rst_i, get_clk_i, get, put_clk_i, put_di, put
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);
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parameter AW=3; // default address width
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parameter DW=8; // default data width
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input put_rst_i; // async reset from the put_clk_i domain
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input get_rst_i; // async reset from the get_clk_i domain
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input get_clk_i;
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output [DW-1:0] get_do;
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input get;
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output get_have; // fifo has 1 or more
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input put_clk_i;
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input [DW-1:0] put_di;
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input put;
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output put_need; // fifo has room for 1 more
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reg [AW :0] rp_bin;
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reg [AW :0] rp_gra;
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reg [AW :0] rp_gra_sync;
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reg [AW :0] wp_bin;
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reg [AW :0] wp_gra;
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reg [AW :0] wp_gra_sync;
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reg put_full;
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reg get_emty;
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wire get_have = ~get_emty;
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wire put_need = ~put_full;
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reg [DW-1:0] mem [0:(1<<AW)-1]; // fifo data
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wire [DW-1:0] get_do = {DW{get_have}} & mem[ rp_bin[AW-1:0] ]; // output data
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//////////////////////////
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function [AW:0] bin_to_gray;
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input [AW:0] b;
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begin
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bin_to_gray = b ^ (b>>1);
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end
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endfunction
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//////////////////////////
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function [AW:0] gray_to_bin;
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input [AW:0] g;
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reg [AW:0] b;
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integer i;
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begin
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for( i=0; i<=AW; i=i+1 ) b[i] = ^(g>>i);
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gray_to_bin = b;
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end
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endfunction
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////////////////////////////
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// in the get_clk_i domain
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////////////////////////////
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wire [AW :0] rp_bin_add1 = rp_bin + 1'd1;
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wire [AW :0] rp_gra_add1 = bin_to_gray( rp_bin_add1 );
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//
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// get the gray-coded write pointer over to the get_clk_i domain
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//
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always @( posedge get_clk_i or posedge get_rst_i ) // put_clk_i to get_clk_i boundary crossing
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if( get_rst_i )
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wp_gra_sync <= 0;
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else wp_gra_sync <= wp_gra;
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//
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// convert the sampled graycode read pointer to binary
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//
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// wire [AW :0] wp_bin_sync = gray_to_bin( wp_gra_sync );
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// compare the write pointer and read pointer
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//
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// set empty when: getting AND the next read pointer == the current write pointer
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// hold empty when: read pointer == write pointer
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// clr empty when: read pointer no longer equal to write pointer
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//
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always @( posedge get_clk_i or posedge get_rst_i )
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if( get_rst_i )
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begin
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rp_bin <= 0;
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rp_gra <= 0;
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get_emty <= 1'b1;
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end
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else
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begin
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get_emty <= ( rp_gra == wp_gra_sync ) |
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( get & ~get_emty & ( rp_gra_add1 == wp_gra_sync ) );
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if( get & ~get_emty )
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begin
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rp_bin <= rp_bin_add1;
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rp_gra <= rp_gra_add1;
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end
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end
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////////////////////////////////
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// over in the put_clk_i domain
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////////////////////////////////
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wire [AW :0] wp_bin_add1 = wp_bin + 1'd1;
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wire [AW :0] wp_gra_add1 = bin_to_gray( wp_bin_add1 );
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//
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// get the gray-coded read pointer over to the put_clk_i domain
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//
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always @( posedge put_clk_i or posedge put_rst_i ) // get_clk_i to put_clk_i boundary crossing
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if( put_rst_i )
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rp_gra_sync <= 0;
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else rp_gra_sync <= rp_gra;
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//
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// convert the sampled graycode read pointer to binary
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//
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wire [AW :0] rp_bin_sync = gray_to_bin( rp_gra_sync );
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// compare the read pointer and write pointer
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//
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// set full when: putting AND the next write pointer == read pointer
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// hold full when: full and write pointer == read pointer
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// clr full when: write pointer no longer equal to read pointer
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//
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always @( posedge put_clk_i or posedge put_rst_i )
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if( put_rst_i )
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begin
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wp_bin <= 0;
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wp_gra <= 0;
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put_full <= 1'b0;
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end
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else
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begin
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put_full <=
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( ( wp_bin[ AW-1:0] == rp_bin_sync[AW-1:0] ) & ( wp_bin[ AW] != rp_bin_sync[AW] ) ) |
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( put & ~put_full & ( wp_bin_add1[AW-1:0] == rp_bin_sync[AW-1:0] ) & ( wp_bin_add1[AW] != rp_bin_sync[AW] ) );
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if( put & ~put_full )
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begin
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wp_bin <= wp_bin_add1;
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wp_gra <= wp_gra_add1;
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end
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end
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always @( posedge put_clk_i )
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if( put & ~put_full ) mem[ wp_bin[AW-1:0] ] <= put_di; // do the data write
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endmodule
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