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//////////////////////////////////////////////////////////////////////
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//// ////
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//// clock_switch2_basic.v ////
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//// ////
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//// This file is part of the boundaries opencores effort. ////
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//// <http://www.opencores.org/cores/boundaries/> ////
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//// ////
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//// Module Description: ////
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//// ////
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//// 1-of-2 glitchless clock switcher ////
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//// ////
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//// The 2 clocks, enable, and select are assumed to be ////
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//// asynchronous. ////
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//// ////
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//// Selecting/deselecting a stopped clock is not handled. ////
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//// ////
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//// To Do: ////
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//// Verify in silicon. ////
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//// ////
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//// Author(s): ////
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//// - Shannon Hill ////
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//// (based on "Techniques to make clock switching glitch free" ////
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//// By Rafey Mahmud; EEdesign.com June 26, 2003) ////
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//// ////
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//// http://www.eedesign.com/showArticle.jhtml?articleID=16501239 ////
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//// ////
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//// (modified to use positive edge flops; to stall the output ////
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//// clock high). ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Id: clock_switch2_basic.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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module clock_switch2_basic( /*AUTOARG*/
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// Outputs
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clk_o,
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// Inputs
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rst0_i, clk0_i, rst1_i, clk1_i, enable, select
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);
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input rst0_i;
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input clk0_i;
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input rst1_i;
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input clk1_i;
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input enable; // start&stop the clock
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input select; // select which source clock
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output clk_o;
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wire sel0 = ~select & enable;
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wire sel1 = select & enable;
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reg [1:0] ssync0; // selection synchronizers
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reg [1:0] ssync1;
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always @( posedge clk0_i or posedge rst0_i)
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if( rst0_i )
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ssync0 <= 2'b0;
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else ssync0 <= { ssync0[0] , (sel0 & ~ssync1[1] ) }; // async input
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always @( posedge clk1_i or posedge rst1_i)
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if( rst1_i )
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ssync1 <= 2'b0;
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else ssync1 <= { ssync1[0] , (sel1 & ~ssync0[1] ) }; // async input
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wire gclk0 = ~ssync0[1] | clk0_i; // forced 1 when not selected
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wire gclk1 = ~ssync1[1] | clk1_i; // forced 1 when not selected
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wire clk_o = gclk0 & gclk1; // clock stalls high
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endmodule
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