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[/] [brisc/] [trunk/] [register.v] - Blame information for rev 3

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module register(in, out, clk, reset_n);
 
parameter dw = 8;
 
input [dw-1:0] in;
input clk;
input reset_n;
 
output reg [dw-1:0] out;
 
 
always @(posedge clk or negedge reset_n)
begin
        if (!reset_n)
                out <= 0;
        else
                out <= in;
end
 
endmodule

Line No.	Rev	Author	Line
1	2	waqqas.jab	`module register(in, out, clk, reset_n);`
2
3			`parameter dw = 8;`
4
5			`input [dw-1:0] in;`
6			`input clk;`
7			`input reset_n;`
8
9			`output reg [dw-1:0] out;`
10
11
12			`always @(posedge clk or negedge reset_n)`
13			`begin`
14			`if (!reset_n)`
15			`out <= 0;`
16			`else`
17			`out <= in;`
18			`end`
19
20			`endmodule`

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[/] [brisc/] [trunk/] [register.v] - Blame information for rev 3