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[/] [brsfmnce/] [trunk/] [Sim/] [tb_BRSFmnCE.v] - Blame information for rev 3

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Line No.	Rev	Author	Line
1	2	MichaelA	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company: M. A. Morris & Associates`
5			`// Engineer: Michael A. Morris`
6			`//`
7			`// Create Date: 17:33:56 07/27/2008`
8			`// Design Name: BRSFmnCE`
9			`// Module Name: C:/XProjects/ISE10.1i/BRAMFIFO/tb_BRSFmnCE.v`
10			`// Project Name: BRAMFIFO`
11			`// Target Device: SRAM-based FPGA: XC3S1400AN-4FGG656I, XC3S700AN-4FGG484I`
12			`// Tool versions: ISE 10.1i SP3`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: BRSFmnCE`
16			`//`
17			`// Dependencies: None`
18			`//`
19	3	MichaelA	`// Revision:`
20			`//`
21			`// 1.00 08F27 MAM File Created`
22			`//`
23	2	MichaelA	`// 1.10 13G12 MAM Prepared for release on Opencore.com.`
24	3	MichaelA	`//`
25	2	MichaelA	`// Additional Comments:`
26			`//`
27			`////////////////////////////////////////////////////////////////////////////////`
28
29			`module tb_BRSFmnCE;`
30
31			`// Inputs`
32	3	MichaelA	`reg Rst;`
33			`reg Clk;`
34
35			`reg Clr;`
36
37			`reg WE;`
38			`reg [7:0] DI;`
39
40			`reg RE;`
41			`wire [7:0] DO;`
42			`wire ACK;`
43
44			`wire FF;`
45			`wire AF;`
46			`wire HF;`
47			`wire AE;`
48			`wire EF;`
49
50			`wire [10:0] Cnt;`
51	2	MichaelA
52			`integer i;`
53
54			`// Instantiate the Unit Under Test (UUT)`
55	3	MichaelA
56	2	MichaelA	`BRSFmnCE uut (`
57			`.Rst(Rst),`
58			`.Clk(Clk),`
59	3	MichaelA
60			`.Clr(Clr),`
61	2	MichaelA
62			`.WE(WE),`
63			`.DI(DI),`
64	3	MichaelA
65	2	MichaelA	`.RE(RE),`
66			`.DO(DO),`
67			`.ACK(ACK),`
68	3	MichaelA
69	2	MichaelA	`.FF(FF),`
70			`.AF(AF),`
71			`.HF(HF),`
72			`.AE(AE),`
73			`.EF(EF),`
74	3	MichaelA
75	2	MichaelA	`.Cnt(Cnt)`
76			`);`
77
78			`initial begin`
79			`// Initialize Inputs`
80			`Rst = 1;`
81	3	MichaelA	`Clk = 1;`
82			`Clr = 0;`
83			`WE = 0;`
84			`RE = 0;`
85			`DI = $random(5);`
86	2	MichaelA
87	3	MichaelA	`i = 0;`
88	2	MichaelA
89			`// Wait 100 ns for global reset to finish`
90	3	MichaelA	`#101 Rst = 0;`
91	2	MichaelA
92	3	MichaelA	`// Add stimulus here`
93
94	2	MichaelA	`while (AF != 1) begin`
95			`@(posedge Clk) #1;`
96			`if(AF != 1) begin`
97			`DI = $random;`
98			`WE = ~FF;`
99			`i = i + 1;`
100			`end`
101			`end`
102
103			`WE = 0; DI = 0;`
104
105			`RE = ~EF;`
106			`while (AE != 1) begin`
107			`@(posedge Clk) #1;`
108			`if (AE != 1) begin`
109			`RE = ~EF;`
110			`i = i - 1;`
111			`end`
112			`end`
113			`RE = 0; i = i - 1;`
114
115			`@(negedge ACK);`
116			`@(posedge Clk) #1; WE = 1; DI = $random; i = i + 1;`
117			`@(posedge Clk) #1; WE = 0;`
118
119			`@(posedge Clk) #1; RE = 1;`
120			`@(posedge Clk) #1; RE = 0; i = i - 1;`
121
122			`end`
123	3	MichaelA
124			`////////////////////////////////////////////////////////////////////////////////`
125			`//`
126			`// Clock`
127			`//`
128	2	MichaelA
129			`always #5 Clk = ~Clk;`
130
131	3	MichaelA	`////////////////////////////////////////////////////////////////////////////////`
132
133	2	MichaelA	`endmodule`
134

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[/] [brsfmnce/] [trunk/] [Sim/] [tb_BRSFmnCE.v] - Blame information for rev 3