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[/] [brsfmnce/] [trunk/] [Sim/] [tb_BRSFmnCE.v] - Blame information for rev 2

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Line No.	Rev	Author	Line
1	2	MichaelA	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company: M. A. Morris & Associates`
5			`// Engineer: Michael A. Morris`
6			`//`
7			`// Create Date: 17:33:56 07/27/2008`
8			`// Design Name: BRSFmnCE`
9			`// Module Name: C:/XProjects/ISE10.1i/BRAMFIFO/tb_BRSFmnCE.v`
10			`// Project Name: BRAMFIFO`
11			`// Target Device: SRAM-based FPGA: XC3S1400AN-4FGG656I, XC3S700AN-4FGG484I`
12			`// Tool versions: ISE 10.1i SP3`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: BRSFmnCE`
16			`//`
17			`// Dependencies: None`
18			`//`
19			`// Revision:`
20			`//`
21			`// 1.00 08F27 MAM File Created`
22			`//`
23			`// 1.10 13G12 MAM Prepared for release on Opencore.com.`
24			`//`
25			`// Additional Comments:`
26			`//`
27			`////////////////////////////////////////////////////////////////////////////////`
28
29			`module tb_BRSFmnCE;`
30
31			`// Inputs`
32			`reg Rst;`
33			`reg Clk;`
34			`reg WE;`
35			`reg RE;`
36			`reg [7:0] DI;`
37
38			`// Outputs`
39			`wire [7:0] DO;`
40			`wire ACK;`
41			`wire FF;`
42			`wire AF;`
43			`wire HF;`
44			`wire AE;`
45			`wire EF;`
46			`wire [10:0] Cnt;`
47
48			`integer i;`
49
50			`// Instantiate the Unit Under Test (UUT)`
51
52			`BRSFmnCE uut (`
53			`.Rst(Rst),`
54			`.Clk(Clk),`
55
56			`.WE(WE),`
57			`.DI(DI),`
58
59			`.RE(RE),`
60			`.DO(DO),`
61			`.ACK(ACK),`
62
63			`.FF(FF),`
64			`.AF(AF),`
65			`.HF(HF),`
66			`.AE(AE),`
67			`.EF(EF),`
68
69			`.Cnt(Cnt)`
70			`);`
71
72			`initial begin`
73			`// Initialize Inputs`
74			`Rst = 1;`
75			`Clk = 1;`
76			`WE = 0;`
77			`RE = 0;`
78			`DI = $random(5);`
79
80			`i = 0;`
81
82			`// Wait 100 ns for global reset to finish`
83			`#106 Rst = 0;`
84
85			`// Add stimulus here`
86
87			`while (AF != 1) begin`
88			`@(posedge Clk) #1;`
89			`if(AF != 1) begin`
90			`DI = $random;`
91			`WE = ~FF;`
92			`i = i + 1;`
93			`end`
94			`end`
95
96			`WE = 0; DI = 0;`
97
98			`RE = ~EF;`
99			`while (AE != 1) begin`
100			`@(posedge Clk) #1;`
101			`if (AE != 1) begin`
102			`RE = ~EF;`
103			`i = i - 1;`
104			`end`
105			`end`
106			`RE = 0; i = i - 1;`
107
108			`@(negedge ACK);`
109			`@(posedge Clk) #1; WE = 1; DI = $random; i = i + 1;`
110			`@(posedge Clk) #1; WE = 0;`
111
112			`@(posedge Clk) #1; RE = 1;`
113			`@(posedge Clk) #1; RE = 0; i = i - 1;`
114
115			`end`
116
117			`////////////////////////////////////////////////////////////////////////////////`
118			`//`
119			`// Clock`
120			`//`
121
122			`always #5 Clk = ~Clk;`
123
124			`////////////////////////////////////////////////////////////////////////////////`
125
126			`endmodule`
127

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[/] [brsfmnce/] [trunk/] [Sim/] [tb_BRSFmnCE.v] - Blame information for rev 2