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Subversion Repositories btc_dsha256

[/] [btc_dsha256/] [trunk/] [rtl/] [vhdl/] [TestBench/] [btc_dsha_TB.vhd] - Blame information for rev 2

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library hotan;
use hotan.sha_256_pkg.all;
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
        -- Add your library and packages declaration here ...
 
entity btc_dsha_tb is
        -- Generic declarations of the tested unit
                generic(
                gBASE_DELAY : INTEGER := 1 );
end btc_dsha_tb;
 
architecture TB_ARCHITECTURE of btc_dsha_tb is
        -- Component declaration of the tested unit
        component btc_dsha
                generic(
                gBASE_DELAY : INTEGER := 1 );
        port(
                iClkReg : in STD_LOGIC;
                iClkProcess : in STD_LOGIC;
                iRst_async : in STD_LOGIC;
                iValid_p : in STD_LOGIC;
                ivAddr : in STD_LOGIC_VECTOR(3 downto 0);
                ivData : in STD_LOGIC_VECTOR(31 downto 0);
                oReachEnd : out STD_LOGIC;
                oFoundNonce : out STD_LOGIC;
                ovNonce : out STD_LOGIC_VECTOR(31 downto 0);
                ovDigest : out tDwordArray(0 to 7) );
        end component;
 
        component sha_256_chunk
        generic(
                gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
                gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');
                gBASE_DELAY : integer := 1
        );
        port(
                iClk : in STD_LOGIC;
                iRst_async : in STD_LOGIC;
                iValid : in STD_LOGIC;
                ivMsgDword : in tDwordArray(0 to 15);
                ivH0 : in STD_LOGIC_VECTOR(31 downto 0);
                ivH1 : in STD_LOGIC_VECTOR(31 downto 0);
                ivH2 : in STD_LOGIC_VECTOR(31 downto 0);
                ivH3 : in STD_LOGIC_VECTOR(31 downto 0);
                ivH4 : in STD_LOGIC_VECTOR(31 downto 0);
                ivH5 : in STD_LOGIC_VECTOR(31 downto 0);
                ivH6 : in STD_LOGIC_VECTOR(31 downto 0);
                ivH7 : in STD_LOGIC_VECTOR(31 downto 0);
                ovH0 : out STD_LOGIC_VECTOR(31 downto 0);
                ovH1 : out STD_LOGIC_VECTOR(31 downto 0);
                ovH2 : out STD_LOGIC_VECTOR(31 downto 0);
                ovH3 : out STD_LOGIC_VECTOR(31 downto 0);
                ovH4 : out STD_LOGIC_VECTOR(31 downto 0);
                ovH5 : out STD_LOGIC_VECTOR(31 downto 0);
                ovH6 : out STD_LOGIC_VECTOR(31 downto 0);
                ovH7 : out STD_LOGIC_VECTOR(31 downto 0) );
        end component;
 
        component pipelines_without_reset IS
                GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);
                PORT(
                        iClk                            : IN            STD_LOGIC;
                        iInput                          : IN            STD_LOGIC;
                        ivInput                         : IN            STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);
                        oDelayed_output         : OUT           STD_LOGIC;
                        ovDelayed_output        : OUT           STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)
                );
        end component;
 
        -- Stimulus signals - signals mapped to the input and inout ports of tested entity
        signal iClkReg : STD_LOGIC := '1';
        signal iClkProcess : STD_LOGIC := '1';
        signal iRst_async : STD_LOGIC := '1';
        signal iValid_p : STD_LOGIC := '0';
        signal ivAddr : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
        signal ivData : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
        -- Observed signals - signals mapped to the output ports of tested entity
        signal oReachEnd : STD_LOGIC := '0';
        signal oFoundNonce : STD_LOGIC := '0';
        signal ovNonce : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
        signal ovDigest : tDwordArray(0 to 7) := (others=>(others=>'0'));
 
        -- Add your code here ...
        constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
        constant cCMD_IDLE : std_logic_vector(15 downto 0) := X"0000";
        constant cCMD_RESET : std_logic_vector(15 downto 0) := X"CAFE";
        constant cCMD_START : std_logic_vector(15 downto 0) := X"0001";
 
        signal svWork : tDwordArray(0 to 31) := (others=>(others=>'0'));
 
        signal siWriteCnt : std_logic_vector(31 downto 0) := (others => '0');
 
        signal sHashMidStateValidIn : std_logic := '0';
        signal sHashMidStateValidOut : std_logic := '0';
        signal svHashMidStateDataOut : tDwordArray(0 to 7) := (others=>(others=>'0'));
        signal svMidState : tDwordArray(0 to 7) := (others=>(others=>'0'));
        signal sMidStateValid : std_logic := '0';
 
begin
 
        -- Unit Under Test port map
        UUT : btc_dsha
                generic map (
                        gBASE_DELAY => gBASE_DELAY
                )
 
                port map (
                        iClkReg => iClkReg,
                        iClkProcess => iClkProcess,
                        iRst_async => iRst_async,
                        iValid_p => iValid_p,
                        ivAddr => ivAddr,
                        ivData => ivData,
                        oReachEnd => oReachEnd,
                        oFoundNonce => oFoundNonce,
                        ovNonce => ovNonce,
                        ovDigest => ovDigest
                );
 
        -- Add your stimulus here ...
 
        iClkReg <= not iClkReg after 5 ns;
        iClkProcess <= not iClkProcess after 5 ns;
        iRst_async <= '0' after 71 ns;
 
        svWork(0) <= X"02000000" after 251 ns;
        svWork(1) <= X"ea144059" after 251 ns;
        svWork(2) <= X"2a8b0d36" after 251 ns;
        svWork(3) <= X"b2e5f8a4" after 251 ns;
        svWork(4) <= X"85db1c04" after 251 ns;
        svWork(5) <= X"ca9290ca" after 251 ns;
        svWork(6) <= X"05bdc7f2" after 251 ns;
        svWork(7) <= X"05000000" after 251 ns;
        svWork(8) <= X"00000000" after 251 ns;
        svWork(9) <= X"11dfffb5" after 251 ns;
        svWork(10) <= X"ad285596" after 251 ns;
        svWork(11) <= X"8e4403d0" after 251 ns;
        svWork(12) <= X"60bdf636" after 251 ns;
        svWork(13) <= X"a023e387" after 251 ns;
        svWork(14) <= X"2870bbdc" after 251 ns;
        svWork(15) <= X"92e0aede" after 251 ns;
        svWork(16) <= X"acde4c0e" after 251 ns;
        svWork(17) <= X"032A6C52" after 251 ns;
        svWork(18) <= X"85fc0a19" after 251 ns;
        svWork(19) <= X"0BCFA6B6" after 251 ns;
 
 
        process(iClkReg, iRst_async)
        begin
                if iRst_async = '1' then
                        siWriteCnt <= (others => '0');
                        iValid_p <= '0';
                elsif rising_edge(iClkReg) then
                        if sMidStateValid = '1' then
                                siWriteCnt <= siWriteCnt + '1';
                        end if;
 
                        if siWriteCnt(3 downto 0) = X"F" and siWriteCnt(15 downto 4) <= conv_std_logic_vector(13, 12) then
                                iValid_p <= '1';
                        else
                                iValid_p <= '0';
                        end if;
                end if;
        end process;
 
        process(iClkReg, iRst_async)
        begin
                if iRst_async = '1' then
                        ivAddr <= (others=>'0');
                        ivData <= (others=>'0');
                elsif rising_edge(iClkReg) then
                        if siWriteCnt(3 downto 0) = X"F" then
                                case siWriteCnt(15 downto 4) is
                                        when X"000" =>
                                        ivAddr <= X"0";
                                        ivData <= svMidState(0);
 
                                        when X"001" =>
                                        ivAddr <= X"1";
                                        ivData <= svMidState(1);
 
                                        when X"002" =>
                                        ivAddr <= X"2";
                                        ivData <= svMidState(2);
 
                                        when X"003" =>
                                        ivAddr <= X"3";
                                        ivData <= svMidState(3);
 
                                        when X"004" =>
                                        ivAddr <= X"4";
                                        ivData <= svMidState(4);
 
                                        when X"005" =>
                                        ivAddr <= X"5";
                                        ivData <= svMidState(5);
 
                                        when X"006" =>
                                        ivAddr <= X"6";
                                        ivData <= svMidState(6);
 
                                        when X"007" =>
                                        ivAddr <= X"7";
                                        ivData <= svMidState(7);
 
                                        when X"008" =>
                                        ivAddr <= X"8";
                                        ivData <= svWork(16);
 
                                        when X"009" =>
                                        ivAddr <= X"9";
                                        ivData <= svWork(17);
 
                                        when X"00A" =>
                                        ivAddr <= X"A";
                                        ivData <= svWork(18);
 
                                        when X"00B" =>
                                        ivAddr <= X"B";
                                        ivData <= svWork(19) - X"20";
 
                                        when X"00C" =>
                                        ivAddr <= X"C";
                                        ivData <= svWork(19); -- + X"02";
 
                                        when X"00D" =>
                                        ivAddr <= cCMD_ADDR;
                                        ivData <= X"0000" & cCMD_START;
 
                                        when others =>
                                        ivAddr <= cCMD_ADDR;
                                        ivData <= X"0000" & cCMD_IDLE;
                                end case;
                        end if;
                end if;
        end process;
 
 
        sHashMidStateValidIn <= '1' after 251 ns, '0' after 261 ns;
 
        sha_256_chunk_inst_HashMidState : sha_256_chunk
                generic map(
                        gMSG_IS_CONSTANT => (others=>'0'),
                        gH_IS_CONST => (others=>'1'),
                        gBASE_DELAY => gBASE_DELAY
                )
                port map (
                        iClk => iClkProcess,
                        iRst_async => iRst_async,
                        iValid => sHashMidStateValidIn,
 
                        ivMsgDword => svWork(0 to 15),
 
                        ivH0 => X"6a09e667",
                        ivH1 => X"bb67ae85",
                        ivH2 => X"3c6ef372",
                        ivH3 => X"a54ff53a",
                        ivH4 => X"510e527f",
                        ivH5 => X"9b05688c",
                        ivH6 => X"1f83d9ab",
                        ivH7 => X"5be0cd19",
 
                        ovH0 => svHashMidStateDataOut(0),
                        ovH1 => svHashMidStateDataOut(1),
                        ovH2 => svHashMidStateDataOut(2),
                        ovH3 => svHashMidStateDataOut(3),
                        ovH4 => svHashMidStateDataOut(4),
                        ovH5 => svHashMidStateDataOut(5),
                        ovH6 => svHashMidStateDataOut(6),
                        ovH7 => svHashMidStateDataOut(7)
                );
 
        pipelines_without_reset_Valid : pipelines_without_reset
                GENERIC map(gBUS_WIDTH => 1, gNB_PIPELINES => (64 * gBASE_DELAY + 1))
                PORT map(
                        iClk => iClkProcess,
                        iInput => sHashMidStateValidIn,
                        ivInput => (others=>'0'),
                        oDelayed_output => sHashMidStateValidOut,
                        ovDelayed_output => open
                );
 
        process(iClkProcess)
        begin
                if rising_edge(iClkProcess) then
                        if sHashMidStateValidOut = '1' then
                                svMidState <= svHashMidStateDataOut;
                                sMidStateValid <= '1';
                        end if;
                end if;
        end process;
 
end TB_ARCHITECTURE;
 
configuration TESTBENCH_FOR_btc_dsha of btc_dsha_tb is
        for TB_ARCHITECTURE
                for UUT : btc_dsha
                        use entity work.btc_dsha(behavioral);
                end for;
        end for;
end TESTBENCH_FOR_btc_dsha;
 

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Subversion Repositories btc_dsha256

[/] [btc_dsha256/] [trunk/] [rtl/] [vhdl/] [TestBench/] [btc_dsha_TB.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	nuxi1209	`library hotan;`
2			`use hotan.sha_256_pkg.all;`
3			`library ieee;`
4			`use ieee.NUMERIC_STD.all;`
5			`use ieee.STD_LOGIC_UNSIGNED.all;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.std_logic_arith.all;`
8
9			`-- Add your library and packages declaration here ...`
10
11			`entity btc_dsha_tb is`
12			`-- Generic declarations of the tested unit`
13			`generic(`
14			`gBASE_DELAY : INTEGER := 1 );`
15			`end btc_dsha_tb;`
16
17			`architecture TB_ARCHITECTURE of btc_dsha_tb is`
18			`-- Component declaration of the tested unit`
19			`component btc_dsha`
20			`generic(`
21			`gBASE_DELAY : INTEGER := 1 );`
22			`port(`
23			`iClkReg : in STD_LOGIC;`
24			`iClkProcess : in STD_LOGIC;`
25			`iRst_async : in STD_LOGIC;`
26			`iValid_p : in STD_LOGIC;`
27			`ivAddr : in STD_LOGIC_VECTOR(3 downto 0);`
28			`ivData : in STD_LOGIC_VECTOR(31 downto 0);`
29			`oReachEnd : out STD_LOGIC;`
30			`oFoundNonce : out STD_LOGIC;`
31			`ovNonce : out STD_LOGIC_VECTOR(31 downto 0);`
32			`ovDigest : out tDwordArray(0 to 7) );`
33			`end component;`
34
35			`component sha_256_chunk`
36			`generic(`
37			`gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');`
38			`gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');`
39			`gBASE_DELAY : integer := 1`
40			`);`
41			`port(`
42			`iClk : in STD_LOGIC;`
43			`iRst_async : in STD_LOGIC;`
44			`iValid : in STD_LOGIC;`
45			`ivMsgDword : in tDwordArray(0 to 15);`
46			`ivH0 : in STD_LOGIC_VECTOR(31 downto 0);`
47			`ivH1 : in STD_LOGIC_VECTOR(31 downto 0);`
48			`ivH2 : in STD_LOGIC_VECTOR(31 downto 0);`
49			`ivH3 : in STD_LOGIC_VECTOR(31 downto 0);`
50			`ivH4 : in STD_LOGIC_VECTOR(31 downto 0);`
51			`ivH5 : in STD_LOGIC_VECTOR(31 downto 0);`
52			`ivH6 : in STD_LOGIC_VECTOR(31 downto 0);`
53			`ivH7 : in STD_LOGIC_VECTOR(31 downto 0);`
54			`ovH0 : out STD_LOGIC_VECTOR(31 downto 0);`
55			`ovH1 : out STD_LOGIC_VECTOR(31 downto 0);`
56			`ovH2 : out STD_LOGIC_VECTOR(31 downto 0);`
57			`ovH3 : out STD_LOGIC_VECTOR(31 downto 0);`
58			`ovH4 : out STD_LOGIC_VECTOR(31 downto 0);`
59			`ovH5 : out STD_LOGIC_VECTOR(31 downto 0);`
60			`ovH6 : out STD_LOGIC_VECTOR(31 downto 0);`
61			`ovH7 : out STD_LOGIC_VECTOR(31 downto 0) );`
62			`end component;`
63
64			`component pipelines_without_reset IS`
65			`GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);`
66			`PORT(`
67			`iClk : IN STD_LOGIC;`
68			`iInput : IN STD_LOGIC;`
69			`ivInput : IN STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);`
70			`oDelayed_output : OUT STD_LOGIC;`
71			`ovDelayed_output : OUT STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)`
72			`);`
73			`end component;`
74
75			`-- Stimulus signals - signals mapped to the input and inout ports of tested entity`
76			`signal iClkReg : STD_LOGIC := '1';`
77			`signal iClkProcess : STD_LOGIC := '1';`
78			`signal iRst_async : STD_LOGIC := '1';`
79			`signal iValid_p : STD_LOGIC := '0';`
80			`signal ivAddr : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');`
81			`signal ivData : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');`
82			`-- Observed signals - signals mapped to the output ports of tested entity`
83			`signal oReachEnd : STD_LOGIC := '0';`
84			`signal oFoundNonce : STD_LOGIC := '0';`
85			`signal ovNonce : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');`
86			`signal ovDigest : tDwordArray(0 to 7) := (others=>(others=>'0'));`
87
88			`-- Add your code here ...`
89			`constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";`
90			`constant cCMD_IDLE : std_logic_vector(15 downto 0) := X"0000";`
91			`constant cCMD_RESET : std_logic_vector(15 downto 0) := X"CAFE";`
92			`constant cCMD_START : std_logic_vector(15 downto 0) := X"0001";`
93
94			`signal svWork : tDwordArray(0 to 31) := (others=>(others=>'0'));`
95
96			`signal siWriteCnt : std_logic_vector(31 downto 0) := (others => '0');`
97
98			`signal sHashMidStateValidIn : std_logic := '0';`
99			`signal sHashMidStateValidOut : std_logic := '0';`
100			`signal svHashMidStateDataOut : tDwordArray(0 to 7) := (others=>(others=>'0'));`
101			`signal svMidState : tDwordArray(0 to 7) := (others=>(others=>'0'));`
102			`signal sMidStateValid : std_logic := '0';`
103
104			`begin`
105
106			`-- Unit Under Test port map`
107			`UUT : btc_dsha`
108			`generic map (`
109			`gBASE_DELAY => gBASE_DELAY`
110			`)`
111
112			`port map (`
113			`iClkReg => iClkReg,`
114			`iClkProcess => iClkProcess,`
115			`iRst_async => iRst_async,`
116			`iValid_p => iValid_p,`
117			`ivAddr => ivAddr,`
118			`ivData => ivData,`
119			`oReachEnd => oReachEnd,`
120			`oFoundNonce => oFoundNonce,`
121			`ovNonce => ovNonce,`
122			`ovDigest => ovDigest`
123			`);`
124
125			`-- Add your stimulus here ...`
126
127			`iClkReg <= not iClkReg after 5 ns;`
128			`iClkProcess <= not iClkProcess after 5 ns;`
129			`iRst_async <= '0' after 71 ns;`
130
131			`svWork(0) <= X"02000000" after 251 ns;`
132			`svWork(1) <= X"ea144059" after 251 ns;`
133			`svWork(2) <= X"2a8b0d36" after 251 ns;`
134			`svWork(3) <= X"b2e5f8a4" after 251 ns;`
135			`svWork(4) <= X"85db1c04" after 251 ns;`
136			`svWork(5) <= X"ca9290ca" after 251 ns;`
137			`svWork(6) <= X"05bdc7f2" after 251 ns;`
138			`svWork(7) <= X"05000000" after 251 ns;`
139			`svWork(8) <= X"00000000" after 251 ns;`
140			`svWork(9) <= X"11dfffb5" after 251 ns;`
141			`svWork(10) <= X"ad285596" after 251 ns;`
142			`svWork(11) <= X"8e4403d0" after 251 ns;`
143			`svWork(12) <= X"60bdf636" after 251 ns;`
144			`svWork(13) <= X"a023e387" after 251 ns;`
145			`svWork(14) <= X"2870bbdc" after 251 ns;`
146			`svWork(15) <= X"92e0aede" after 251 ns;`
147			`svWork(16) <= X"acde4c0e" after 251 ns;`
148			`svWork(17) <= X"032A6C52" after 251 ns;`
149			`svWork(18) <= X"85fc0a19" after 251 ns;`
150			`svWork(19) <= X"0BCFA6B6" after 251 ns;`
151
152
153			`process(iClkReg, iRst_async)`
154			`begin`
155			`if iRst_async = '1' then`
156			`siWriteCnt <= (others => '0');`
157			`iValid_p <= '0';`
158			`elsif rising_edge(iClkReg) then`
159			`if sMidStateValid = '1' then`
160			`siWriteCnt <= siWriteCnt + '1';`
161			`end if;`
162
163			`if siWriteCnt(3 downto 0) = X"F" and siWriteCnt(15 downto 4) <= conv_std_logic_vector(13, 12) then`
164			`iValid_p <= '1';`
165			`else`
166			`iValid_p <= '0';`
167			`end if;`
168			`end if;`
169			`end process;`
170
171			`process(iClkReg, iRst_async)`
172			`begin`
173			`if iRst_async = '1' then`
174			`ivAddr <= (others=>'0');`
175			`ivData <= (others=>'0');`
176			`elsif rising_edge(iClkReg) then`
177			`if siWriteCnt(3 downto 0) = X"F" then`
178			`case siWriteCnt(15 downto 4) is`
179			`when X"000" =>`
180			`ivAddr <= X"0";`
181			`ivData <= svMidState(0);`
182
183			`when X"001" =>`
184			`ivAddr <= X"1";`
185			`ivData <= svMidState(1);`
186
187			`when X"002" =>`
188			`ivAddr <= X"2";`
189			`ivData <= svMidState(2);`
190
191			`when X"003" =>`
192			`ivAddr <= X"3";`
193			`ivData <= svMidState(3);`
194
195			`when X"004" =>`
196			`ivAddr <= X"4";`
197			`ivData <= svMidState(4);`
198
199			`when X"005" =>`
200			`ivAddr <= X"5";`
201			`ivData <= svMidState(5);`
202
203			`when X"006" =>`
204			`ivAddr <= X"6";`
205			`ivData <= svMidState(6);`
206
207			`when X"007" =>`
208			`ivAddr <= X"7";`
209			`ivData <= svMidState(7);`
210
211			`when X"008" =>`
212			`ivAddr <= X"8";`
213			`ivData <= svWork(16);`
214
215			`when X"009" =>`
216			`ivAddr <= X"9";`
217			`ivData <= svWork(17);`
218
219			`when X"00A" =>`
220			`ivAddr <= X"A";`
221			`ivData <= svWork(18);`
222
223			`when X"00B" =>`
224			`ivAddr <= X"B";`
225			`ivData <= svWork(19) - X"20";`
226
227			`when X"00C" =>`
228			`ivAddr <= X"C";`
229			`ivData <= svWork(19); -- + X"02";`
230
231			`when X"00D" =>`
232			`ivAddr <= cCMD_ADDR;`
233			`ivData <= X"0000" & cCMD_START;`
234
235			`when others =>`
236			`ivAddr <= cCMD_ADDR;`
237			`ivData <= X"0000" & cCMD_IDLE;`
238			`end case;`
239			`end if;`
240			`end if;`
241			`end process;`
242
243
244			`sHashMidStateValidIn <= '1' after 251 ns, '0' after 261 ns;`
245
246			`sha_256_chunk_inst_HashMidState : sha_256_chunk`
247			`generic map(`
248			`gMSG_IS_CONSTANT => (others=>'0'),`
249			`gH_IS_CONST => (others=>'1'),`
250			`gBASE_DELAY => gBASE_DELAY`
251			`)`
252			`port map (`
253			`iClk => iClkProcess,`
254			`iRst_async => iRst_async,`
255			`iValid => sHashMidStateValidIn,`
256
257			`ivMsgDword => svWork(0 to 15),`
258
259			`ivH0 => X"6a09e667",`
260			`ivH1 => X"bb67ae85",`
261			`ivH2 => X"3c6ef372",`
262			`ivH3 => X"a54ff53a",`
263			`ivH4 => X"510e527f",`
264			`ivH5 => X"9b05688c",`
265			`ivH6 => X"1f83d9ab",`
266			`ivH7 => X"5be0cd19",`
267
268			`ovH0 => svHashMidStateDataOut(0),`
269			`ovH1 => svHashMidStateDataOut(1),`
270			`ovH2 => svHashMidStateDataOut(2),`
271			`ovH3 => svHashMidStateDataOut(3),`
272			`ovH4 => svHashMidStateDataOut(4),`
273			`ovH5 => svHashMidStateDataOut(5),`
274			`ovH6 => svHashMidStateDataOut(6),`
275			`ovH7 => svHashMidStateDataOut(7)`
276			`);`
277
278			`pipelines_without_reset_Valid : pipelines_without_reset`
279			`GENERIC map(gBUS_WIDTH => 1, gNB_PIPELINES => (64 * gBASE_DELAY + 1))`
280			`PORT map(`
281			`iClk => iClkProcess,`
282			`iInput => sHashMidStateValidIn,`
283			`ivInput => (others=>'0'),`
284			`oDelayed_output => sHashMidStateValidOut,`
285			`ovDelayed_output => open`
286			`);`
287
288			`process(iClkProcess)`
289			`begin`
290			`if rising_edge(iClkProcess) then`
291			`if sHashMidStateValidOut = '1' then`
292			`svMidState <= svHashMidStateDataOut;`
293			`sMidStateValid <= '1';`
294			`end if;`
295			`end if;`
296			`end process;`
297
298			`end TB_ARCHITECTURE;`
299
300			`configuration TESTBENCH_FOR_btc_dsha of btc_dsha_tb is`
301			`for TB_ARCHITECTURE`
302			`for UUT : btc_dsha`
303			`use entity work.btc_dsha(behavioral);`
304			`end for;`
305			`end for;`
306			`end TESTBENCH_FOR_btc_dsha;`
307