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nuxi1209 |
-------------------------------------------------------------------
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-- --
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-- Copyright (C) 2013 Author and VariStream Studio --
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-- Author : Yu Peng --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- This source file is free software; you can redistribute it --
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-- and/or modify it under the terms of the GNU Lesser General --
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-- Public License as published by the Free Software Foundation; --
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-- either version 2.1 of the License, or (at your option) any --
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-- later version. --
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-- --
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-- This source is distributed in the hope that it will be --
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-- useful, but WITHOUT ANY WARRANTY; without even the implied --
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
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-- PURPOSE. See the GNU Lesser General Public License for more --
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-- details. --
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-- --
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-- You should have received a copy of the GNU Lesser General --
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-- Public License along with this source; if not, download it --
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-- from http://www.opencores.org/lgpl.shtml --
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-- --
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-------------------------------------------------------------------
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6 |
nuxi1209 |
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2 |
nuxi1209 |
library ieee;
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use ieee.NUMERIC_STD.all;
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use ieee.STD_LOGIC_UNSIGNED.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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6 |
nuxi1209 |
use work.sha_256_pkg.all;
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2 |
nuxi1209 |
-- Add your library and packages declaration here ...
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entity btc_dsha_tb is
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-- Generic declarations of the tested unit
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generic(
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gBASE_DELAY : INTEGER := 1 );
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end btc_dsha_tb;
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architecture TB_ARCHITECTURE of btc_dsha_tb is
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-- Component declaration of the tested unit
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component btc_dsha
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generic(
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gBASE_DELAY : INTEGER := 1 );
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port(
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iClkReg : in STD_LOGIC;
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iClkProcess : in STD_LOGIC;
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iRst_async : in STD_LOGIC;
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iValid_p : in STD_LOGIC;
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ivAddr : in STD_LOGIC_VECTOR(3 downto 0);
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ivData : in STD_LOGIC_VECTOR(31 downto 0);
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3 |
nuxi1209 |
oReachEnd_p : out STD_LOGIC;
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oFoundNonce_p : out STD_LOGIC;
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2 |
nuxi1209 |
ovNonce : out STD_LOGIC_VECTOR(31 downto 0);
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ovDigest : out tDwordArray(0 to 7) );
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end component;
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component sha_256_chunk
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generic(
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gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
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gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');
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3 |
nuxi1209 |
gBASE_DELAY : integer := 3;
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gOUT_VALID_GEN : boolean := false;
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gUSE_BRAM_AS_LARGE_SHIFTREG : boolean := false
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2 |
nuxi1209 |
);
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port(
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iClk : in STD_LOGIC;
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iRst_async : in STD_LOGIC;
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iValid : in STD_LOGIC;
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ivMsgDword : in tDwordArray(0 to 15);
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ivH0 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH1 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH2 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH3 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH4 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH5 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH6 : in STD_LOGIC_VECTOR(31 downto 0);
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ivH7 : in STD_LOGIC_VECTOR(31 downto 0);
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ovH0 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH1 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH2 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH3 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH4 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH5 : out STD_LOGIC_VECTOR(31 downto 0);
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ovH6 : out STD_LOGIC_VECTOR(31 downto 0);
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3 |
nuxi1209 |
ovH7 : out STD_LOGIC_VECTOR(31 downto 0);
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oValid : out std_logic);
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2 |
nuxi1209 |
end component;
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component pipelines_without_reset IS
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GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);
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PORT(
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iClk : IN STD_LOGIC;
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iInput : IN STD_LOGIC;
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ivInput : IN STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);
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oDelayed_output : OUT STD_LOGIC;
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ovDelayed_output : OUT STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)
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);
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end component;
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-- Stimulus signals - signals mapped to the input and inout ports of tested entity
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signal iClkReg : STD_LOGIC := '1';
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signal iClkProcess : STD_LOGIC := '1';
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signal iRst_async : STD_LOGIC := '1';
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signal iValid_p : STD_LOGIC := '0';
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signal ivAddr : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
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signal ivData : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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-- Observed signals - signals mapped to the output ports of tested entity
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nuxi1209 |
signal oReachEnd_p : STD_LOGIC := '0';
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signal oFoundNonce_p : STD_LOGIC := '0';
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2 |
nuxi1209 |
signal ovNonce : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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signal ovDigest : tDwordArray(0 to 7) := (others=>(others=>'0'));
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-- Add your code here ...
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5 |
nuxi1209 |
constant cREG_CLK_PERIOD : time := 10 ns; -- 100M Register Clock
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constant cPROC_CLK_PERIOD : time := 5 ns; -- 200M Processing Clock
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3 |
nuxi1209 |
constant cRESET_INTERVAL : time := 71 ns;
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constant cSTRAT_TEST : integer := 25;
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nuxi1209 |
constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
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3 |
nuxi1209 |
constant cCMD_NOP : std_logic_vector(15 downto 0) := X"0000";
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2 |
nuxi1209 |
constant cCMD_START : std_logic_vector(15 downto 0) := X"0001";
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signal svWork : tDwordArray(0 to 31) := (others=>(others=>'0'));
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nuxi1209 |
signal svWriteCnt : std_logic_vector(31 downto 0) := (others => '0');
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2 |
nuxi1209 |
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signal sHashMidStateValidIn : std_logic := '0';
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signal sHashMidStateValidOut : std_logic := '0';
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signal svHashMidStateDataOut : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal svMidState : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal sMidStateValid : std_logic := '0';
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begin
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-- Unit Under Test port map
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UUT : btc_dsha
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generic map (
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gBASE_DELAY => gBASE_DELAY
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)
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port map (
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iClkReg => iClkReg,
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iClkProcess => iClkProcess,
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iRst_async => iRst_async,
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iValid_p => iValid_p,
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ivAddr => ivAddr,
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ivData => ivData,
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3 |
nuxi1209 |
oReachEnd_p => oReachEnd_p,
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oFoundNonce_p => oFoundNonce_p,
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2 |
nuxi1209 |
ovNonce => ovNonce,
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ovDigest => ovDigest
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);
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-- Add your stimulus here ...
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3 |
nuxi1209 |
iClkReg <= not iClkReg after (cREG_CLK_PERIOD / 2);
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iClkProcess <= not iClkProcess after (cPROC_CLK_PERIOD / 2);
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iRst_async <= '0' after cRESET_INTERVAL;
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2 |
nuxi1209 |
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3 |
nuxi1209 |
-- This test vector is derive from block 266243, notice the endianess changment of converting JSON data to test vector
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-- blockId: 266243
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-- blockHash: 000000000000000399572203a6035acb2d68944c9c047435a5e9f11d40daa4ee
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-- merkleroot: 0e4cdeacdeaee092dcbb702887e323a036f6bd60d003448e965528adb5ffdf11
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-- nonce: 3064385291
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-- previousblockhash: 0000000000000005f2c7bd05ca9092ca041cdb85a4f8e5b2360d8b2a594014ea
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-- hash: 000000000000000399572203a6035acb2d68944c9c047435a5e9f11d40daa4ee
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-- version: 2
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-- height: 266243
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-- difficulty: 390928787.63808584
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-- confirmations: 1
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-- time: 1382820355
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-- bits: 190afc85
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-- size: 227682
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svWork(0) <= X"02000000" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(1) <= X"ea144059" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(2) <= X"2a8b0d36" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(3) <= X"b2e5f8a4" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(4) <= X"85db1c04" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(5) <= X"ca9290ca" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(6) <= X"05bdc7f2" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(7) <= X"05000000" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(8) <= X"00000000" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(9) <= X"11dfffb5" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(10) <= X"ad285596" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(11) <= X"8e4403d0" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(12) <= X"60bdf636" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(13) <= X"a023e387" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(14) <= X"2870bbdc" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(15) <= X"92e0aede" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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2 |
nuxi1209 |
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198 |
3 |
nuxi1209 |
svWork(16) <= X"acde4c0e" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(17) <= X"032A6C52" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(18) <= X"85fc0a19" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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svWork(19) <= X"0BCFA6B6" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns);
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2 |
nuxi1209 |
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process(iClkReg, iRst_async)
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begin
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if iRst_async = '1' then
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3 |
nuxi1209 |
svWriteCnt <= (others => '0');
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2 |
nuxi1209 |
iValid_p <= '0';
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elsif rising_edge(iClkReg) then
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210 |
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if sMidStateValid = '1' then
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211 |
3 |
nuxi1209 |
svWriteCnt <= svWriteCnt + '1';
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2 |
nuxi1209 |
end if;
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214 |
5 |
nuxi1209 |
if svWriteCnt(1 downto 0) = "11" and svWriteCnt(13 downto 2) <= conv_std_logic_vector(13, 12) then
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215 |
2 |
nuxi1209 |
iValid_p <= '1';
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216 |
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else
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iValid_p <= '0';
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end if;
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end if;
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end process;
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process(iClkReg, iRst_async)
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begin
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224 |
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if iRst_async = '1' then
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ivAddr <= (others=>'0');
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ivData <= (others=>'0');
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227 |
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elsif rising_edge(iClkReg) then
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228 |
5 |
nuxi1209 |
if svWriteCnt(1 downto 0) = "11" then
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229 |
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case svWriteCnt(13 downto 2) is
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230 |
2 |
nuxi1209 |
when X"000" =>
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ivAddr <= X"0";
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ivData <= svMidState(0);
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when X"001" =>
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ivAddr <= X"1";
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ivData <= svMidState(1);
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238 |
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when X"002" =>
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ivAddr <= X"2";
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ivData <= svMidState(2);
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241 |
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when X"003" =>
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ivAddr <= X"3";
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ivData <= svMidState(3);
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245 |
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246 |
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when X"004" =>
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247 |
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ivAddr <= X"4";
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248 |
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ivData <= svMidState(4);
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249 |
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250 |
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when X"005" =>
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251 |
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ivAddr <= X"5";
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252 |
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ivData <= svMidState(5);
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253 |
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254 |
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when X"006" =>
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255 |
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ivAddr <= X"6";
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256 |
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ivData <= svMidState(6);
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257 |
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258 |
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when X"007" =>
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259 |
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ivAddr <= X"7";
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260 |
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ivData <= svMidState(7);
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261 |
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262 |
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when X"008" =>
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263 |
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ivAddr <= X"8";
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264 |
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ivData <= svWork(16);
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265 |
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266 |
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when X"009" =>
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267 |
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ivAddr <= X"9";
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268 |
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ivData <= svWork(17);
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269 |
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270 |
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when X"00A" =>
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271 |
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ivAddr <= X"A";
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272 |
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ivData <= svWork(18);
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273 |
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274 |
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when X"00B" =>
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275 |
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ivAddr <= X"B";
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276 |
5 |
nuxi1209 |
ivData <= svWork(19) - X"02";
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277 |
2 |
nuxi1209 |
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278 |
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when X"00C" =>
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279 |
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ivAddr <= X"C";
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280 |
5 |
nuxi1209 |
ivData <= svWork(19) + X"02";
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281 |
2 |
nuxi1209 |
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282 |
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when X"00D" =>
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283 |
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ivAddr <= cCMD_ADDR;
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284 |
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ivData <= X"0000" & cCMD_START;
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285 |
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286 |
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when others =>
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287 |
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ivAddr <= cCMD_ADDR;
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288 |
3 |
nuxi1209 |
ivData <= X"0000" & cCMD_NOP;
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289 |
2 |
nuxi1209 |
end case;
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290 |
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end if;
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291 |
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end if;
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292 |
|
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end process;
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293 |
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294 |
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295 |
3 |
nuxi1209 |
sHashMidStateValidIn <= '1' after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns), '0' after (cSTRAT_TEST * cPROC_CLK_PERIOD + cPROC_CLK_PERIOD + 1 ns);
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296 |
2 |
nuxi1209 |
|
297 |
|
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sha_256_chunk_inst_HashMidState : sha_256_chunk
|
298 |
|
|
generic map(
|
299 |
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gMSG_IS_CONSTANT => (others=>'0'),
|
300 |
|
|
gH_IS_CONST => (others=>'1'),
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301 |
3 |
nuxi1209 |
gBASE_DELAY => gBASE_DELAY,
|
302 |
|
|
gOUT_VALID_GEN => true
|
303 |
2 |
nuxi1209 |
)
|
304 |
|
|
port map (
|
305 |
|
|
iClk => iClkProcess,
|
306 |
|
|
iRst_async => iRst_async,
|
307 |
|
|
iValid => sHashMidStateValidIn,
|
308 |
|
|
|
309 |
|
|
ivMsgDword => svWork(0 to 15),
|
310 |
|
|
|
311 |
|
|
ivH0 => X"6a09e667",
|
312 |
|
|
ivH1 => X"bb67ae85",
|
313 |
|
|
ivH2 => X"3c6ef372",
|
314 |
|
|
ivH3 => X"a54ff53a",
|
315 |
|
|
ivH4 => X"510e527f",
|
316 |
|
|
ivH5 => X"9b05688c",
|
317 |
|
|
ivH6 => X"1f83d9ab",
|
318 |
|
|
ivH7 => X"5be0cd19",
|
319 |
|
|
|
320 |
|
|
ovH0 => svHashMidStateDataOut(0),
|
321 |
|
|
ovH1 => svHashMidStateDataOut(1),
|
322 |
|
|
ovH2 => svHashMidStateDataOut(2),
|
323 |
|
|
ovH3 => svHashMidStateDataOut(3),
|
324 |
|
|
ovH4 => svHashMidStateDataOut(4),
|
325 |
|
|
ovH5 => svHashMidStateDataOut(5),
|
326 |
|
|
ovH6 => svHashMidStateDataOut(6),
|
327 |
3 |
nuxi1209 |
ovH7 => svHashMidStateDataOut(7),
|
328 |
|
|
|
329 |
|
|
oValid => sHashMidStateValidOut
|
330 |
2 |
nuxi1209 |
);
|
331 |
|
|
|
332 |
3 |
nuxi1209 |
-- pipelines_without_reset_Valid : pipelines_without_reset
|
333 |
|
|
-- GENERIC map(gBUS_WIDTH => 1, gNB_PIPELINES => (64 * gBASE_DELAY + 1))
|
334 |
|
|
-- PORT map(
|
335 |
|
|
-- iClk => iClkProcess,
|
336 |
|
|
-- iInput => sHashMidStateValidIn,
|
337 |
|
|
-- ivInput => (others=>'0'),
|
338 |
|
|
-- oDelayed_output => sHashMidStateValidOut,
|
339 |
|
|
-- ovDelayed_output => open
|
340 |
|
|
-- );
|
341 |
2 |
nuxi1209 |
|
342 |
|
|
process(iClkProcess)
|
343 |
|
|
begin
|
344 |
|
|
if rising_edge(iClkProcess) then
|
345 |
|
|
if sHashMidStateValidOut = '1' then
|
346 |
|
|
svMidState <= svHashMidStateDataOut;
|
347 |
|
|
sMidStateValid <= '1';
|
348 |
|
|
end if;
|
349 |
|
|
end if;
|
350 |
|
|
end process;
|
351 |
|
|
|
352 |
|
|
end TB_ARCHITECTURE;
|
353 |
|
|
|
354 |
|
|
configuration TESTBENCH_FOR_btc_dsha of btc_dsha_tb is
|
355 |
|
|
for TB_ARCHITECTURE
|
356 |
|
|
for UUT : btc_dsha
|
357 |
|
|
use entity work.btc_dsha(behavioral);
|
358 |
|
|
end for;
|
359 |
|
|
end for;
|
360 |
|
|
end TESTBENCH_FOR_btc_dsha;
|
361 |
|
|
|