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[/] [btc_dsha256/] [trunk/] [rtl/] [vhdl/] [TestBench/] [sha_256_chunk_TB.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 nuxi1209 
library hotan;
2 
use hotan.sha_256_pkg.all;
3 
library ieee;
4 
use ieee.NUMERIC_STD.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.NUMERIC_STD.ALL;
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9 
        -- Add your library and packages declaration here ...
10 
 
11 
entity sha_256_chunk_tb is
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end sha_256_chunk_tb;
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architecture TB_ARCHITECTURE of sha_256_chunk_tb is
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        -- Component declaration of the tested unit
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        component sha_256_chunk
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        generic(
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                gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
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                gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');
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                gBASE_DELAY : integer := 3;
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                gOUT_VALID_GEN : boolean := false;
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                gUSE_BRAM_AS_LARGE_SHIFTREG : boolean := false
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        );
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        port(
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                iClk : in STD_LOGIC;
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                iRst_async : in STD_LOGIC;
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                iValid : in STD_LOGIC;
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                ivMsgDword : in tDwordArray(0 to 15);
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                ivH0 : in STD_LOGIC_VECTOR(31 downto 0);
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                ivH1 : in STD_LOGIC_VECTOR(31 downto 0);
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                ivH2 : in STD_LOGIC_VECTOR(31 downto 0);
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                ivH3 : in STD_LOGIC_VECTOR(31 downto 0);
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                ivH4 : in STD_LOGIC_VECTOR(31 downto 0);
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                ivH5 : in STD_LOGIC_VECTOR(31 downto 0);
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                ivH6 : in STD_LOGIC_VECTOR(31 downto 0);
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                ivH7 : in STD_LOGIC_VECTOR(31 downto 0);
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                ovH0 : out STD_LOGIC_VECTOR(31 downto 0);
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                ovH1 : out STD_LOGIC_VECTOR(31 downto 0);
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                ovH2 : out STD_LOGIC_VECTOR(31 downto 0);
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                ovH3 : out STD_LOGIC_VECTOR(31 downto 0);
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                ovH4 : out STD_LOGIC_VECTOR(31 downto 0);
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                ovH5 : out STD_LOGIC_VECTOR(31 downto 0);
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                ovH6 : out STD_LOGIC_VECTOR(31 downto 0);
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                ovH7 : out STD_LOGIC_VECTOR(31 downto 0);
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                oValid : out std_logic);
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        end component;
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48 
        -- Stimulus signals - signals mapped to the input and inout ports of tested entity
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        signal iClk : STD_LOGIC := '1';
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        signal iRst_async : STD_LOGIC := '1';
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        signal iValid : STD_LOGIC := '0';
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        signal ivMsgDword : tDwordArray(0 to 15) := (others=>(others=>'0'));
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        signal ivH0 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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        signal ivH1 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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        signal ivH2 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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        signal ivH3 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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        signal ivH4 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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        signal ivH5 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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        signal ivH6 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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        signal ivH7 : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
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        signal oValid : std_logic;
62 
 
63 
        -- Observed signals - signals mapped to the output ports of tested entity
64 
 
65 
        -- Add your code here ...
66 
 
67 
        constant cTEST_NUM : integer := 3;
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        type tTEST_MSG is array(0 to cTEST_NUM - 1) of tDwordArray(0 to 15);
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        type tTEST_RESULT is array(0 to cTEST_NUM - 1) of tDwordArray(0 to 7);
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        -- The test string length must <= 63
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        constant cTEST_STR_00 : string := "";
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        constant cTEST_STR_01 : string := "The quick brown fox jumps over the lazy dog";
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        constant cTEST_STR_02 : string := "The quick brown fox jumps over the lazy dog.";
74 
 
75 
        constant cTEST_MSG : tTEST_MSG := (
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                                                                                conv_str_to_msg(cTEST_STR_00),
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                                                                                conv_str_to_msg(cTEST_STR_01),
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                                                                                conv_str_to_msg(cTEST_STR_02)
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                                                                                );
80 
 
81 
        constant cTEST_RESULT : tTEST_RESULT := (
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                                                                                (X"e3b0c442", X"98fc1c14", X"9afbf4c8", X"996fb924", X"27ae41e4", X"649b934c", X"a495991b", X"7852b855"),
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                                                                                (X"D7A8FBB3", X"07D78094", X"69CA9ABC", X"B0082E4F", X"8D5651E4", X"6D3CDB76", X"2D02D0BF", X"37C9E592"),
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                                                                                (X"EF537F25", X"C895BFA7", X"82526529", X"A9B63D97", X"AA631564", X"D5D789C2", X"B765448C", X"8635FB6C")
85 
                                                                                );
86 
 
87 
        constant cCLK_PERIOD : time := 10 ns;
88 
        constant cRESET_INTERVAL : time := 71 ns;
89 
        constant cSTRAT_TEST : integer := 19;
90 
 
91 
 
92 
        signal ovH : tDwordArray(0 to 7) := (others=>(others=>'0'));
93 
 
94 
        signal siTestInCnt : integer := 0;
95 
        signal siTestOutCnt : integer := 0;
96 
 
97 
        signal svResultMatch : std_logic_vector(0 to cTEST_NUM - 1) := (others=>'0');
98 
 
99 
begin
100 
 
101 
        -- Unit Under Test port map
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        UUT : sha_256_chunk
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                generic map(
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                        gMSG_IS_CONSTANT => (others=>'0'),
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                        gH_IS_CONST => (others=>'0'),
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                        gBASE_DELAY => 1,
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                        gOUT_VALID_GEN => true
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                )
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                port map (
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                        iClk => iClk,
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                        iRst_async => iRst_async,
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                        iValid => iValid,
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                        ivMsgDword => ivMsgDword,
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                        ivH0 => ivH0,
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                        ivH1 => ivH1,
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                        ivH2 => ivH2,
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                        ivH3 => ivH3,
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                        ivH4 => ivH4,
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                        ivH5 => ivH5,
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                        ivH6 => ivH6,
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                        ivH7 => ivH7,
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                        ovH0 => ovH(0),
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                        ovH1 => ovH(1),
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                        ovH2 => ovH(2),
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                        ovH3 => ovH(3),
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                        ovH4 => ovH(4),
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                        ovH5 => ovH(5),
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                        ovH6 => ovH(6),
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                        ovH7 => ovH(7),
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                        oValid => oValid
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                );
132 
 
133 
        -- Add your stimulus here ...
134 
        iClk <= not iClk after (cCLK_PERIOD / 2);
135 
        iRst_async <= '0' after cRESET_INTERVAL;
136 
 
137 
        iValid <= '1' after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), '0' after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
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        ivH0 <= X"6a09e667" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
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        ivH1 <= X"bb67ae85" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
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        ivH2 <= X"3c6ef372" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
141 
        ivH3 <= X"a54ff53a" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
142 
        ivH4 <= X"510e527f" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
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        ivH5 <= X"9b05688c" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
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        ivH6 <= X"1f83d9ab" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
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        ivH7 <= X"5be0cd19" after (cSTRAT_TEST * cCLK_PERIOD + 1 ns), (others=>'0') after ((cSTRAT_TEST * cCLK_PERIOD + 1 ns) + cTEST_NUM * cCLK_PERIOD);
146 
 
147 
        process(iClk, iRst_async)
148 
        begin
149 
                if iRst_async = '1' then
150 
                        siTestInCnt <= 0;
151 
                        siTestOutCnt <= 0;
152 
                        svResultMatch <= (others=>'0');
153 
                elsif rising_edge(iClk) then
154 
                        if iValid = '1' then
155 
                                siTestInCnt <= siTestInCnt + 1 after 1 ns;
156 
                        end if;
157 
 
158 
                        if oValid = '1' then
159 
                                siTestOutCnt <= siTestOutCnt + 1;
160 
                        end if;
161 
 
162 
                        if oValid = '1' then
163 
                                for i in 0 to cTEST_NUM - 1 loop
164 
                                        if i = siTestOutCnt then
165 
                                                if ovH = cTEST_RESULT(i) then
166 
                                                        svResultMatch(i) <= '1';
167 
                                                else
168 
                                                        svResultMatch(i) <= '0';
169 
                                                end if;
170 
                                        end if;
171 
                                end loop;
172 
                        end if;
173 
                end if;
174 
        end process;
175 
 
176 
        process(iValid, siTestInCnt)
177 
        begin
178 
                if iValid = '0' or siTestInCnt >= cTEST_NUM then
179 
                        ivMsgDword <= (others=>(others=>'0'));
180 
                else
181 
                        ivMsgDword <= cTEST_MSG(siTestInCnt);
182 
                end if;
183 
        end process;
184 
 
185 
end TB_ARCHITECTURE;
186 
 
187 
configuration TESTBENCH_FOR_sha_256_chunk of sha_256_chunk_tb is
188 
        for TB_ARCHITECTURE
189 
                for UUT : sha_256_chunk
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                        use entity work.sha_256_chunk(behavioral);
191 
                end for;
192 
        end for;
193 
end TESTBENCH_FOR_sha_256_chunk;
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