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[/] [btc_dsha256/] [trunk/] [rtl/] [vhdl/] [misc/] [sdpram_infer_read_first_outreg.vhd] - Blame information for rev 3

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1 3 nuxi1209
------------------------------------------------------------------- 
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--                                                               --
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--  Copyright (C) 2013 Author and VariStream Studio              --
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--  Author : Yu Peng                                             --
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--                                                               -- 
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--  This source file may be used and distributed without         -- 
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--  restriction provided that this copyright statement is not    -- 
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--  removed from the file and that any derivative work contains  -- 
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--  the original copyright notice and the associated disclaimer. -- 
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--                                                               -- 
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--  This source file is free software; you can redistribute it   -- 
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--  and/or modify it under the terms of the GNU Lesser General   -- 
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--  Public License as published by the Free Software Foundation; -- 
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--  either version 2.1 of the License, or (at your option) any   -- 
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--  later version.                                               -- 
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--                                                               -- 
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--  This source is distributed in the hope that it will be       -- 
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--  useful, but WITHOUT ANY WARRANTY; without even the implied   -- 
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--  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      -- 
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--  PURPOSE.  See the GNU Lesser General Public License for more -- 
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--  details.                                                     -- 
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--                                                               -- 
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--  You should have received a copy of the GNU Lesser General    -- 
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--  Public License along with this source; if not, download it   -- 
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--  from http://www.opencores.org/lgpl.shtml                     -- 
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--                                                               -- 
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------------------------------------------------------------------- 
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--  Description:
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--      Simple dual-port RAM in read-first mode with output 
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--      register.
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--      This block infers block RAM or distribute RAM according 
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--      to value of gADDRESS_WIDTH and gDATA_WIDTH.
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--  NOTE: 
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--      Reset is on data output ONLY.
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--      This requirement follows the XST User Guide to synthesize
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--      into BRAM.
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-------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity sdpram_infer_read_first_outreg is
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    generic (
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        gADDRESS_WIDTH : integer := 5;
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        gDATA_WIDTH : integer := 24
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        );
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    port (
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        iClk : in std_logic;
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        iReset_sync : in std_logic;
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        iWe : in std_logic;
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        ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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                ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
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        ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);
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        ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)
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        );
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end sdpram_infer_read_first_outreg;
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architecture behavioral of sdpram_infer_read_first_outreg is
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    -- Output register
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    signal svDataOut : std_logic_vector (gDATA_WIDTH-1 downto 0) := (others => '0');
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    -- RAM addressable data array
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    type   tRAM is array (2**gADDRESS_WIDTH-1 downto 0) of std_logic_vector (gDATA_WIDTH-1 downto 0);
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    signal svRAM : tRAM := (others => (others => '0'));
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begin
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    ovDataOut <= svDataOut;
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    process (iClk)
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    begin
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        if iClk'event and iClk = '1' then
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            if iWE = '1' then
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                svRAM(conv_integer(ivWrAddr)) <= ivDataIn;
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            end if;
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                        svDataOut <= svRAM(conv_integer(ivRdAddr));
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        end if;
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    end process;
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end behavioral;

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