1 |
3 |
nuxi1209 |
-------------------------------------------------------------------
|
2 |
|
|
-- --
|
3 |
|
|
-- Copyright (C) 2013 Author and VariStream Studio --
|
4 |
|
|
-- Author : Yu Peng --
|
5 |
|
|
-- --
|
6 |
|
|
-- This source file may be used and distributed without --
|
7 |
|
|
-- restriction provided that this copyright statement is not --
|
8 |
|
|
-- removed from the file and that any derivative work contains --
|
9 |
|
|
-- the original copyright notice and the associated disclaimer. --
|
10 |
|
|
-- --
|
11 |
|
|
-- This source file is free software; you can redistribute it --
|
12 |
|
|
-- and/or modify it under the terms of the GNU Lesser General --
|
13 |
|
|
-- Public License as published by the Free Software Foundation; --
|
14 |
|
|
-- either version 2.1 of the License, or (at your option) any --
|
15 |
|
|
-- later version. --
|
16 |
|
|
-- --
|
17 |
|
|
-- This source is distributed in the hope that it will be --
|
18 |
|
|
-- useful, but WITHOUT ANY WARRANTY; without even the implied --
|
19 |
|
|
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
|
20 |
|
|
-- PURPOSE. See the GNU Lesser General Public License for more --
|
21 |
|
|
-- details. --
|
22 |
|
|
-- --
|
23 |
|
|
-- You should have received a copy of the GNU Lesser General --
|
24 |
|
|
-- Public License along with this source; if not, download it --
|
25 |
|
|
-- from http://www.opencores.org/lgpl.shtml --
|
26 |
|
|
-- --
|
27 |
|
|
-------------------------------------------------------------------
|
28 |
|
|
-- Description:
|
29 |
|
|
-- Simple dual-port RAM in read-first mode with output
|
30 |
|
|
-- register.
|
31 |
|
|
-- This block infers block RAM or distribute RAM according
|
32 |
|
|
-- to value of gADDRESS_WIDTH and gDATA_WIDTH.
|
33 |
|
|
-- NOTE:
|
34 |
|
|
-- Reset is on data output ONLY.
|
35 |
|
|
-- This requirement follows the XST User Guide to synthesize
|
36 |
|
|
-- into BRAM.
|
37 |
|
|
-------------------------------------------------------------------
|
38 |
2 |
nuxi1209 |
library ieee;
|
39 |
|
|
use ieee.std_logic_1164.all;
|
40 |
|
|
use ieee.std_logic_unsigned.all;
|
41 |
|
|
|
42 |
|
|
entity sdpram_infer_read_first_outreg is
|
43 |
|
|
generic (
|
44 |
|
|
gADDRESS_WIDTH : integer := 5;
|
45 |
|
|
gDATA_WIDTH : integer := 24
|
46 |
|
|
);
|
47 |
|
|
port (
|
48 |
|
|
iClk : in std_logic;
|
49 |
|
|
iReset_sync : in std_logic;
|
50 |
|
|
iWe : in std_logic;
|
51 |
|
|
ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
|
52 |
|
|
ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
|
53 |
|
|
ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);
|
54 |
|
|
ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)
|
55 |
|
|
);
|
56 |
|
|
end sdpram_infer_read_first_outreg;
|
57 |
|
|
|
58 |
|
|
architecture behavioral of sdpram_infer_read_first_outreg is
|
59 |
|
|
-- Output register
|
60 |
|
|
signal svDataOut : std_logic_vector (gDATA_WIDTH-1 downto 0) := (others => '0');
|
61 |
|
|
|
62 |
|
|
-- RAM addressable data array
|
63 |
|
|
type tRAM is array (2**gADDRESS_WIDTH-1 downto 0) of std_logic_vector (gDATA_WIDTH-1 downto 0);
|
64 |
|
|
signal svRAM : tRAM := (others => (others => '0'));
|
65 |
|
|
|
66 |
|
|
begin
|
67 |
|
|
ovDataOut <= svDataOut;
|
68 |
|
|
process (iClk)
|
69 |
|
|
begin
|
70 |
|
|
if iClk'event and iClk = '1' then
|
71 |
|
|
if iWE = '1' then
|
72 |
|
|
svRAM(conv_integer(ivWrAddr)) <= ivDataIn;
|
73 |
|
|
end if;
|
74 |
|
|
|
75 |
|
|
svDataOut <= svRAM(conv_integer(ivRdAddr));
|
76 |
|
|
end if;
|
77 |
|
|
end process;
|
78 |
|
|
end behavioral;
|