URL
https://opencores.org/ocsvn/btc_dsha256/btc_dsha256/trunk
[/] [btc_dsha256/] [trunk/] [rtl/] [vhdl/] [misc/] [sdpram_infer_read_first_outreset.vhd] - Blame information for rev 2
Go to most recent revision |
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
2 |
nuxi1209 |
-------------------------------------------------------------------------------
|
2 |
|
|
-- Copyright (c) 2013 VariStream
|
3 |
|
|
-- Author : Yu Peng
|
4 |
|
|
-- Description:
|
5 |
|
|
-- Simple dual-port RAM in read-first mode with output register reset.
|
6 |
|
|
-- This block infers block RAM or distribute RAM according to value of gADDRESS_WIDTH and gDATA_WIDTH,
|
7 |
|
|
-- NOTE:
|
8 |
|
|
-- Reset is on data output ONLY.
|
9 |
|
|
-- This requirement follows the XST User Guide to synthesize into BRAM.
|
10 |
|
|
-------------------------------------------------------------------------------
|
11 |
|
|
library ieee;
|
12 |
|
|
use ieee.std_logic_1164.all;
|
13 |
|
|
use ieee.std_logic_unsigned.all;
|
14 |
|
|
|
15 |
|
|
entity sdpram_infer_read_first_outreset is
|
16 |
|
|
generic (
|
17 |
|
|
gADDRESS_WIDTH : integer := 5;
|
18 |
|
|
gDATA_WIDTH : integer := 24
|
19 |
|
|
);
|
20 |
|
|
port (
|
21 |
|
|
iClk : in std_logic;
|
22 |
|
|
iReset_sync : in std_logic;
|
23 |
|
|
iWe : in std_logic;
|
24 |
|
|
ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
|
25 |
|
|
ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
|
26 |
|
|
ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);
|
27 |
|
|
ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)
|
28 |
|
|
);
|
29 |
|
|
end sdpram_infer_read_first_outreset;
|
30 |
|
|
|
31 |
|
|
architecture behavioral of sdpram_infer_read_first_outreset is
|
32 |
|
|
-- Output register
|
33 |
|
|
signal svDataOut : std_logic_vector (gDATA_WIDTH-1 downto 0) := (others => '0');
|
34 |
|
|
|
35 |
|
|
-- RAM addressable data array
|
36 |
|
|
type tRAM is array (2**gADDRESS_WIDTH-1 downto 0) of std_logic_vector (gDATA_WIDTH-1 downto 0);
|
37 |
|
|
signal svRAM : tRAM := (others => (others => '0'));
|
38 |
|
|
|
39 |
|
|
begin
|
40 |
|
|
ovDataOut <= svDataOut;
|
41 |
|
|
process (iClk)
|
42 |
|
|
begin
|
43 |
|
|
if iClk'event and iClk = '1' then
|
44 |
|
|
if iWE = '1' then
|
45 |
|
|
svRAM(conv_integer(ivWrAddr)) <= ivDataIn;
|
46 |
|
|
end if;
|
47 |
|
|
|
48 |
|
|
if iReset_sync = '1' then -- Reset only on output port
|
49 |
|
|
svDataOut <= (others => '0');
|
50 |
|
|
else
|
51 |
|
|
svDataOut <= svRAM(conv_integer(ivRdAddr));
|
52 |
|
|
end if;
|
53 |
|
|
end if;
|
54 |
|
|
end process;
|
55 |
|
|
end behavioral;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.