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[/] [btc_dsha256/] [trunk/] [rtl/] [vhdl/] [misc/] [sync_fifo_infer.vhd] - Blame information for rev 2

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---------------------------------------------------------------------------------------------------
-- Copyright (c) 2013 VariStream
-- Author : Yu Peng
-- Description:
--   Implement BRAM according to gADDRESS_WIDTH and gDATA_WIDTH
--   Maxim number of data word is (2**gADDRESS_WIDTH - 1)
---------------------------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--use synplify.attributes.all;
 
entity sync_fifo_infer is
        generic (
                gADDRESS_WIDTH : integer range 4 to (integer'HIGH) := 8;
                gDATA_WIDTH : integer := 32;
                gDYNAMIC_PROG_FULL_TH : boolean := false;
                gDYNAMIC_PROG_EMPTY_TH : boolean := false;
                gOUTPUT_PIPELINE_NUM : integer range 1 to (integer'HIGH) := 1
                );
        port(
                iClk : in std_logic := '0';
                iReset_sync : in std_logic := '0';
 
                ivProgFullTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2**gADDRESS_WIDTH-3, gADDRESS_WIDTH);
                ivProgEmptyTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2, gADDRESS_WIDTH);
 
                iWrEn : in std_logic := '0';
                iRdEn : in std_logic := '0';
                ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
                ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
                oDataOutValid : out std_logic := '0';
 
                oFull : out std_logic := '0';
                oEmpty : out std_logic := '1';
                oAlmostFull : out std_logic := '0';
                oAlmostEmpty : out std_logic := '1';
                oProgFull : out std_logic := '0';
                oProgEmpty : out std_logic := '1';
 
                oOverflow : out std_logic := '0';
                oUnderflow : out std_logic := '0'
        );
end sync_fifo_infer;
 
ARCHITECTURE behavioral OF sync_fifo_infer IS
 
        component sdpram_infer_read_first_outreg is
            generic (
                gADDRESS_WIDTH : integer := 5;
                gDATA_WIDTH : integer := 24
                );
            port (
                iClk : in std_logic;
                iReset_sync : in std_logic;
                iWe : in std_logic;
                ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
                        ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
                ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);
                ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)
                );
        end component;
 
        component sdpram_infer_read_first_outreset is
            generic (
                gADDRESS_WIDTH : integer := 5;
                gDATA_WIDTH : integer := 24
                );
            port (
                iClk : in std_logic;
                iReset_sync : in std_logic;
                iWe : in std_logic;
                ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
                        ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);
                ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);
                ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)
                );
        end component;
 
        component pipelines_without_reset IS
                GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);
                PORT(
                        iClk                            : IN            STD_LOGIC;
                        iInput                          : IN            STD_LOGIC;
                        ivInput                         : IN            STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);
                        oDelayed_output         : OUT           STD_LOGIC;
                        ovDelayed_output        : OUT           STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)
                );
        END component;
 
        signal svWriteAddr : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');
        signal svReadAddr : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');
        signal sEffectiveWrEn : std_logic := '0';
        signal sEffectiveRdEn : std_logic := '0';
        signal svFifoCount : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');
        signal svProgFullThM1 : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2**gADDRESS_WIDTH-4, gADDRESS_WIDTH);
        signal svProgEmptyThP1 : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(3, gADDRESS_WIDTH);
        signal sFifoFull : std_logic := '0';
        signal sFifoEmpty : std_logic := '1';
        signal sAlmostFull : std_logic := '0';
        signal sAlmostEmpty : std_logic := '1';
        signal sProgFull : std_logic := '0';
        signal sProgEmpty : std_logic := '1';
        signal sFifoOverflow : std_logic := '0';
        signal sFifoUnderflow : std_logic := '0';
 
        signal svMemDataOut : std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
        signal sMemDataOutValid : std_logic := '0';
        signal svPipeDataOut : std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
        signal sPipeDataOutValid: std_logic := '0';
 
 
BEGIN
        sdpram_gen_1: if gOUTPUT_PIPELINE_NUM = 1 generate
                sdpram_inst: sdpram_infer_read_first_outreset
                    generic map(
                        gADDRESS_WIDTH => gADDRESS_WIDTH,
                        gDATA_WIDTH => gDATA_WIDTH
                        )
                    port map(
                        iClk => iClk,
                        iReset_sync => iReset_sync,
                        iWe => iWrEn,
                        ivWrAddr => svWriteAddr,
                                ivRdAddr => svReadAddr,
                        ivDataIn => ivDataIn,
                        ovDataOut => svMemDataOut
                        );
 
                process(iClk)
                begin
                        if rising_edge(iClk) then
                                if iReset_sync = '1' then
                                        sMemDataOutValid <= '0';
                                else
                                        sMemDataOutValid <= iRdEn;
                                end if;
                        end if;
                end process;
        end generate;
 
        sdpram_gen_others: if gOUTPUT_PIPELINE_NUM > 1 generate
                sdpram_inst: sdpram_infer_read_first_outreg
                    generic map(
                        gADDRESS_WIDTH => gADDRESS_WIDTH,
                        gDATA_WIDTH => gDATA_WIDTH
                        )
                    port map(
                        iClk => iClk,
                        iReset_sync => iReset_sync,
                        iWe => iWrEn,
                        ivWrAddr => svWriteAddr,
                                ivRdAddr => svReadAddr,
                        ivDataIn => ivDataIn,
                        ovDataOut => svMemDataOut
                        );
 
                process(iClk)
                begin
                        if rising_edge(iClk) then
                                sMemDataOutValid <= iRdEn;
                        end if;
                end process;
        end generate;
 
        -----------------------------------------------------------------------------------------------
        -- Generate the write and read pointers
        -----------------------------------------------------------------------------------------------
        process(iClk)
        begin
                if rising_edge(iClk) then
                        if iReset_sync = '1' then
                                svWriteAddr <= (others=>'0');
                        elsif sEffectiveWrEn = '1' then
                                svWriteAddr <= svWriteAddr + '1';
                        end if;
                end if;
        end process;
 
        process(iClk)
        begin
                if rising_edge(iClk) then
                        if iReset_sync = '1' then
                                svReadAddr <= (others=>'0');
                        elsif sEffectiveRdEn = '1' then
                                svReadAddr <= svReadAddr + '1';
                        end if;
                end if;
        end process;
 
        -----------------------------------------------------------------------------------------------
        -- Generate Fifo Flags
        -----------------------------------------------------------------------------------------------
        sEffectiveWrEn <= iWrEn and (not sFifoFull);
        sEffectiveRdEn <= iRdEn and (not sFifoEmpty);
 
        ProgFullThM1_gen_dynamic : if gDYNAMIC_PROG_FULL_TH = true generate
                process (iClk)
                begin
                        if rising_edge(iClk) then
                                svProgFullThM1 <= ivProgFullTh - '1';
                        end if;
                end process;
        end generate;
 
        ProgFullThM1_gen_static : if gDYNAMIC_PROG_FULL_TH = false generate
                svProgFullThM1 <= ivProgFullTh - '1';
        end generate;
 
        ProgEmptyThM1_gen_dynamic : if gDYNAMIC_PROG_EMPTY_TH = true generate
                process (iClk)
                begin
                        if rising_edge(iClk) then
                                svProgEmptyThP1 <= ivProgEmptyTh + '1';
                        end if;
                end process;
        end generate;
 
        ProgEmptyThM1_gen_static : if gDYNAMIC_PROG_EMPTY_TH = false generate
                svProgEmptyThP1 <= ivProgEmptyTh + '1';
        end generate;
 
        process (iClk)
        begin
                if rising_edge(iClk) then
                        if (iReset_sync = '1') then
                                svFifoCount <= (others => '0');
                                sFifoFull <= '0';
                                sFifoEmpty <= '1';
                                sAlmostFull <= '0';
                                sAlmostEmpty <= '1';
                                sProgFull <= '0';
                                sProgEmpty <= '1';
 
                                sFifoOverflow <= '0';
                                sFifoUnderflow <= '0';
                        else
                                -- Fifo count when it is read or written
                                if (sEffectiveWrEn = '1') and (sEffectiveRdEn = '0') then
                                        svFifoCount <= svFifoCount + '1';
                                elsif (sEffectiveWrEn = '0') and (sEffectiveRdEn = '1') then
                                        svFifoCount <= svFifoCount - '1';
                                end if;
 
                                if svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-2, gADDRESS_WIDTH) then
                                        if (iWrEn = '1') and (iRdEn = '0') then
                                                sFifoFull <= '1';
                                        else
                                                sFifoFull <= '0';
                                        end if;
                                elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-1, gADDRESS_WIDTH) then
                                        if iRdEn = '1' then
                                                sFifoFull <= '0';
                                        else
                                                sFifoFull <= '1';
                                        end if;
                                else
                                        sFifoFull <= '0';
                                end if;
 
                                if svFifoCount = conv_std_logic_vector(1, gADDRESS_WIDTH) then
                                        if (iWrEn = '0') and (iRdEn = '1') then
                                                sFifoEmpty <= '1';
                                        else
                                                sFifoEmpty <= '0';
                                        end if;
                                elsif svFifoCount = conv_std_logic_vector(0, gADDRESS_WIDTH) then
                                        if (iWrEn = '1') then
                                                sFifoEmpty <= '0';
                                        else
                                                sFifoEmpty <= '1';
                                        end if;
                                else
                                        sFifoEmpty <= '0';
                                end if;
 
                                if svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-3, gADDRESS_WIDTH) then
                                        if (iWrEn = '1') and (iRdEn = '0') then
                                                sAlmostFull <= '1';
                                        else
                                                sAlmostFull <= '0';
                                        end if;
                                elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-2, gADDRESS_WIDTH) then
                                        if (iWrEn = '0') and (iRdEn = '1') then
                                                sAlmostFull <= '0';
                                        else
                                                sAlmostFull <= '1';
                                        end if;
                                elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-1, gADDRESS_WIDTH) then
                                        sAlmostFull <= '1';
                                else
                                        sAlmostFull <= '0';
                                end if;
 
                                if svFifoCount = conv_std_logic_vector(2, gADDRESS_WIDTH) then
                                        if (iWrEn = '0') and (iRdEn = '1') then
                                                sAlmostEmpty <= '1';
                                        else
                                                sAlmostEmpty <= '0';
                                        end if;
                                elsif svFifoCount = conv_std_logic_vector(1, gADDRESS_WIDTH) then
                                        if (iWrEn = '1') and (iRdEn = '0') then
                                                sAlmostEmpty <= '0';
                                        else
                                                sAlmostEmpty <= '1';
                                        end if;
                                elsif svFifoCount = conv_std_logic_vector(0, gADDRESS_WIDTH) then
                                        sAlmostEmpty <= '1';
                                else
                                        sAlmostEmpty <= '0';
                                end if;
 
                                if svFifoCount = svProgFullThM1 then
                                        if (iWrEn = '1') and (iRdEn = '0') then
                                                sProgFull <= '1';
                                        else
                                                sProgFull <= '0';
                                        end if;
                                elsif svFifoCount = ivProgFullTh then
                                        if (iWrEn = '0') and (iRdEn = '1') then
                                                sProgFull <= '0';
                                        else
                                                sProgFull <= '1';
                                        end if;
                                elsif svFifoCount > ivProgFullTh then
                                        sProgFull <= '1';
                                else
                                        sProgFull <= '0';
                                end if;
 
                                if svFifoCount = svProgEmptyThP1 then
                                        if (iWrEn = '0') and (iRdEn = '1') then
                                                sProgEmpty <= '1';
                                        else
                                                sProgEmpty <= '0';
                                        end if;
                                elsif svFifoCount = ivProgEmptyTh then
                                        if (iWrEn = '1') and (iRdEn = '0') then
                                                sProgEmpty <= '0';
                                        else
                                                sProgEmpty <= '1';
                                        end if;
                                elsif svFifoCount < ivProgEmptyTh then
                                        sProgEmpty <= '1';
                                else
                                        sProgEmpty <= '0';
                                end if;
                                --------------------------------
                                -- Generate the error flag
                                -------------------------------
                                if sFifoFull = '1' and iWrEn = '1'  then
                                        sFifoOverflow <= '1';
                                end if;
 
                                if sFifoEmpty = '1' and iRdEn = '1'  then
                                        sFifoUnderflow <= '1';
                                end if;
                        end if;
                end if;
        end process;
 
        oFull <= sFifoFull;
        oEmpty <= sFifoEmpty;
        oAlmostFull <= sAlmostFull;
        oAlmostEmpty <= sAlmostEmpty;
        oProgFull <= sProgFull;
        oProgEmpty <= sProgEmpty;
        oOverflow <= sFifoOverflow;
        oUnderflow <= sFifoUnderflow;
 
        -------------------------------------------------------------------------------------
        -- This section generates the code for the output pipelines
        -------------------------------------------------------------------------------------
        OutputPipeline_gen_1: if gOUTPUT_PIPELINE_NUM = 1 generate
                ovDataOut <= svMemDataOut;
                oDataOutValid <= sMemDataOutValid;
        end generate;
 
        OutputPipeline_gen_2: if gOUTPUT_PIPELINE_NUM = 2 generate
                process (iClk)
                begin
                        if rising_edge(iClk) then
                                if (iReset_sync = '1') then
                                        ovDataOut <= (others=>'0');
                                        oDataOutValid <= '0';
                                else
                                        ovDataOut <= svMemDataOut;
                                        oDataOutValid <= sMemDataOutValid;
                                end if;
                        end if;
                end process;
        end generate;
 
        OutputPipeline_gen_others: if gOUTPUT_PIPELINE_NUM > 2 generate
                pipelines_without_reset_inst_output: pipelines_without_reset
                        GENERIC map(
                                gBUS_WIDTH => gDATA_WIDTH,
                                gNB_PIPELINES => (gOUTPUT_PIPELINE_NUM-1)
                        )
                        PORT map(
                                iClk => iClk,
                                iInput => sMemDataOutValid,
                                ivInput => svMemDataOut,
                                oDelayed_output => sPipeDataOutValid,
                                ovDelayed_output => svPipeDataOut
                        );
 
                process (iClk)
                begin
                        if rising_edge(iClk) then
                                if (iReset_sync = '1') then
                                        ovDataOut <= (others=>'0');
                                        oDataOutValid <= '0';
                                else
                                        ovDataOut <= svPipeDataOut;
                                        oDataOutValid <= sPipeDataOutValid;
                                end if;
                        end if;
                end process;
        end generate;
 
END behavioral;
 
 
 

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[/] [btc_dsha256/] [trunk/] [rtl/] [vhdl/] [misc/] [sync_fifo_infer.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	nuxi1209	`---------------------------------------------------------------------------------------------------`
2			`-- Copyright (c) 2013 VariStream`
3			`-- Author : Yu Peng`
4			`-- Description:`
5			`-- Implement BRAM according to gADDRESS_WIDTH and gDATA_WIDTH`
6			`-- Maxim number of data word is (2**gADDRESS_WIDTH - 1)`
7			`---------------------------------------------------------------------------------------------------`
8
9			`LIBRARY ieee;`
10			`USE ieee.std_logic_1164.all;`
11			`USE ieee.std_logic_unsigned.all;`
12			`USE ieee.std_logic_arith.all;`
13			`--use synplify.attributes.all;`
14
15			`entity sync_fifo_infer is`
16			`generic (`
17			`gADDRESS_WIDTH : integer range 4 to (integer'HIGH) := 8;`
18			`gDATA_WIDTH : integer := 32;`
19			`gDYNAMIC_PROG_FULL_TH : boolean := false;`
20			`gDYNAMIC_PROG_EMPTY_TH : boolean := false;`
21			`gOUTPUT_PIPELINE_NUM : integer range 1 to (integer'HIGH) := 1`
22			`);`
23			`port(`
24			`iClk : in std_logic := '0';`
25			`iReset_sync : in std_logic := '0';`
26
27			`ivProgFullTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2**gADDRESS_WIDTH-3, gADDRESS_WIDTH);`
28			`ivProgEmptyTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2, gADDRESS_WIDTH);`
29
30			`iWrEn : in std_logic := '0';`
31			`iRdEn : in std_logic := '0';`
32			`ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');`
33			`ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');`
34			`oDataOutValid : out std_logic := '0';`
35
36			`oFull : out std_logic := '0';`
37			`oEmpty : out std_logic := '1';`
38			`oAlmostFull : out std_logic := '0';`
39			`oAlmostEmpty : out std_logic := '1';`
40			`oProgFull : out std_logic := '0';`
41			`oProgEmpty : out std_logic := '1';`
42
43			`oOverflow : out std_logic := '0';`
44			`oUnderflow : out std_logic := '0'`
45			`);`
46			`end sync_fifo_infer;`
47
48			`ARCHITECTURE behavioral OF sync_fifo_infer IS`
49
50			`component sdpram_infer_read_first_outreg is`
51			`generic (`
52			`gADDRESS_WIDTH : integer := 5;`
53			`gDATA_WIDTH : integer := 24`
54			`);`
55			`port (`
56			`iClk : in std_logic;`
57			`iReset_sync : in std_logic;`
58			`iWe : in std_logic;`
59			`ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);`
60			`ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);`
61			`ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);`
62			`ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)`
63			`);`
64			`end component;`
65
66			`component sdpram_infer_read_first_outreset is`
67			`generic (`
68			`gADDRESS_WIDTH : integer := 5;`
69			`gDATA_WIDTH : integer := 24`
70			`);`
71			`port (`
72			`iClk : in std_logic;`
73			`iReset_sync : in std_logic;`
74			`iWe : in std_logic;`
75			`ivWrAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);`
76			`ivRdAddr : in std_logic_vector(gADDRESS_WIDTH-1 downto 0);`
77			`ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0);`
78			`ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0)`
79			`);`
80			`end component;`
81
82			`component pipelines_without_reset IS`
83			`GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);`
84			`PORT(`
85			`iClk : IN STD_LOGIC;`
86			`iInput : IN STD_LOGIC;`
87			`ivInput : IN STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);`
88			`oDelayed_output : OUT STD_LOGIC;`
89			`ovDelayed_output : OUT STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)`
90			`);`
91			`END component;`
92
93			`signal svWriteAddr : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');`
94			`signal svReadAddr : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');`
95			`signal sEffectiveWrEn : std_logic := '0';`
96			`signal sEffectiveRdEn : std_logic := '0';`
97			`signal svFifoCount : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := (others=>'0');`
98			`signal svProgFullThM1 : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2**gADDRESS_WIDTH-4, gADDRESS_WIDTH);`
99			`signal svProgEmptyThP1 : std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(3, gADDRESS_WIDTH);`
100			`signal sFifoFull : std_logic := '0';`
101			`signal sFifoEmpty : std_logic := '1';`
102			`signal sAlmostFull : std_logic := '0';`
103			`signal sAlmostEmpty : std_logic := '1';`
104			`signal sProgFull : std_logic := '0';`
105			`signal sProgEmpty : std_logic := '1';`
106			`signal sFifoOverflow : std_logic := '0';`
107			`signal sFifoUnderflow : std_logic := '0';`
108
109			`signal svMemDataOut : std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');`
110			`signal sMemDataOutValid : std_logic := '0';`
111			`signal svPipeDataOut : std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');`
112			`signal sPipeDataOutValid: std_logic := '0';`
113
114
115			`BEGIN`
116			`sdpram_gen_1: if gOUTPUT_PIPELINE_NUM = 1 generate`
117			`sdpram_inst: sdpram_infer_read_first_outreset`
118			`generic map(`
119			`gADDRESS_WIDTH => gADDRESS_WIDTH,`
120			`gDATA_WIDTH => gDATA_WIDTH`
121			`)`
122			`port map(`
123			`iClk => iClk,`
124			`iReset_sync => iReset_sync,`
125			`iWe => iWrEn,`
126			`ivWrAddr => svWriteAddr,`
127			`ivRdAddr => svReadAddr,`
128			`ivDataIn => ivDataIn,`
129			`ovDataOut => svMemDataOut`
130			`);`
131
132			`process(iClk)`
133			`begin`
134			`if rising_edge(iClk) then`
135			`if iReset_sync = '1' then`
136			`sMemDataOutValid <= '0';`
137			`else`
138			`sMemDataOutValid <= iRdEn;`
139			`end if;`
140			`end if;`
141			`end process;`
142			`end generate;`
143
144			`sdpram_gen_others: if gOUTPUT_PIPELINE_NUM > 1 generate`
145			`sdpram_inst: sdpram_infer_read_first_outreg`
146			`generic map(`
147			`gADDRESS_WIDTH => gADDRESS_WIDTH,`
148			`gDATA_WIDTH => gDATA_WIDTH`
149			`)`
150			`port map(`
151			`iClk => iClk,`
152			`iReset_sync => iReset_sync,`
153			`iWe => iWrEn,`
154			`ivWrAddr => svWriteAddr,`
155			`ivRdAddr => svReadAddr,`
156			`ivDataIn => ivDataIn,`
157			`ovDataOut => svMemDataOut`
158			`);`
159
160			`process(iClk)`
161			`begin`
162			`if rising_edge(iClk) then`
163			`sMemDataOutValid <= iRdEn;`
164			`end if;`
165			`end process;`
166			`end generate;`
167
168			`-----------------------------------------------------------------------------------------------`
169			`-- Generate the write and read pointers`
170			`-----------------------------------------------------------------------------------------------`
171			`process(iClk)`
172			`begin`
173			`if rising_edge(iClk) then`
174			`if iReset_sync = '1' then`
175			`svWriteAddr <= (others=>'0');`
176			`elsif sEffectiveWrEn = '1' then`
177			`svWriteAddr <= svWriteAddr + '1';`
178			`end if;`
179			`end if;`
180			`end process;`
181
182			`process(iClk)`
183			`begin`
184			`if rising_edge(iClk) then`
185			`if iReset_sync = '1' then`
186			`svReadAddr <= (others=>'0');`
187			`elsif sEffectiveRdEn = '1' then`
188			`svReadAddr <= svReadAddr + '1';`
189			`end if;`
190			`end if;`
191			`end process;`
192
193			`-----------------------------------------------------------------------------------------------`
194			`-- Generate Fifo Flags`
195			`-----------------------------------------------------------------------------------------------`
196			`sEffectiveWrEn <= iWrEn and (not sFifoFull);`
197			`sEffectiveRdEn <= iRdEn and (not sFifoEmpty);`
198
199			`ProgFullThM1_gen_dynamic : if gDYNAMIC_PROG_FULL_TH = true generate`
200			`process (iClk)`
201			`begin`
202			`if rising_edge(iClk) then`
203			`svProgFullThM1 <= ivProgFullTh - '1';`
204			`end if;`
205			`end process;`
206			`end generate;`
207
208			`ProgFullThM1_gen_static : if gDYNAMIC_PROG_FULL_TH = false generate`
209			`svProgFullThM1 <= ivProgFullTh - '1';`
210			`end generate;`
211
212			`ProgEmptyThM1_gen_dynamic : if gDYNAMIC_PROG_EMPTY_TH = true generate`
213			`process (iClk)`
214			`begin`
215			`if rising_edge(iClk) then`
216			`svProgEmptyThP1 <= ivProgEmptyTh + '1';`
217			`end if;`
218			`end process;`
219			`end generate;`
220
221			`ProgEmptyThM1_gen_static : if gDYNAMIC_PROG_EMPTY_TH = false generate`
222			`svProgEmptyThP1 <= ivProgEmptyTh + '1';`
223			`end generate;`
224
225			`process (iClk)`
226			`begin`
227			`if rising_edge(iClk) then`
228			`if (iReset_sync = '1') then`
229			`svFifoCount <= (others => '0');`
230			`sFifoFull <= '0';`
231			`sFifoEmpty <= '1';`
232			`sAlmostFull <= '0';`
233			`sAlmostEmpty <= '1';`
234			`sProgFull <= '0';`
235			`sProgEmpty <= '1';`
236
237			`sFifoOverflow <= '0';`
238			`sFifoUnderflow <= '0';`
239			`else`
240			`-- Fifo count when it is read or written`
241			`if (sEffectiveWrEn = '1') and (sEffectiveRdEn = '0') then`
242			`svFifoCount <= svFifoCount + '1';`
243			`elsif (sEffectiveWrEn = '0') and (sEffectiveRdEn = '1') then`
244			`svFifoCount <= svFifoCount - '1';`
245			`end if;`
246
247			`if svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-2, gADDRESS_WIDTH) then`
248			`if (iWrEn = '1') and (iRdEn = '0') then`
249			`sFifoFull <= '1';`
250			`else`
251			`sFifoFull <= '0';`
252			`end if;`
253			`elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-1, gADDRESS_WIDTH) then`
254			`if iRdEn = '1' then`
255			`sFifoFull <= '0';`
256			`else`
257			`sFifoFull <= '1';`
258			`end if;`
259			`else`
260			`sFifoFull <= '0';`
261			`end if;`
262
263			`if svFifoCount = conv_std_logic_vector(1, gADDRESS_WIDTH) then`
264			`if (iWrEn = '0') and (iRdEn = '1') then`
265			`sFifoEmpty <= '1';`
266			`else`
267			`sFifoEmpty <= '0';`
268			`end if;`
269			`elsif svFifoCount = conv_std_logic_vector(0, gADDRESS_WIDTH) then`
270			`if (iWrEn = '1') then`
271			`sFifoEmpty <= '0';`
272			`else`
273			`sFifoEmpty <= '1';`
274			`end if;`
275			`else`
276			`sFifoEmpty <= '0';`
277			`end if;`
278
279			`if svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-3, gADDRESS_WIDTH) then`
280			`if (iWrEn = '1') and (iRdEn = '0') then`
281			`sAlmostFull <= '1';`
282			`else`
283			`sAlmostFull <= '0';`
284			`end if;`
285			`elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-2, gADDRESS_WIDTH) then`
286			`if (iWrEn = '0') and (iRdEn = '1') then`
287			`sAlmostFull <= '0';`
288			`else`
289			`sAlmostFull <= '1';`
290			`end if;`
291			`elsif svFifoCount = conv_std_logic_vector((2**gADDRESS_WIDTH)-1, gADDRESS_WIDTH) then`
292			`sAlmostFull <= '1';`
293			`else`
294			`sAlmostFull <= '0';`
295			`end if;`
296
297			`if svFifoCount = conv_std_logic_vector(2, gADDRESS_WIDTH) then`
298			`if (iWrEn = '0') and (iRdEn = '1') then`
299			`sAlmostEmpty <= '1';`
300			`else`
301			`sAlmostEmpty <= '0';`
302			`end if;`
303			`elsif svFifoCount = conv_std_logic_vector(1, gADDRESS_WIDTH) then`
304			`if (iWrEn = '1') and (iRdEn = '0') then`
305			`sAlmostEmpty <= '0';`
306			`else`
307			`sAlmostEmpty <= '1';`
308			`end if;`
309			`elsif svFifoCount = conv_std_logic_vector(0, gADDRESS_WIDTH) then`
310			`sAlmostEmpty <= '1';`
311			`else`
312			`sAlmostEmpty <= '0';`
313			`end if;`
314
315			`if svFifoCount = svProgFullThM1 then`
316			`if (iWrEn = '1') and (iRdEn = '0') then`
317			`sProgFull <= '1';`
318			`else`
319			`sProgFull <= '0';`
320			`end if;`
321			`elsif svFifoCount = ivProgFullTh then`
322			`if (iWrEn = '0') and (iRdEn = '1') then`
323			`sProgFull <= '0';`
324			`else`
325			`sProgFull <= '1';`
326			`end if;`
327			`elsif svFifoCount > ivProgFullTh then`
328			`sProgFull <= '1';`
329			`else`
330			`sProgFull <= '0';`
331			`end if;`
332
333			`if svFifoCount = svProgEmptyThP1 then`
334			`if (iWrEn = '0') and (iRdEn = '1') then`
335			`sProgEmpty <= '1';`
336			`else`
337			`sProgEmpty <= '0';`
338			`end if;`
339			`elsif svFifoCount = ivProgEmptyTh then`
340			`if (iWrEn = '1') and (iRdEn = '0') then`
341			`sProgEmpty <= '0';`
342			`else`
343			`sProgEmpty <= '1';`
344			`end if;`
345			`elsif svFifoCount < ivProgEmptyTh then`
346			`sProgEmpty <= '1';`
347			`else`
348			`sProgEmpty <= '0';`
349			`end if;`
350			`--------------------------------`
351			`-- Generate the error flag`
352			`-------------------------------`
353			`if sFifoFull = '1' and iWrEn = '1' then`
354			`sFifoOverflow <= '1';`
355			`end if;`
356
357			`if sFifoEmpty = '1' and iRdEn = '1' then`
358			`sFifoUnderflow <= '1';`
359			`end if;`
360			`end if;`
361			`end if;`
362			`end process;`
363
364			`oFull <= sFifoFull;`
365			`oEmpty <= sFifoEmpty;`
366			`oAlmostFull <= sAlmostFull;`
367			`oAlmostEmpty <= sAlmostEmpty;`
368			`oProgFull <= sProgFull;`
369			`oProgEmpty <= sProgEmpty;`
370			`oOverflow <= sFifoOverflow;`
371			`oUnderflow <= sFifoUnderflow;`
372
373			`-------------------------------------------------------------------------------------`
374			`-- This section generates the code for the output pipelines`
375			`-------------------------------------------------------------------------------------`
376			`OutputPipeline_gen_1: if gOUTPUT_PIPELINE_NUM = 1 generate`
377			`ovDataOut <= svMemDataOut;`
378			`oDataOutValid <= sMemDataOutValid;`
379			`end generate;`
380
381			`OutputPipeline_gen_2: if gOUTPUT_PIPELINE_NUM = 2 generate`
382			`process (iClk)`
383			`begin`
384			`if rising_edge(iClk) then`
385			`if (iReset_sync = '1') then`
386			`ovDataOut <= (others=>'0');`
387			`oDataOutValid <= '0';`
388			`else`
389			`ovDataOut <= svMemDataOut;`
390			`oDataOutValid <= sMemDataOutValid;`
391			`end if;`
392			`end if;`
393			`end process;`
394			`end generate;`
395
396			`OutputPipeline_gen_others: if gOUTPUT_PIPELINE_NUM > 2 generate`
397			`pipelines_without_reset_inst_output: pipelines_without_reset`
398			`GENERIC map(`
399			`gBUS_WIDTH => gDATA_WIDTH,`
400			`gNB_PIPELINES => (gOUTPUT_PIPELINE_NUM-1)`
401			`)`
402			`PORT map(`
403			`iClk => iClk,`
404			`iInput => sMemDataOutValid,`
405			`ivInput => svMemDataOut,`
406			`oDelayed_output => sPipeDataOutValid,`
407			`ovDelayed_output => svPipeDataOut`
408			`);`
409
410			`process (iClk)`
411			`begin`
412			`if rising_edge(iClk) then`
413			`if (iReset_sync = '1') then`
414			`ovDataOut <= (others=>'0');`
415			`oDataOutValid <= '0';`
416			`else`
417			`ovDataOut <= svPipeDataOut;`
418			`oDataOutValid <= sPipeDataOutValid;`
419			`end if;`
420			`end if;`
421			`end process;`
422			`end generate;`
423
424			`END behavioral;`
425
426
427