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nuxi1209 |
-- Copyright (c) 2013 VariStream
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-- Auther : Yu Peng
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.NUMERIC_STD.ALL;
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use work.sha_256_pkg.ALL;
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entity btc_dsha is
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generic(
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gBASE_DELAY : integer := 1
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);
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port(
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iClkReg : in std_logic := '0';
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iClkProcess : in std_logic := '0';
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iRst_async : in std_logic := '0';
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iValid_p : in std_logic := '0';
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ivAddr : in std_logic_vector(3 downto 0) := (others=>'0');
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ivData : in std_logic_vector(31 downto 0) := (others=>'0');
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oReachEnd : out std_logic := '0';
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oFoundNonce : out std_logic := '0';
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ovNonce : out std_logic_vector(31 downto 0) := (others=>'0');
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ovDigest : out tDwordArray(0 to 7) := (others=>(others=>'0'))
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);
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end btc_dsha;
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architecture behavioral of btc_dsha is
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component pipelines_without_reset IS
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GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);
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PORT(
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iClk : IN STD_LOGIC;
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iInput : IN STD_LOGIC;
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ivInput : IN STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);
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oDelayed_output : OUT STD_LOGIC;
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ovDelayed_output : OUT STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)
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);
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END component;
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component edgedtc is port
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(
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iD : in std_logic;
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iClk : in std_logic;
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iResetSync_Clk : in std_logic;
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iEdge : in std_logic;
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oQ : out std_logic := '0'
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);
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end component;
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component sha_256_chunk is
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generic(
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gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
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gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');
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gBASE_DELAY : integer := 3;
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gOUT_VALID_GEN : boolean := false;
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gUSE_BRAM_AS_LARGE_SHIFTREG : boolean := false
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);
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port(
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iClk : in std_logic := '0';
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iRst_async : in std_logic := '0';
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iValid : in std_logic := '0';
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ivMsgDword : in tDwordArray(0 to 15) := (others=>(others=>'0'));
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ivH0 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH1 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH2 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH3 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH4 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH5 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH6 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH7 : in std_logic_vector(31 downto 0) := (others=>'0');
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ovH0 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH1 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH2 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH3 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH4 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH5 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH6 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH7 : out std_logic_vector(31 downto 0) := (others=>'0');
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oValid : out std_logic := '0'
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);
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end component;
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component HandShake is port
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(
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iResetSync_Clk : in std_logic; -- Active Hi Reset
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iClk : in std_logic; -- Clock
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iExternalDemand : in std_logic; -- Async External Demand : one positive pulse
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oInternalDemand : out std_logic; -- Sync with iClk Internal demand
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iInternalClrDemand : in std_logic -- Clr Internal Demand
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);
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end component;
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component SyncReset is
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port(
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iClk : in std_logic; -- Clock domain that the reset should be resynchronyze to
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iAsyncReset : in std_logic; -- Asynchronous reset that should be resynchronyse
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oSyncReset : out std_logic -- Synchronous reset output
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);
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end component;
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constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
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constant cCMD_IDLE : std_logic_vector(15 downto 0) := X"0000";
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constant cCMD_RESET : std_logic_vector(15 downto 0) := X"CAFE";
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constant cCMD_START : std_logic_vector(15 downto 0) := X"0001";
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constant cPROCESS_DEALY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1, 16);
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constant cCMP_DELAY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1 + 2, 16);
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type tProcessStateMachine is (stIdle, stSearch); --, stFound, stNone);
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signal sReset_syncProcess : std_logic := '0';
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signal svMidState : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal svMerkleRootDword7 : std_logic_vector(31 downto 0) := (others=>'0');
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signal svTimeStamp : std_logic_vector(31 downto 0) := (others=>'0');
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signal svTargetBits : std_logic_vector(31 downto 0) := (others=>'0');
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signal svTargetIndex : std_logic_vector(7 downto 0) := (others=>'0');
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signal svTargetFraction : std_logic_vector(23 downto 0) := (others=>'0');
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signal svH : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal svStage1MsgDword : tDwordArray(0 to 15) := (others=>(others=>'0'));
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signal svStage1Digest : tDwordArray(0 to 7) := (others=>(others=>'0'));
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signal svStage2MsgDword : tDwordArray(0 to 15) := (others=>(others=>'0'));
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signal svStartNonce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svEndNonce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svNonce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svCmd : std_logic_vector(15 downto 0) := (others=>'0');
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signal sCmdValid_syncReg_p : std_logic := '0';
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signal sCmdReset : std_logic := '0';
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signal sCmdStart_syncReg_p : std_logic := '0';
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signal sCmdStart_syncProcess_p : std_logic := '0';
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signal sCmdStart_syncProcess_p_1d : std_logic := '0';
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signal sProcess : tProcessStateMachine := stIdle;
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signal svProcessDelayCnt : std_logic_vector(15 downto 0) := (others=>'0');
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signal sProcessOutValid : std_logic := '0';
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signal sProcessOutValid_1d : std_logic := '0';
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signal sProcessOutValid_2d : std_logic := '0';
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signal svCmpNounce : std_logic_vector(31 downto 0) := (others=>'0');
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signal svProcessNounce_1d : std_logic_vector(31 downto 0) := (others=>'0');
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signal svProcessNounce_2d : std_logic_vector(31 downto 0) := (others=>'0');
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signal svStage2DigestBig : std_logic_vector(255 downto 0) := (others=>'0');
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signal svStage2DigestLittle : std_logic_vector(255 downto 0) := (others=>'0');
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signal svDigestIsZero : std_logic_vector(31 downto 0) := (others=>'0');
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signal svDigestSignificant : std_logic_vector(23 downto 0) := (others=>'0');
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signal sDigestHighBitsZero : std_logic := '0';
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signal sDigestSignificantFit : std_logic := '0';
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signal svCmpDelayCnt : std_logic_vector(15 downto 0) := (others=>'0');
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signal sCmpResultValid : std_logic := '0';
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signal sFoundNonceToIdle : std_logic := '0';
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signal sReachEndToIdle : std_logic := '0';
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begin
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SyncReset_inst_Process : SyncReset
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port map(
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iClk => iClkProcess,
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iAsyncReset => iRst_async,
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oSyncReset => sReset_syncProcess
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);
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process(iClkReg)
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begin
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if rising_edge(iClkReg) then
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if iValid_p = '1' then
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case ivAddr is
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when X"0" =>
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svMidState(0) <= ivData;
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when X"1" =>
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svMidState(1) <= ivData;
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when X"2" =>
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svMidState(2) <= ivData;
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when X"3" =>
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svMidState(3) <= ivData;
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when X"4" =>
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svMidState(4) <= ivData;
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when X"5" =>
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svMidState(5) <= ivData;
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when X"6" =>
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svMidState(6) <= ivData;
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when X"7" =>
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svMidState(7) <= ivData;
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when X"8" =>
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svMerkleRootDword7 <= ivData;
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when X"9" =>
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svTimeStamp <= ivData;
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when X"A" =>
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svTargetBits <= ivData;
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when X"B" =>
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svStartNonce(31 downto 0) <= ivData;
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when X"C" =>
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svEndNonce(31 downto 0) <= ivData;
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when cCMD_ADDR =>
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svCmd <= ivData(15 downto 0);
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when others =>
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svCmd <= ivData(15 downto 0);
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end case;
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end if;
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end if;
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end process;
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process(iClkReg, iRst_async)
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begin
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if iRst_async = '1' then
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sCmdReset <= '0';
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sCmdValid_syncReg_p <= '0';
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elsif rising_edge(iClkReg) then
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if iValid_p = '1' and ivAddr = cCMD_ADDR then
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if ivData(15 downto 0) = cCMD_RESET then
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sCmdReset <= '1';
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else
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sCmdReset <= '0';
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end if;
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end if;
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if iValid_p = '1' and ivAddr = cCMD_ADDR then
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sCmdValid_syncReg_p <= '1';
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else
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sCmdValid_syncReg_p <= '0';
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end if;
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if iValid_p = '1' and ivAddr = cCMD_ADDR and ivData(15 downto 0) = cCMD_START then
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sCmdStart_syncReg_p <= '1';
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else
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sCmdStart_syncReg_p <= '0';
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end if;
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end if;
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end process;
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HandShake_inst : HandShake
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port map (
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iResetSync_Clk => sReset_syncProcess,
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iClk => iClkProcess,
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iExternalDemand => sCmdStart_syncReg_p,
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oInternalDemand => sCmdStart_syncProcess_p,
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iInternalClrDemand => sCmdStart_syncProcess_p
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);
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process(iClkProcess, iRst_async)
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begin
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if iRst_async = '1' then
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sCmdStart_syncProcess_p_1d <= '0';
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elsif rising_edge(iClkProcess) then
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sCmdStart_syncProcess_p_1d <= sCmdStart_syncProcess_p;
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end if;
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end process;
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process(iClkProcess)
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begin
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if rising_edge(iClkProcess) then
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if sCmdStart_syncProcess_p = '1' then
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for i in 0 to 7 loop
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svH(i) <= svMidState(i);
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end loop;
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svStage1MsgDword(0) <= svMerkleRootDword7;
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svStage1MsgDword(1) <= svTimeStamp;
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svStage1MsgDword(2) <= svTargetBits;
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end if;
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end if;
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end process;
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process(iClkProcess)
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begin
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if rising_edge(iClkProcess) then
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if sCmdStart_syncProcess_p = '1' then
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svNonce <= svStartNonce;
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elsif sCmdStart_syncProcess_p_1d = '1' or sProcess = stSearch then
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svNonce <= svNonce + '1';
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end if;
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svStage1MsgDword(3) <= svNonce;
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end if;
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end process;
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process(iClkProcess)
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begin
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if rising_edge(iClkProcess) then
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if sCmdStart_syncProcess_p = '1' then
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svProcessDelayCnt <= (others=>'0');
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sProcessOutValid <= '0';
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sProcessOutValid_1d <= '0';
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sProcessOutValid_2d <= '0';
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else
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if sProcess = stSearch and svProcessDelayCnt < cPROCESS_DEALY then
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svProcessDelayCnt <= svProcessDelayCnt + '1';
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end if;
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|
|
if sProcess = stSearch and svProcessDelayCnt = cPROCESS_DEALY then
|
| 318 |
|
|
sProcessOutValid <= '1';
|
| 319 |
|
|
elsif sReachEndToIdle = '1' or sFoundNonceToIdle = '1' then
|
| 320 |
|
|
sProcessOutValid <= '0';
|
| 321 |
|
|
end if;
|
| 322 |
|
|
|
| 323 |
|
|
sProcessOutValid_1d <= sProcessOutValid;
|
| 324 |
|
|
sProcessOutValid_2d <= sProcessOutValid_1d;
|
| 325 |
|
|
end if;
|
| 326 |
|
|
end if;
|
| 327 |
|
|
end process;
|
| 328 |
|
|
|
| 329 |
|
|
process(iClkProcess)
|
| 330 |
|
|
begin
|
| 331 |
|
|
if rising_edge(iClkProcess) then
|
| 332 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 333 |
|
|
sProcess <= stIdle;
|
| 334 |
|
|
else
|
| 335 |
|
|
case sProcess is
|
| 336 |
|
|
when stIdle =>
|
| 337 |
|
|
if sCmdStart_syncProcess_p_1d = '1' then
|
| 338 |
|
|
sProcess <= stSearch;
|
| 339 |
|
|
end if;
|
| 340 |
|
|
|
| 341 |
|
|
when stSearch =>
|
| 342 |
|
|
if sFoundNonceToIdle = '1' then
|
| 343 |
|
|
sProcess <= stIdle;
|
| 344 |
|
|
elsif sReachEndToIdle = '1' then
|
| 345 |
|
|
sProcess <= stIdle;
|
| 346 |
|
|
end if;
|
| 347 |
|
|
|
| 348 |
|
|
when others =>
|
| 349 |
|
|
sProcess <= stIdle;
|
| 350 |
|
|
end case;
|
| 351 |
|
|
end if;
|
| 352 |
|
|
end if;
|
| 353 |
|
|
end process;
|
| 354 |
|
|
|
| 355 |
|
|
svStage1MsgDword(4) <= X"80000000";
|
| 356 |
|
|
svStage1MsgDword(5) <= X"00000000";
|
| 357 |
|
|
svStage1MsgDword(6) <= X"00000000";
|
| 358 |
|
|
svStage1MsgDword(7) <= X"00000000";
|
| 359 |
|
|
svStage1MsgDword(8) <= X"00000000";
|
| 360 |
|
|
svStage1MsgDword(9) <= X"00000000";
|
| 361 |
|
|
svStage1MsgDword(10) <= X"00000000";
|
| 362 |
|
|
svStage1MsgDword(11) <= X"00000000";
|
| 363 |
|
|
svStage1MsgDword(12) <= X"00000000";
|
| 364 |
|
|
svStage1MsgDword(13) <= X"00000000";
|
| 365 |
|
|
svStage1MsgDword(14) <= X"00000000";
|
| 366 |
|
|
svStage1MsgDword(15) <= X"00000280";
|
| 367 |
|
|
|
| 368 |
|
|
sha_256_chunk_inst_stage1: sha_256_chunk
|
| 369 |
|
|
generic map(
|
| 370 |
|
|
gMSG_IS_CONSTANT => (3 => '0', others => '1'),
|
| 371 |
|
|
gH_IS_CONST => (others => '1'),
|
| 372 |
|
|
gBASE_DELAY => gBASE_DELAY
|
| 373 |
|
|
)
|
| 374 |
|
|
port map(
|
| 375 |
|
|
iClk => iClkProcess,
|
| 376 |
|
|
iRst_async => iRst_async,
|
| 377 |
|
|
|
| 378 |
|
|
iValid => '0',
|
| 379 |
|
|
|
| 380 |
|
|
ivMsgDword => svStage1MsgDword,
|
| 381 |
|
|
|
| 382 |
|
|
ivH0 => svH(0),
|
| 383 |
|
|
ivH1 => svH(1),
|
| 384 |
|
|
ivH2 => svH(2),
|
| 385 |
|
|
ivH3 => svH(3),
|
| 386 |
|
|
ivH4 => svH(4),
|
| 387 |
|
|
ivH5 => svH(5),
|
| 388 |
|
|
ivH6 => svH(6),
|
| 389 |
|
|
ivH7 => svH(7),
|
| 390 |
|
|
|
| 391 |
|
|
ovH0 => svStage1Digest(0),
|
| 392 |
|
|
ovH1 => svStage1Digest(1),
|
| 393 |
|
|
ovH2 => svStage1Digest(2),
|
| 394 |
|
|
ovH3 => svStage1Digest(3),
|
| 395 |
|
|
ovH4 => svStage1Digest(4),
|
| 396 |
|
|
ovH5 => svStage1Digest(5),
|
| 397 |
|
|
ovH6 => svStage1Digest(6),
|
| 398 |
|
|
ovH7 => svStage1Digest(7),
|
| 399 |
|
|
|
| 400 |
|
|
oValid => open
|
| 401 |
|
|
);
|
| 402 |
|
|
|
| 403 |
|
|
svStage2MsgDword(0) <= svStage1Digest(0);
|
| 404 |
|
|
svStage2MsgDword(1) <= svStage1Digest(1);
|
| 405 |
|
|
svStage2MsgDword(2) <= svStage1Digest(2);
|
| 406 |
|
|
svStage2MsgDword(3) <= svStage1Digest(3);
|
| 407 |
|
|
svStage2MsgDword(4) <= svStage1Digest(4);
|
| 408 |
|
|
svStage2MsgDword(5) <= svStage1Digest(5);
|
| 409 |
|
|
svStage2MsgDword(6) <= svStage1Digest(6);
|
| 410 |
|
|
svStage2MsgDword(7) <= svStage1Digest(7);
|
| 411 |
|
|
svStage2MsgDword(8) <= X"80000000";
|
| 412 |
|
|
svStage2MsgDword(9) <= X"00000000";
|
| 413 |
|
|
svStage2MsgDword(10) <= X"00000000";
|
| 414 |
|
|
svStage2MsgDword(11) <= X"00000000";
|
| 415 |
|
|
svStage2MsgDword(12) <= X"00000000";
|
| 416 |
|
|
svStage2MsgDword(13) <= X"00000000";
|
| 417 |
|
|
svStage2MsgDword(14) <= X"00000000";
|
| 418 |
|
|
svStage2MsgDword(15) <= X"00000100";
|
| 419 |
|
|
|
| 420 |
|
|
sha_256_chunk_inst_stage2: sha_256_chunk
|
| 421 |
|
|
generic map(
|
| 422 |
|
|
gMSG_IS_CONSTANT => (0 => '0',
|
| 423 |
|
|
1 => '0',
|
| 424 |
|
|
2 => '0',
|
| 425 |
|
|
3 => '0',
|
| 426 |
|
|
4 => '0',
|
| 427 |
|
|
5 => '0',
|
| 428 |
|
|
6 => '0',
|
| 429 |
|
|
7 => '0',
|
| 430 |
|
|
others => '1'),
|
| 431 |
|
|
gH_IS_CONST => (others => '1'),
|
| 432 |
|
|
gBASE_DELAY => gBASE_DELAY
|
| 433 |
|
|
)
|
| 434 |
|
|
port map(
|
| 435 |
|
|
iClk => iClkProcess,
|
| 436 |
|
|
iRst_async => iRst_async,
|
| 437 |
|
|
|
| 438 |
|
|
iValid => '0',
|
| 439 |
|
|
|
| 440 |
|
|
ivMsgDword => svStage2MsgDword,
|
| 441 |
|
|
|
| 442 |
|
|
ivH0 => X"6a09e667",
|
| 443 |
|
|
ivH1 => X"bb67ae85",
|
| 444 |
|
|
ivH2 => X"3c6ef372",
|
| 445 |
|
|
ivH3 => X"a54ff53a",
|
| 446 |
|
|
ivH4 => X"510e527f",
|
| 447 |
|
|
ivH5 => X"9b05688c",
|
| 448 |
|
|
ivH6 => X"1f83d9ab",
|
| 449 |
|
|
ivH7 => X"5be0cd19",
|
| 450 |
|
|
|
| 451 |
|
|
ovH0 => svStage2DigestBig(((7 + 1) * 32 - 1) downto (7 * 32)),
|
| 452 |
|
|
ovH1 => svStage2DigestBig(((6 + 1) * 32 - 1) downto (6 * 32)),
|
| 453 |
|
|
ovH2 => svStage2DigestBig(((5 + 1) * 32 - 1) downto (5 * 32)),
|
| 454 |
|
|
ovH3 => svStage2DigestBig(((4 + 1) * 32 - 1) downto (4 * 32)),
|
| 455 |
|
|
ovH4 => svStage2DigestBig(((3 + 1) * 32 - 1) downto (3 * 32)),
|
| 456 |
|
|
ovH5 => svStage2DigestBig(((2 + 1) * 32 - 1) downto (2 * 32)),
|
| 457 |
|
|
ovH6 => svStage2DigestBig(((1 + 1) * 32 - 1) downto (1 * 32)),
|
| 458 |
|
|
ovH7 => svStage2DigestBig(((0 + 1) * 32 - 1) downto (0 * 32)),
|
| 459 |
|
|
|
| 460 |
|
|
oValid => open
|
| 461 |
|
|
);
|
| 462 |
|
|
|
| 463 |
|
|
Stage2DigestLittle_gen : for i in 0 to 31 generate
|
| 464 |
|
|
svStage2DigestLittle(((i + 1) * 8 - 1) downto (i * 8)) <= svStage2DigestBig(((31 - i + 1) * 8 - 1) downto ((31 - i) * 8));
|
| 465 |
|
|
end generate;
|
| 466 |
|
|
|
| 467 |
|
|
Digest_gen : for i in 0 to 7 generate
|
| 468 |
|
|
ovDigest(i) <= svStage2DigestBig(((i + 1) * 32 - 1) downto (i * 32));
|
| 469 |
|
|
end generate;
|
| 470 |
|
|
|
| 471 |
|
|
process(iClkProcess)
|
| 472 |
|
|
begin
|
| 473 |
|
|
if rising_edge(iClkProcess) then
|
| 474 |
|
|
for i in 0 to 31 loop
|
| 475 |
|
|
if svStage2DigestLittle(((i + 1) * 8 - 1) downto (i * 8)) = X"00" then
|
| 476 |
|
|
svDigestIsZero(i) <= '1';
|
| 477 |
|
|
else
|
| 478 |
|
|
svDigestIsZero(i) <= '0';
|
| 479 |
|
|
end if;
|
| 480 |
|
|
end loop;
|
| 481 |
|
|
|
| 482 |
|
|
case svTargetIndex(4 downto 0) is
|
| 483 |
|
|
when "00011" =>
|
| 484 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 3 - 1 downto 8 * (3 - 3));
|
| 485 |
|
|
|
| 486 |
|
|
when "00100" =>
|
| 487 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 4 - 1 downto 8 * (4 - 3));
|
| 488 |
|
|
|
| 489 |
|
|
when "00101" =>
|
| 490 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 5 - 1 downto 8 * (5 - 3));
|
| 491 |
|
|
|
| 492 |
|
|
when "00110" =>
|
| 493 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 6 - 1 downto 8 * (6 - 3));
|
| 494 |
|
|
|
| 495 |
|
|
when "00111" =>
|
| 496 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 7 - 1 downto 8 * (7 - 3));
|
| 497 |
|
|
|
| 498 |
|
|
when "01000" =>
|
| 499 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 8 - 1 downto 8 * (8 - 3));
|
| 500 |
|
|
|
| 501 |
|
|
when "01001" =>
|
| 502 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 9 - 1 downto 8 * (9 - 3));
|
| 503 |
|
|
|
| 504 |
|
|
when "01010" =>
|
| 505 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 10 - 1 downto 8 * (10 - 3));
|
| 506 |
|
|
|
| 507 |
|
|
when "01011" =>
|
| 508 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 11 - 1 downto 8 * (11 - 3));
|
| 509 |
|
|
|
| 510 |
|
|
when "01100" =>
|
| 511 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 12 - 1 downto 8 * (12 - 3));
|
| 512 |
|
|
|
| 513 |
|
|
when "01101" =>
|
| 514 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 13 - 1 downto 8 * (13 - 3));
|
| 515 |
|
|
|
| 516 |
|
|
when "01110" =>
|
| 517 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 14 - 1 downto 8 * (14 - 3));
|
| 518 |
|
|
|
| 519 |
|
|
when "01111" =>
|
| 520 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 15 - 1 downto 8 * (15 - 3));
|
| 521 |
|
|
|
| 522 |
|
|
when "10000" =>
|
| 523 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 16 - 1 downto 8 * (16 - 3));
|
| 524 |
|
|
|
| 525 |
|
|
when "10001" =>
|
| 526 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 17 - 1 downto 8 * (17 - 3));
|
| 527 |
|
|
|
| 528 |
|
|
when "10010" =>
|
| 529 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 18 - 1 downto 8 * (18 - 3));
|
| 530 |
|
|
|
| 531 |
|
|
when "10011" =>
|
| 532 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 19 - 1 downto 8 * (19 - 3));
|
| 533 |
|
|
|
| 534 |
|
|
when "10100" =>
|
| 535 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 20 - 1 downto 8 * (20 - 3));
|
| 536 |
|
|
|
| 537 |
|
|
when "10101" =>
|
| 538 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 21 - 1 downto 8 * (21 - 3));
|
| 539 |
|
|
|
| 540 |
|
|
when "10110" =>
|
| 541 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 22 - 1 downto 8 * (22 - 3));
|
| 542 |
|
|
|
| 543 |
|
|
when "10111" =>
|
| 544 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 23 - 1 downto 8 * (23 - 3));
|
| 545 |
|
|
|
| 546 |
|
|
when "11000" =>
|
| 547 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 24 - 1 downto 8 * (24 - 3));
|
| 548 |
|
|
|
| 549 |
|
|
when "11001" =>
|
| 550 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 25 - 1 downto 8 * (25 - 3));
|
| 551 |
|
|
|
| 552 |
|
|
when "11010" =>
|
| 553 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 26 - 1 downto 8 * (26 - 3));
|
| 554 |
|
|
|
| 555 |
|
|
when "11011" =>
|
| 556 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 27 - 1 downto 8 * (27 - 3));
|
| 557 |
|
|
|
| 558 |
|
|
when "11100" =>
|
| 559 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 28 - 1 downto 8 * (28 - 3));
|
| 560 |
|
|
|
| 561 |
|
|
when others => --"11101", Maximum difficulty
|
| 562 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 29 - 1 downto 8 * (29 - 3));
|
| 563 |
|
|
end case;
|
| 564 |
|
|
end if;
|
| 565 |
|
|
end process;
|
| 566 |
|
|
|
| 567 |
|
|
svTargetIndex <= svTargetBits(7 downto 0);
|
| 568 |
|
|
svTargetFraction(7 downto 0) <= svTargetBits(31 downto 24);
|
| 569 |
|
|
svTargetFraction(15 downto 8) <= svTargetBits(23 downto 16);
|
| 570 |
|
|
svTargetFraction(23 downto 16) <= svTargetBits(15 downto 8);
|
| 571 |
|
|
|
| 572 |
|
|
process(iClkProcess)
|
| 573 |
|
|
begin
|
| 574 |
|
|
if rising_edge(iClkProcess) then
|
| 575 |
|
|
case svTargetIndex(4 downto 0) is
|
| 576 |
|
|
when "00011" =>
|
| 577 |
|
|
if svDigestIsZero(31 downto 3) = conv_std_logic_vector(-1, 31 - 3 + 1) then
|
| 578 |
|
|
sDigestHighBitsZero <= '1';
|
| 579 |
|
|
else
|
| 580 |
|
|
sDigestHighBitsZero <= '0';
|
| 581 |
|
|
end if;
|
| 582 |
|
|
|
| 583 |
|
|
when "00100" =>
|
| 584 |
|
|
if svDigestIsZero(31 downto 4) = conv_std_logic_vector(-1, 31 - 4 + 1) then
|
| 585 |
|
|
sDigestHighBitsZero <= '1';
|
| 586 |
|
|
else
|
| 587 |
|
|
sDigestHighBitsZero <= '0';
|
| 588 |
|
|
end if;
|
| 589 |
|
|
|
| 590 |
|
|
when "00101" =>
|
| 591 |
|
|
if svDigestIsZero(31 downto 5) = conv_std_logic_vector(-1, 31 - 5 + 1) then
|
| 592 |
|
|
sDigestHighBitsZero <= '1';
|
| 593 |
|
|
else
|
| 594 |
|
|
sDigestHighBitsZero <= '0';
|
| 595 |
|
|
end if;
|
| 596 |
|
|
|
| 597 |
|
|
when "00110" =>
|
| 598 |
|
|
if svDigestIsZero(31 downto 6) = conv_std_logic_vector(-1, 31 - 6 + 1) then
|
| 599 |
|
|
sDigestHighBitsZero <= '1';
|
| 600 |
|
|
else
|
| 601 |
|
|
sDigestHighBitsZero <= '0';
|
| 602 |
|
|
end if;
|
| 603 |
|
|
|
| 604 |
|
|
when "00111" =>
|
| 605 |
|
|
if svDigestIsZero(31 downto 7) = conv_std_logic_vector(-1, 31 - 7 + 1) then
|
| 606 |
|
|
sDigestHighBitsZero <= '1';
|
| 607 |
|
|
else
|
| 608 |
|
|
sDigestHighBitsZero <= '0';
|
| 609 |
|
|
end if;
|
| 610 |
|
|
|
| 611 |
|
|
when "01000" =>
|
| 612 |
|
|
if svDigestIsZero(31 downto 8) = conv_std_logic_vector(-1, 31 - 8 + 1) then
|
| 613 |
|
|
sDigestHighBitsZero <= '1';
|
| 614 |
|
|
else
|
| 615 |
|
|
sDigestHighBitsZero <= '0';
|
| 616 |
|
|
end if;
|
| 617 |
|
|
|
| 618 |
|
|
when "01001" =>
|
| 619 |
|
|
if svDigestIsZero(31 downto 9) = conv_std_logic_vector(-1, 31 - 9 + 1) then
|
| 620 |
|
|
sDigestHighBitsZero <= '1';
|
| 621 |
|
|
else
|
| 622 |
|
|
sDigestHighBitsZero <= '0';
|
| 623 |
|
|
end if;
|
| 624 |
|
|
|
| 625 |
|
|
when "01010" =>
|
| 626 |
|
|
if svDigestIsZero(31 downto 10) = conv_std_logic_vector(-1, 31 - 10 + 1) then
|
| 627 |
|
|
sDigestHighBitsZero <= '1';
|
| 628 |
|
|
else
|
| 629 |
|
|
sDigestHighBitsZero <= '0';
|
| 630 |
|
|
end if;
|
| 631 |
|
|
|
| 632 |
|
|
when "01011" =>
|
| 633 |
|
|
if svDigestIsZero(31 downto 11) = conv_std_logic_vector(-1, 31 - 11 + 1) then
|
| 634 |
|
|
sDigestHighBitsZero <= '1';
|
| 635 |
|
|
else
|
| 636 |
|
|
sDigestHighBitsZero <= '0';
|
| 637 |
|
|
end if;
|
| 638 |
|
|
|
| 639 |
|
|
when "01100" =>
|
| 640 |
|
|
if svDigestIsZero(31 downto 12) = conv_std_logic_vector(-1, 31 - 12 + 1) then
|
| 641 |
|
|
sDigestHighBitsZero <= '1';
|
| 642 |
|
|
else
|
| 643 |
|
|
sDigestHighBitsZero <= '0';
|
| 644 |
|
|
end if;
|
| 645 |
|
|
|
| 646 |
|
|
when "01101" =>
|
| 647 |
|
|
if svDigestIsZero(31 downto 13) = conv_std_logic_vector(-1, 31 -13 + 1) then
|
| 648 |
|
|
sDigestHighBitsZero <= '1';
|
| 649 |
|
|
else
|
| 650 |
|
|
sDigestHighBitsZero <= '0';
|
| 651 |
|
|
end if;
|
| 652 |
|
|
|
| 653 |
|
|
when "01110" =>
|
| 654 |
|
|
if svDigestIsZero(31 downto 14) = conv_std_logic_vector(-1, 31 - 14 + 1) then
|
| 655 |
|
|
sDigestHighBitsZero <= '1';
|
| 656 |
|
|
else
|
| 657 |
|
|
sDigestHighBitsZero <= '0';
|
| 658 |
|
|
end if;
|
| 659 |
|
|
|
| 660 |
|
|
when "01111" =>
|
| 661 |
|
|
if svDigestIsZero(31 downto 15) = conv_std_logic_vector(-1, 31 - 15 + 1) then
|
| 662 |
|
|
sDigestHighBitsZero <= '1';
|
| 663 |
|
|
else
|
| 664 |
|
|
sDigestHighBitsZero <= '0';
|
| 665 |
|
|
end if;
|
| 666 |
|
|
|
| 667 |
|
|
when "10000" =>
|
| 668 |
|
|
if svDigestIsZero(31 downto 16) = conv_std_logic_vector(-1, 31 - 16 + 1) then
|
| 669 |
|
|
sDigestHighBitsZero <= '1';
|
| 670 |
|
|
else
|
| 671 |
|
|
sDigestHighBitsZero <= '0';
|
| 672 |
|
|
end if;
|
| 673 |
|
|
|
| 674 |
|
|
when "10001" =>
|
| 675 |
|
|
if svDigestIsZero(31 downto 17) = conv_std_logic_vector(-1, 31 - 17 + 1) then
|
| 676 |
|
|
sDigestHighBitsZero <= '1';
|
| 677 |
|
|
else
|
| 678 |
|
|
sDigestHighBitsZero <= '0';
|
| 679 |
|
|
end if;
|
| 680 |
|
|
|
| 681 |
|
|
when "10010" =>
|
| 682 |
|
|
if svDigestIsZero(31 downto 18) = conv_std_logic_vector(-1, 31 - 18 + 1) then
|
| 683 |
|
|
sDigestHighBitsZero <= '1';
|
| 684 |
|
|
else
|
| 685 |
|
|
sDigestHighBitsZero <= '0';
|
| 686 |
|
|
end if;
|
| 687 |
|
|
|
| 688 |
|
|
when "10011" =>
|
| 689 |
|
|
if svDigestIsZero(31 downto 19) = conv_std_logic_vector(-1, 31 - 19 + 1) then
|
| 690 |
|
|
sDigestHighBitsZero <= '1';
|
| 691 |
|
|
else
|
| 692 |
|
|
sDigestHighBitsZero <= '0';
|
| 693 |
|
|
end if;
|
| 694 |
|
|
|
| 695 |
|
|
when "10100" =>
|
| 696 |
|
|
if svDigestIsZero(31 downto 20) = conv_std_logic_vector(-1, 31 - 20 + 1) then
|
| 697 |
|
|
sDigestHighBitsZero <= '1';
|
| 698 |
|
|
else
|
| 699 |
|
|
sDigestHighBitsZero <= '0';
|
| 700 |
|
|
end if;
|
| 701 |
|
|
|
| 702 |
|
|
when "10101" =>
|
| 703 |
|
|
if svDigestIsZero(31 downto 21) = conv_std_logic_vector(-1, 31 - 21 + 1) then
|
| 704 |
|
|
sDigestHighBitsZero <= '1';
|
| 705 |
|
|
else
|
| 706 |
|
|
sDigestHighBitsZero <= '0';
|
| 707 |
|
|
end if;
|
| 708 |
|
|
|
| 709 |
|
|
when "10110" =>
|
| 710 |
|
|
if svDigestIsZero(31 downto 22) = conv_std_logic_vector(-1, 31 - 22 + 1) then
|
| 711 |
|
|
sDigestHighBitsZero <= '1';
|
| 712 |
|
|
else
|
| 713 |
|
|
sDigestHighBitsZero <= '0';
|
| 714 |
|
|
end if;
|
| 715 |
|
|
|
| 716 |
|
|
when "10111" =>
|
| 717 |
|
|
if svDigestIsZero(31 downto 23) = conv_std_logic_vector(-1, 31 - 23 + 1) then
|
| 718 |
|
|
sDigestHighBitsZero <= '1';
|
| 719 |
|
|
else
|
| 720 |
|
|
sDigestHighBitsZero <= '0';
|
| 721 |
|
|
end if;
|
| 722 |
|
|
|
| 723 |
|
|
when "11000" =>
|
| 724 |
|
|
if svDigestIsZero(31 downto 24) = conv_std_logic_vector(-1, 31 - 24 + 1) then
|
| 725 |
|
|
sDigestHighBitsZero <= '1';
|
| 726 |
|
|
else
|
| 727 |
|
|
sDigestHighBitsZero <= '0';
|
| 728 |
|
|
end if;
|
| 729 |
|
|
|
| 730 |
|
|
when "11001" =>
|
| 731 |
|
|
if svDigestIsZero(31 downto 25) = conv_std_logic_vector(-1, 31 - 25 + 1) then
|
| 732 |
|
|
sDigestHighBitsZero <= '1';
|
| 733 |
|
|
else
|
| 734 |
|
|
sDigestHighBitsZero <= '0';
|
| 735 |
|
|
end if;
|
| 736 |
|
|
|
| 737 |
|
|
when "11010" =>
|
| 738 |
|
|
if svDigestIsZero(31 downto 26) = conv_std_logic_vector(-1, 31 - 26 + 1) then
|
| 739 |
|
|
sDigestHighBitsZero <= '1';
|
| 740 |
|
|
else
|
| 741 |
|
|
sDigestHighBitsZero <= '0';
|
| 742 |
|
|
end if;
|
| 743 |
|
|
|
| 744 |
|
|
when "11011" =>
|
| 745 |
|
|
if svDigestIsZero(31 downto 27) = conv_std_logic_vector(-1, 31 - 27 + 1) then
|
| 746 |
|
|
sDigestHighBitsZero <= '1';
|
| 747 |
|
|
else
|
| 748 |
|
|
sDigestHighBitsZero <= '0';
|
| 749 |
|
|
end if;
|
| 750 |
|
|
|
| 751 |
|
|
when "11100" =>
|
| 752 |
|
|
if svDigestIsZero(31 downto 28) = conv_std_logic_vector(-1, 31 - 28 + 1) then
|
| 753 |
|
|
sDigestHighBitsZero <= '1';
|
| 754 |
|
|
else
|
| 755 |
|
|
sDigestHighBitsZero <= '0';
|
| 756 |
|
|
end if;
|
| 757 |
|
|
|
| 758 |
|
|
when others => --"11101", Maximum difficulty
|
| 759 |
|
|
if svDigestIsZero(31 downto 29) = conv_std_logic_vector(-1, 31 - 29 + 1) then
|
| 760 |
|
|
sDigestHighBitsZero <= '1';
|
| 761 |
|
|
else
|
| 762 |
|
|
sDigestHighBitsZero <= '0';
|
| 763 |
|
|
end if;
|
| 764 |
|
|
end case;
|
| 765 |
|
|
|
| 766 |
|
|
if svDigestSignificant <= svTargetFraction(23 downto 0) then
|
| 767 |
|
|
sDigestSignificantFit <= '1';
|
| 768 |
|
|
else
|
| 769 |
|
|
sDigestSignificantFit <= '0';
|
| 770 |
|
|
end if;
|
| 771 |
|
|
end if;
|
| 772 |
|
|
end process;
|
| 773 |
|
|
|
| 774 |
|
|
process(iClkProcess)
|
| 775 |
|
|
begin
|
| 776 |
|
|
if rising_edge(iClkProcess) then
|
| 777 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 778 |
|
|
svCmpDelayCnt <= (others=>'0');
|
| 779 |
|
|
sCmpResultValid <= '0';
|
| 780 |
|
|
else
|
| 781 |
|
|
if sProcess = stSearch and svCmpDelayCnt < cCMP_DELAY then
|
| 782 |
|
|
svCmpDelayCnt <= svCmpDelayCnt + '1';
|
| 783 |
|
|
end if;
|
| 784 |
|
|
|
| 785 |
|
|
if sProcess = stSearch and svCmpDelayCnt = cCMP_DELAY then
|
| 786 |
|
|
sCmpResultValid <= '1';
|
| 787 |
|
|
else
|
| 788 |
|
|
sCmpResultValid <= '0';
|
| 789 |
|
|
end if;
|
| 790 |
|
|
end if;
|
| 791 |
|
|
end if;
|
| 792 |
|
|
end process;
|
| 793 |
|
|
|
| 794 |
|
|
process(iClkProcess)
|
| 795 |
|
|
begin
|
| 796 |
|
|
if rising_edge(iClkProcess) then
|
| 797 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 798 |
|
|
svCmpNounce <= svStartNonce;
|
| 799 |
|
|
elsif sCmpResultValid = '1' then
|
| 800 |
|
|
svCmpNounce <= svCmpNounce + '1';
|
| 801 |
|
|
end if;
|
| 802 |
|
|
end if;
|
| 803 |
|
|
end process;
|
| 804 |
|
|
|
| 805 |
|
|
process(iClkProcess)
|
| 806 |
|
|
begin
|
| 807 |
|
|
if rising_edge(iClkProcess) then
|
| 808 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 809 |
|
|
sReachEndToIdle <= '0';
|
| 810 |
|
|
else
|
| 811 |
|
|
if sProcess = stSearch and sCmpResultValid = '1' and svCmpNounce = svEndNonce then
|
| 812 |
|
|
sReachEndToIdle <= '1';
|
| 813 |
|
|
else
|
| 814 |
|
|
sReachEndToIdle <= '0';
|
| 815 |
|
|
end if;
|
| 816 |
|
|
end if;
|
| 817 |
|
|
end if;
|
| 818 |
|
|
end process;
|
| 819 |
|
|
|
| 820 |
|
|
process(iClkProcess)
|
| 821 |
|
|
begin
|
| 822 |
|
|
if rising_edge(iClkProcess) then
|
| 823 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 824 |
|
|
oReachEnd <= '0';
|
| 825 |
|
|
else
|
| 826 |
|
|
if sProcess = stSearch and sReachEndToIdle = '1' and sFoundNonceToIdle = '0' then
|
| 827 |
|
|
oReachEnd <= '1';
|
| 828 |
|
|
else
|
| 829 |
|
|
oReachEnd <= '0';
|
| 830 |
|
|
end if;
|
| 831 |
|
|
end if;
|
| 832 |
|
|
end if;
|
| 833 |
|
|
end process;
|
| 834 |
|
|
|
| 835 |
|
|
process(iClkProcess)
|
| 836 |
|
|
begin
|
| 837 |
|
|
if rising_edge(iClkProcess) then
|
| 838 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 839 |
|
|
sFoundNonceToIdle <= '0';
|
| 840 |
|
|
else
|
| 841 |
|
|
if sProcess = stSearch and sCmpResultValid = '1' and sDigestHighBitsZero = '1' and sDigestSignificantFit = '1' then
|
| 842 |
|
|
sFoundNonceToIdle <= '1';
|
| 843 |
|
|
else
|
| 844 |
|
|
sFoundNonceToIdle <= '0';
|
| 845 |
|
|
end if;
|
| 846 |
|
|
end if;
|
| 847 |
|
|
end if;
|
| 848 |
|
|
end process;
|
| 849 |
|
|
|
| 850 |
|
|
process(iClkProcess)
|
| 851 |
|
|
begin
|
| 852 |
|
|
if rising_edge(iClkProcess) then
|
| 853 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 854 |
|
|
oFoundNonce <= '0';
|
| 855 |
|
|
else
|
| 856 |
|
|
if sProcess = stSearch and sFoundNonceToIdle = '1' then
|
| 857 |
|
|
oFoundNonce <= '1';
|
| 858 |
|
|
else
|
| 859 |
|
|
oFoundNonce <= '0';
|
| 860 |
|
|
end if;
|
| 861 |
|
|
end if;
|
| 862 |
|
|
end if;
|
| 863 |
|
|
end process;
|
| 864 |
|
|
|
| 865 |
|
|
pipelines_without_reset_inst_Nonce : pipelines_without_reset
|
| 866 |
|
|
GENERIC map(gBUS_WIDTH => 32, gNB_PIPELINES => 2)
|
| 867 |
|
|
PORT map(
|
| 868 |
|
|
iClk => iClkProcess,
|
| 869 |
|
|
iInput => '0',
|
| 870 |
|
|
ivInput => svCmpNounce,
|
| 871 |
|
|
oDelayed_output => open,
|
| 872 |
|
|
ovDelayed_output => ovNonce
|
| 873 |
|
|
);
|
| 874 |
|
|
|
| 875 |
|
|
end behavioral;
|
