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nuxi1209 |
-------------------------------------------------------------------
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-- --
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-- Copyright (C) 2013 Author and VariStream Studio --
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-- Author : Yu Peng --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer. --
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-- --
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-- This source file is free software; you can redistribute it --
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-- and/or modify it under the terms of the GNU Lesser General --
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-- Public License as published by the Free Software Foundation; --
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-- either version 2.1 of the License, or (at your option) any --
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-- later version. --
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-- --
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-- This source is distributed in the hope that it will be --
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-- useful, but WITHOUT ANY WARRANTY; without even the implied --
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
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-- PURPOSE. See the GNU Lesser General Public License for more --
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-- details. --
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-- --
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-- You should have received a copy of the GNU Lesser General --
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-- Public License along with this source; if not, download it --
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-- from http://www.opencores.org/lgpl.shtml --
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-- --
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-------------------------------------------------------------------
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2 |
nuxi1209 |
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.NUMERIC_STD.all;
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use work.sha_256_pkg.ALL;
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entity sha_256_chunk is
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generic(
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gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
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gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'0');
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gBASE_DELAY : integer := 3;
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gOUT_VALID_GEN : boolean := false;
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gUSE_BRAM_AS_LARGE_SHIFTREG : boolean := false
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);
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port(
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iClk : in std_logic := '0';
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iRst_async : in std_logic := '0';
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iValid : in std_logic := '0';
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ivMsgDword : in tDwordArray(0 to 15) := (others=>(others=>'0'));
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ivH0 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH1 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH2 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH3 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH4 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH5 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH6 : in std_logic_vector(31 downto 0) := (others=>'0');
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ivH7 : in std_logic_vector(31 downto 0) := (others=>'0');
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ovH0 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH1 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH2 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH3 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH4 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH5 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH6 : out std_logic_vector(31 downto 0) := (others=>'0');
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ovH7 : out std_logic_vector(31 downto 0) := (others=>'0');
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oValid : out std_logic := '0'
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);
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end sha_256_chunk;
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architecture behavioral of sha_256_chunk is
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component pipelines_without_reset IS
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GENERIC (gBUS_WIDTH : integer := 3; gNB_PIPELINES: integer range 1 to 255 := 2);
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PORT(
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iClk : IN STD_LOGIC;
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iInput : IN STD_LOGIC;
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ivInput : IN STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);
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oDelayed_output : OUT STD_LOGIC;
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ovDelayed_output : OUT STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)
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);
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end component;
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component SyncReset is
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port(
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iClk : in std_logic; -- Clock domain that the reset should be resynchronyze to
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iAsyncReset : in std_logic; -- Asynchronous reset that should be resynchronyse
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oSyncReset : out std_logic -- Synchronous reset output
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);
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end component;
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component sync_fifo_infer is
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generic (
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gADDRESS_WIDTH : integer range 4 to (integer'HIGH) := 5;
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gDATA_WIDTH : integer := 24;
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gDYNAMIC_PROG_FULL_TH : boolean := false;
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gDYNAMIC_PROG_EMPTY_TH : boolean := false;
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gOUTPUT_PIPELINE_NUM : integer range 1 to (integer'HIGH) := 1
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);
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port(
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iClk : in std_logic := '0';
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iReset_sync : in std_logic := '0';
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ivProgFullTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2**gADDRESS_WIDTH-3, gADDRESS_WIDTH);
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ivProgEmptyTh : in std_logic_vector(gADDRESS_WIDTH-1 downto 0) := conv_std_logic_vector(2, gADDRESS_WIDTH);
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iWrEn : in std_logic := '0';
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iRdEn : in std_logic := '0';
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ivDataIn : in std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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ovDataOut : out std_logic_vector(gDATA_WIDTH-1 downto 0) := (others=>'0');
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oDataOutValid : out std_logic := '0';
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oFull : out std_logic := '0';
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oEmpty : out std_logic := '1';
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oAlmostFull : out std_logic := '0';
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oAlmostEmpty : out std_logic := '1';
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oProgFull : out std_logic := '0';
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oProgEmpty : out std_logic := '1';
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oOverflow : out std_logic := '0';
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oUnderflow : out std_logic := '0'
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);
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end component;
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component sha_256_ext_func is
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port(
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iClk : in std_logic;
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iRst_async : in std_logic;
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ivWIM2 : in std_logic_vector(31 downto 0);
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ivWIM7 : in std_logic_vector(31 downto 0);
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ivWIM15 : in std_logic_vector(31 downto 0);
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ivWIM16 : in std_logic_vector(31 downto 0);
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ovWO : out std_logic_vector(31 downto 0)
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);
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end component;
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component sha_256_ext_func_1c is
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port(
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iClk : in std_logic;
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iRst_async : in std_logic;
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ivWIM2 : in std_logic_vector(31 downto 0);
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ivWIM7 : in std_logic_vector(31 downto 0);
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ivWIM15 : in std_logic_vector(31 downto 0);
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ivWIM16 : in std_logic_vector(31 downto 0);
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ovWO : out std_logic_vector(31 downto 0)
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);
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end component;
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component sha_256_comp_func is
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port(
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iClk : in std_logic;
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iRst_async : in std_logic;
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ivA : in std_logic_vector(31 downto 0);
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ivB : in std_logic_vector(31 downto 0);
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ivC : in std_logic_vector(31 downto 0);
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ivD : in std_logic_vector(31 downto 0);
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ivE : in std_logic_vector(31 downto 0);
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ivF : in std_logic_vector(31 downto 0);
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ivG : in std_logic_vector(31 downto 0);
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ivH : in std_logic_vector(31 downto 0);
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ivK : in std_logic_vector(31 downto 0);
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ivW : in std_logic_vector(31 downto 0);
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ovA : out std_logic_vector(31 downto 0);
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ovB : out std_logic_vector(31 downto 0);
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ovC : out std_logic_vector(31 downto 0);
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ovD : out std_logic_vector(31 downto 0);
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ovE : out std_logic_vector(31 downto 0);
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ovF : out std_logic_vector(31 downto 0);
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ovG : out std_logic_vector(31 downto 0);
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ovH : out std_logic_vector(31 downto 0)
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);
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end component;
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component sha_256_comp_func_1c is
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port(
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iClk : in std_logic;
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iRst_async : in std_logic;
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ivA : in std_logic_vector(31 downto 0);
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ivB : in std_logic_vector(31 downto 0);
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ivC : in std_logic_vector(31 downto 0);
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ivD : in std_logic_vector(31 downto 0);
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ivE : in std_logic_vector(31 downto 0);
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ivF : in std_logic_vector(31 downto 0);
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ivG : in std_logic_vector(31 downto 0);
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ivH : in std_logic_vector(31 downto 0);
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ivK : in std_logic_vector(31 downto 0);
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ivW : in std_logic_vector(31 downto 0);
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ovA : out std_logic_vector(31 downto 0);
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ovB : out std_logic_vector(31 downto 0);
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ovC : out std_logic_vector(31 downto 0);
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ovD : out std_logic_vector(31 downto 0);
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ovE : out std_logic_vector(31 downto 0);
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ovF : out std_logic_vector(31 downto 0);
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ovG : out std_logic_vector(31 downto 0);
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ovH : out std_logic_vector(31 downto 0)
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);
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end component;
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constant cvK : tDwordArray(0 to 63) := (
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X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5", X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
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X"d807aa98", X"12835b01", X"243185be", X"550c7dc3", X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
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X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc", X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
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X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7", X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
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X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13", X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
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X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3", X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
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X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5", X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
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X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208", X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2");
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constant cvW_IS_CONST : std_logic_vector(0 to 63) := getW_IS_CONST(gMSG_IS_CONSTANT);
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type tDword2DArrayRow64Col64 is array(0 to 63) of tDwordArray(0 to 63);
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signal svResetHShiftFifo_sync : std_logic_vector(0 to 7) := (others=>'0');
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signal svH0 : std_logic_vector(31 downto 0) := (others=>'0');
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signal svH1 : std_logic_vector(31 downto 0) := (others=>'0');
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signal svH2 : std_logic_vector(31 downto 0) := (others=>'0');
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signal svH3 : std_logic_vector(31 downto 0) := (others=>'0');
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signal svH4 : std_logic_vector(31 downto 0) := (others=>'0');
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signal svH5 : std_logic_vector(31 downto 0) := (others=>'0');
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signal svH6 : std_logic_vector(31 downto 0) := (others=>'0');
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signal svH7 : std_logic_vector(31 downto 0) := (others=>'0');
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signal sHShiftFifoRdEn : std_logic := '0';
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signal svAPipe : tDwordArray(0 to 64) := (others=>(others=>'0'));
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signal svBPipe : tDwordArray(0 to 64) := (others=>(others=>'0'));
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signal svCPipe : tDwordArray(0 to 64) := (others=>(others=>'0'));
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signal svDPipe : tDwordArray(0 to 64) := (others=>(others=>'0'));
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signal svEPipe : tDwordArray(0 to 64) := (others=>(others=>'0'));
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signal svFPipe : tDwordArray(0 to 64) := (others=>(others=>'0'));
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signal svGPipe : tDwordArray(0 to 64) := (others=>(others=>'0'));
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signal svHPipe : tDwordArray(0 to 64) := (others=>(others=>'0'));
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signal svW : tDword2DArrayRow64Col64 := (others=>(others=>(others=>'0')));
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begin
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-- Description of Algorithm
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-- for i in 16 to 63 loop
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-- s0 := (w[i-15] rightrotate 7) xor (w[i-15] rightrotate 18) xor (w[i-15] rightshift 3)
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-- s1 := (w[i-2] rightrotate 17) xor (w[i-2] rightrotate 19) xor (w[i-2] rightshift 10)
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-- w[i] := w[i-16] + s0 + w[i-7] + s1
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-- end loop
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W_col_00_gen : for row in 0 to 15 generate
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svW(row)(0) <= ivMsgDword(row);
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end generate;
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W_01_to_15_gen_row : for row in 1 to 15 generate
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W_01_to_15_gen_col : for col in 1 to row generate
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W_01_to_15_gen_const : if cvW_IS_CONST(row) = '1' generate
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| 265 |
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svW(row)(col) <= svW(row)(col - 1);
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end generate;
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| 267 |
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| 268 |
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W_01_to_15_gen_var : if cvW_IS_CONST(row) = '0' generate
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| 269 |
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pipelines_without_reset_inst: pipelines_without_reset
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| 270 |
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GENERIC map(
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| 271 |
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gBUS_WIDTH => 32,
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| 272 |
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gNB_PIPELINES => gBASE_DELAY)
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| 273 |
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PORT map(
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iClk => iClk,
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iInput => '0',
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| 276 |
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oDelayed_output => open,
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| 277 |
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ivInput => svW(row)(col - 1),
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ovDelayed_output => svW(row)(col)
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| 279 |
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);
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end generate;
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end generate;
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| 282 |
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end generate;
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| 283 |
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|
|
W_16_to_63_gen_row : for row in 16 to 63 generate
|
| 285 |
|
|
W_16_to_63_gen_col : for col in (row - 15) to row generate
|
| 286 |
|
|
W_16_to_63_gen_const : if cvW_IS_CONST(row) = '1' generate
|
| 287 |
|
|
W_16_to_63_gen_const_first : if col = (row - 15) generate
|
| 288 |
|
|
svW(row)(col) <= svW(row - 16)(col - 1) + sigma_0(svW(row - 15)(col - 1)) + svW(row - 7)(col - 1) + sigma_1(svW(row - 2)(col - 1));
|
| 289 |
|
|
end generate;
|
| 290 |
|
|
|
| 291 |
|
|
W_16_to_63_gen_const_rest : if col > (row - 15) generate
|
| 292 |
|
|
svW(row)(col) <= svW(row)(col - 1);
|
| 293 |
|
|
end generate;
|
| 294 |
|
|
end generate;
|
| 295 |
|
|
|
| 296 |
|
|
W_16_to_63_gen_var : if cvW_IS_CONST(row) = '0' generate
|
| 297 |
|
|
W_16_to_63_gen_var_first : if col = (row - 15) generate
|
| 298 |
|
|
W_16_to_63_gen_var_first_3c : if gBASE_DELAY = 3 generate
|
| 299 |
|
|
sha_256_ext_func_inst: sha_256_ext_func
|
| 300 |
|
|
port map(
|
| 301 |
|
|
iClk => iClk,
|
| 302 |
|
|
iRst_async => iRst_async,
|
| 303 |
|
|
|
| 304 |
|
|
ivWIM2 => svW(row-2)(col - 1),
|
| 305 |
|
|
ivWIM7 => svW(row-7)(col - 1),
|
| 306 |
|
|
ivWIM15 => svW(row-15)(col - 1),
|
| 307 |
|
|
ivWIM16 => svW(row-16)(col - 1),
|
| 308 |
|
|
|
| 309 |
|
|
ovWO => svW(row)(col)
|
| 310 |
|
|
);
|
| 311 |
|
|
end generate;
|
| 312 |
|
|
|
| 313 |
|
|
W_16_to_63_gen_var_first_1c : if gBASE_DELAY = 1 generate
|
| 314 |
|
|
sha_256_ext_func_inst: sha_256_ext_func_1c
|
| 315 |
|
|
port map(
|
| 316 |
|
|
iClk => iClk,
|
| 317 |
|
|
iRst_async => iRst_async,
|
| 318 |
|
|
|
| 319 |
|
|
ivWIM2 => svW(row-2)(col - 1),
|
| 320 |
|
|
ivWIM7 => svW(row-7)(col - 1),
|
| 321 |
|
|
ivWIM15 => svW(row-15)(col - 1),
|
| 322 |
|
|
ivWIM16 => svW(row-16)(col - 1),
|
| 323 |
|
|
|
| 324 |
|
|
ovWO => svW(row)(col)
|
| 325 |
|
|
);
|
| 326 |
|
|
end generate;
|
| 327 |
|
|
end generate;
|
| 328 |
|
|
|
| 329 |
|
|
W_16_to_63_gen_var_rest : if col > (row - 15) generate
|
| 330 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 331 |
|
|
GENERIC map(
|
| 332 |
|
|
gBUS_WIDTH => 32,
|
| 333 |
|
|
gNB_PIPELINES => gBASE_DELAY)
|
| 334 |
|
|
PORT map(
|
| 335 |
|
|
iClk => iClk,
|
| 336 |
|
|
iInput => '0',
|
| 337 |
|
|
oDelayed_output => open,
|
| 338 |
|
|
ivInput => svW(row)(col - 1),
|
| 339 |
|
|
ovDelayed_output => svW(row)(col)
|
| 340 |
|
|
);
|
| 341 |
|
|
end generate;
|
| 342 |
|
|
end generate;
|
| 343 |
|
|
end generate;
|
| 344 |
|
|
end generate;
|
| 345 |
|
|
|
| 346 |
|
|
svAPipe(0) <= ivH0;
|
| 347 |
|
|
svBPipe(0) <= ivH1;
|
| 348 |
|
|
svCPipe(0) <= ivH2;
|
| 349 |
|
|
svDPipe(0) <= ivH3;
|
| 350 |
|
|
svEPipe(0) <= ivH4;
|
| 351 |
|
|
svFPipe(0) <= ivH5;
|
| 352 |
|
|
svGPipe(0) <= ivH6;
|
| 353 |
|
|
svHPipe(0) <= ivH7;
|
| 354 |
|
|
|
| 355 |
|
|
loop_gen : for i in 0 to 63 generate
|
| 356 |
|
|
loo_gen_3c : if gBASE_DELAY = 3 generate
|
| 357 |
|
|
sha_256_comp_func_inst : sha_256_comp_func
|
| 358 |
|
|
port map(
|
| 359 |
|
|
iClk => iClk,
|
| 360 |
|
|
iRst_async => iRst_async,
|
| 361 |
|
|
|
| 362 |
|
|
ivA => svAPipe(i),
|
| 363 |
|
|
ivB => svBPipe(i),
|
| 364 |
|
|
ivC => svCPipe(i),
|
| 365 |
|
|
ivD => svDPipe(i),
|
| 366 |
|
|
ivE => svEPipe(i),
|
| 367 |
|
|
ivF => svFPipe(i),
|
| 368 |
|
|
ivG => svGPipe(i),
|
| 369 |
|
|
ivH => svHPipe(i),
|
| 370 |
|
|
|
| 371 |
|
|
ivK => cvK(i),
|
| 372 |
|
|
ivW => svW(i)(i),
|
| 373 |
|
|
|
| 374 |
|
|
ovA => svAPipe(i + 1),
|
| 375 |
|
|
ovB => svBPipe(i + 1),
|
| 376 |
|
|
ovC => svCPipe(i + 1),
|
| 377 |
|
|
ovD => svDPipe(i + 1),
|
| 378 |
|
|
ovE => svEPipe(i + 1),
|
| 379 |
|
|
ovF => svFPipe(i + 1),
|
| 380 |
|
|
ovG => svGPipe(i + 1),
|
| 381 |
|
|
ovH => svHPipe(i + 1)
|
| 382 |
|
|
);
|
| 383 |
|
|
end generate;
|
| 384 |
|
|
|
| 385 |
|
|
loo_gen_1c : if gBASE_DELAY = 1 generate
|
| 386 |
|
|
sha_256_comp_func_inst : sha_256_comp_func_1c
|
| 387 |
|
|
port map(
|
| 388 |
|
|
iClk => iClk,
|
| 389 |
|
|
iRst_async => iRst_async,
|
| 390 |
|
|
|
| 391 |
|
|
ivA => svAPipe(i),
|
| 392 |
|
|
ivB => svBPipe(i),
|
| 393 |
|
|
ivC => svCPipe(i),
|
| 394 |
|
|
ivD => svDPipe(i),
|
| 395 |
|
|
ivE => svEPipe(i),
|
| 396 |
|
|
ivF => svFPipe(i),
|
| 397 |
|
|
ivG => svGPipe(i),
|
| 398 |
|
|
ivH => svHPipe(i),
|
| 399 |
|
|
|
| 400 |
|
|
ivK => cvK(i),
|
| 401 |
|
|
ivW => svW(i)(i),
|
| 402 |
|
|
|
| 403 |
|
|
ovA => svAPipe(i + 1),
|
| 404 |
|
|
ovB => svBPipe(i + 1),
|
| 405 |
|
|
ovC => svCPipe(i + 1),
|
| 406 |
|
|
ovD => svDPipe(i + 1),
|
| 407 |
|
|
ovE => svEPipe(i + 1),
|
| 408 |
|
|
ovF => svFPipe(i + 1),
|
| 409 |
|
|
ovG => svGPipe(i + 1),
|
| 410 |
|
|
ovH => svHPipe(i + 1)
|
| 411 |
|
|
);
|
| 412 |
|
|
end generate;
|
| 413 |
|
|
end generate;
|
| 414 |
|
|
|
| 415 |
|
|
H0_gen_const : if gH_IS_CONST(0) = '1' generate
|
| 416 |
|
|
svH0 <= ivH0;
|
| 417 |
|
|
end generate;
|
| 418 |
|
|
|
| 419 |
|
|
H1_gen_const : if gH_IS_CONST(1) = '1' generate
|
| 420 |
|
|
svH1 <= ivH1;
|
| 421 |
|
|
end generate;
|
| 422 |
|
|
|
| 423 |
|
|
H2_gen_const : if gH_IS_CONST(2) = '1' generate
|
| 424 |
|
|
svH2 <= ivH2;
|
| 425 |
|
|
end generate;
|
| 426 |
|
|
|
| 427 |
|
|
H3_gen_const : if gH_IS_CONST(3) = '1' generate
|
| 428 |
|
|
svH3 <= ivH3;
|
| 429 |
|
|
end generate;
|
| 430 |
|
|
|
| 431 |
|
|
H4_gen_const : if gH_IS_CONST(4) = '1' generate
|
| 432 |
|
|
svH4 <= ivH4;
|
| 433 |
|
|
end generate;
|
| 434 |
|
|
|
| 435 |
|
|
H5_gen_const : if gH_IS_CONST(5) = '1' generate
|
| 436 |
|
|
svH5 <= ivH5;
|
| 437 |
|
|
end generate;
|
| 438 |
|
|
|
| 439 |
|
|
H6_gen_const : if gH_IS_CONST(6) = '1' generate
|
| 440 |
|
|
svH6 <= ivH6;
|
| 441 |
|
|
end generate;
|
| 442 |
|
|
|
| 443 |
|
|
H7_gen_const : if gH_IS_CONST(7) = '1' generate
|
| 444 |
|
|
svH7 <= ivH7;
|
| 445 |
|
|
end generate;
|
| 446 |
|
|
|
| 447 |
|
|
HShiftFifoRdEn_gen : if gUSE_BRAM_AS_LARGE_SHIFTREG = true generate
|
| 448 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 449 |
|
|
GENERIC map(
|
| 450 |
|
|
gBUS_WIDTH => 1,
|
| 451 |
|
|
gNB_PIPELINES => (64 * gBASE_DELAY - 1) )
|
| 452 |
|
|
PORT map(
|
| 453 |
|
|
iClk => iClk,
|
| 454 |
|
|
iInput => iValid,
|
| 455 |
|
|
oDelayed_output => sHShiftFifoRdEn,
|
| 456 |
|
|
ivInput => (others=>'0'),
|
| 457 |
|
|
ovDelayed_output => open
|
| 458 |
|
|
);
|
| 459 |
|
|
end generate;
|
| 460 |
|
|
|
| 461 |
|
|
H0_gen_var : if gH_IS_CONST(0) = '0' generate
|
| 462 |
|
|
H0_gen_var_shiftreg : if gUSE_BRAM_AS_LARGE_SHIFTREG = false generate
|
| 463 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 464 |
|
|
GENERIC map(
|
| 465 |
|
|
gBUS_WIDTH => 32,
|
| 466 |
|
|
gNB_PIPELINES => 64 * gBASE_DELAY)
|
| 467 |
|
|
PORT map(
|
| 468 |
|
|
iClk => iClk,
|
| 469 |
|
|
iInput => '0',
|
| 470 |
|
|
oDelayed_output => open,
|
| 471 |
|
|
ivInput => ivH0,
|
| 472 |
|
|
ovDelayed_output => svH0
|
| 473 |
|
|
);
|
| 474 |
|
|
end generate;
|
| 475 |
|
|
|
| 476 |
|
|
H0_gen_var_bram : if gUSE_BRAM_AS_LARGE_SHIFTREG = true generate
|
| 477 |
|
|
SyncReset_inst : SyncReset
|
| 478 |
|
|
port map(
|
| 479 |
|
|
iClk => iClk,
|
| 480 |
|
|
iAsyncReset => iRst_async,
|
| 481 |
|
|
oSyncReset => svResetHShiftFifo_sync(0)
|
| 482 |
|
|
);
|
| 483 |
|
|
|
| 484 |
|
|
sync_fifo_infer_inst : sync_fifo_infer
|
| 485 |
|
|
generic map(
|
| 486 |
|
|
gADDRESS_WIDTH => 8,
|
| 487 |
|
|
gDATA_WIDTH => 32
|
| 488 |
|
|
)
|
| 489 |
|
|
port map(
|
| 490 |
|
|
iClk => iClk,
|
| 491 |
|
|
iReset_sync => svResetHShiftFifo_sync(0),
|
| 492 |
|
|
|
| 493 |
|
|
ivProgFullTh => conv_std_logic_vector(2**8-3, 8),
|
| 494 |
|
|
ivProgEmptyTh => conv_std_logic_vector(2, 8),
|
| 495 |
|
|
|
| 496 |
|
|
iWrEn => iValid,
|
| 497 |
|
|
iRdEn => sHShiftFifoRdEn,
|
| 498 |
|
|
ivDataIn => ivH0,
|
| 499 |
|
|
ovDataOut => svH0,
|
| 500 |
|
|
oDataOutValid => open,
|
| 501 |
|
|
|
| 502 |
|
|
oFull => open,
|
| 503 |
|
|
oEmpty => open,
|
| 504 |
|
|
oAlmostFull => open,
|
| 505 |
|
|
oAlmostEmpty => open,
|
| 506 |
|
|
oProgFull => open,
|
| 507 |
|
|
oProgEmpty => open,
|
| 508 |
|
|
|
| 509 |
|
|
oOverflow => open,
|
| 510 |
|
|
oUnderflow => open
|
| 511 |
|
|
);
|
| 512 |
|
|
end generate;
|
| 513 |
|
|
end generate;
|
| 514 |
|
|
|
| 515 |
|
|
H1_gen_var : if gH_IS_CONST(1) = '0' generate
|
| 516 |
|
|
H1_gen_var_shiftreg : if gUSE_BRAM_AS_LARGE_SHIFTREG = false generate
|
| 517 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 518 |
|
|
GENERIC map(
|
| 519 |
|
|
gBUS_WIDTH => 32,
|
| 520 |
|
|
gNB_PIPELINES => 64 * gBASE_DELAY)
|
| 521 |
|
|
PORT map(
|
| 522 |
|
|
iClk => iClk,
|
| 523 |
|
|
iInput => '0',
|
| 524 |
|
|
oDelayed_output => open,
|
| 525 |
|
|
ivInput => ivH1,
|
| 526 |
|
|
ovDelayed_output => svH1
|
| 527 |
|
|
);
|
| 528 |
|
|
end generate;
|
| 529 |
|
|
|
| 530 |
|
|
H1_gen_var_bram : if gUSE_BRAM_AS_LARGE_SHIFTREG = true generate
|
| 531 |
|
|
SyncReset_inst : SyncReset
|
| 532 |
|
|
port map(
|
| 533 |
|
|
iClk => iClk,
|
| 534 |
|
|
iAsyncReset => iRst_async,
|
| 535 |
|
|
oSyncReset => svResetHShiftFifo_sync(1)
|
| 536 |
|
|
);
|
| 537 |
|
|
|
| 538 |
|
|
sync_fifo_infer_inst : sync_fifo_infer
|
| 539 |
|
|
generic map(
|
| 540 |
|
|
gADDRESS_WIDTH => 8,
|
| 541 |
|
|
gDATA_WIDTH => 32
|
| 542 |
|
|
)
|
| 543 |
|
|
port map(
|
| 544 |
|
|
iClk => iClk,
|
| 545 |
|
|
iReset_sync => svResetHShiftFifo_sync(1),
|
| 546 |
|
|
|
| 547 |
|
|
ivProgFullTh => conv_std_logic_vector(2**8-3, 8),
|
| 548 |
|
|
ivProgEmptyTh => conv_std_logic_vector(2, 8),
|
| 549 |
|
|
|
| 550 |
|
|
iWrEn => iValid,
|
| 551 |
|
|
iRdEn => sHShiftFifoRdEn,
|
| 552 |
|
|
ivDataIn => ivH1,
|
| 553 |
|
|
ovDataOut => svH1,
|
| 554 |
|
|
oDataOutValid => open,
|
| 555 |
|
|
|
| 556 |
|
|
oFull => open,
|
| 557 |
|
|
oEmpty => open,
|
| 558 |
|
|
oAlmostFull => open,
|
| 559 |
|
|
oAlmostEmpty => open,
|
| 560 |
|
|
oProgFull => open,
|
| 561 |
|
|
oProgEmpty => open,
|
| 562 |
|
|
|
| 563 |
|
|
oOverflow => open,
|
| 564 |
|
|
oUnderflow => open
|
| 565 |
|
|
);
|
| 566 |
|
|
end generate;
|
| 567 |
|
|
end generate;
|
| 568 |
|
|
|
| 569 |
|
|
H2_gen_var : if gH_IS_CONST(2) = '0' generate
|
| 570 |
|
|
H2_gen_var_shiftreg : if gUSE_BRAM_AS_LARGE_SHIFTREG = false generate
|
| 571 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 572 |
|
|
GENERIC map(
|
| 573 |
|
|
gBUS_WIDTH => 32,
|
| 574 |
|
|
gNB_PIPELINES => 64 * gBASE_DELAY)
|
| 575 |
|
|
PORT map(
|
| 576 |
|
|
iClk => iClk,
|
| 577 |
|
|
iInput => '0',
|
| 578 |
|
|
oDelayed_output => open,
|
| 579 |
|
|
ivInput => ivH2,
|
| 580 |
|
|
ovDelayed_output => svH2
|
| 581 |
|
|
);
|
| 582 |
|
|
end generate;
|
| 583 |
|
|
|
| 584 |
|
|
H2_gen_var_bram : if gUSE_BRAM_AS_LARGE_SHIFTREG = true generate
|
| 585 |
|
|
SyncReset_inst : SyncReset
|
| 586 |
|
|
port map(
|
| 587 |
|
|
iClk => iClk,
|
| 588 |
|
|
iAsyncReset => iRst_async,
|
| 589 |
|
|
oSyncReset => svResetHShiftFifo_sync(2)
|
| 590 |
|
|
);
|
| 591 |
|
|
|
| 592 |
|
|
sync_fifo_infer_inst : sync_fifo_infer
|
| 593 |
|
|
generic map(
|
| 594 |
|
|
gADDRESS_WIDTH => 8,
|
| 595 |
|
|
gDATA_WIDTH => 32
|
| 596 |
|
|
)
|
| 597 |
|
|
port map(
|
| 598 |
|
|
iClk => iClk,
|
| 599 |
|
|
iReset_sync => svResetHShiftFifo_sync(2),
|
| 600 |
|
|
|
| 601 |
|
|
ivProgFullTh => conv_std_logic_vector(2**8-3, 8),
|
| 602 |
|
|
ivProgEmptyTh => conv_std_logic_vector(2, 8),
|
| 603 |
|
|
|
| 604 |
|
|
iWrEn => iValid,
|
| 605 |
|
|
iRdEn => sHShiftFifoRdEn,
|
| 606 |
|
|
ivDataIn => ivH2,
|
| 607 |
|
|
ovDataOut => svH2,
|
| 608 |
|
|
oDataOutValid => open,
|
| 609 |
|
|
|
| 610 |
|
|
oFull => open,
|
| 611 |
|
|
oEmpty => open,
|
| 612 |
|
|
oAlmostFull => open,
|
| 613 |
|
|
oAlmostEmpty => open,
|
| 614 |
|
|
oProgFull => open,
|
| 615 |
|
|
oProgEmpty => open,
|
| 616 |
|
|
|
| 617 |
|
|
oOverflow => open,
|
| 618 |
|
|
oUnderflow => open
|
| 619 |
|
|
);
|
| 620 |
|
|
end generate;
|
| 621 |
|
|
end generate;
|
| 622 |
|
|
|
| 623 |
|
|
H3_gen_var : if gH_IS_CONST(3) = '0' generate
|
| 624 |
|
|
H3_gen_var_shiftreg : if gUSE_BRAM_AS_LARGE_SHIFTREG = false generate
|
| 625 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 626 |
|
|
GENERIC map(
|
| 627 |
|
|
gBUS_WIDTH => 32,
|
| 628 |
|
|
gNB_PIPELINES => 64 * gBASE_DELAY)
|
| 629 |
|
|
PORT map(
|
| 630 |
|
|
iClk => iClk,
|
| 631 |
|
|
iInput => '0',
|
| 632 |
|
|
oDelayed_output => open,
|
| 633 |
|
|
ivInput => ivH3,
|
| 634 |
|
|
ovDelayed_output => svH3
|
| 635 |
|
|
);
|
| 636 |
|
|
end generate;
|
| 637 |
|
|
|
| 638 |
|
|
H3_gen_var_bram : if gUSE_BRAM_AS_LARGE_SHIFTREG = true generate
|
| 639 |
|
|
SyncReset_inst : SyncReset
|
| 640 |
|
|
port map(
|
| 641 |
|
|
iClk => iClk,
|
| 642 |
|
|
iAsyncReset => iRst_async,
|
| 643 |
|
|
oSyncReset => svResetHShiftFifo_sync(3)
|
| 644 |
|
|
);
|
| 645 |
|
|
|
| 646 |
|
|
sync_fifo_infer_inst : sync_fifo_infer
|
| 647 |
|
|
generic map(
|
| 648 |
|
|
gADDRESS_WIDTH => 8,
|
| 649 |
|
|
gDATA_WIDTH => 32
|
| 650 |
|
|
)
|
| 651 |
|
|
port map(
|
| 652 |
|
|
iClk => iClk,
|
| 653 |
|
|
iReset_sync => svResetHShiftFifo_sync(3),
|
| 654 |
|
|
|
| 655 |
|
|
ivProgFullTh => conv_std_logic_vector(2**8-3, 8),
|
| 656 |
|
|
ivProgEmptyTh => conv_std_logic_vector(2, 8),
|
| 657 |
|
|
|
| 658 |
|
|
iWrEn => iValid,
|
| 659 |
|
|
iRdEn => sHShiftFifoRdEn,
|
| 660 |
|
|
ivDataIn => ivH3,
|
| 661 |
|
|
ovDataOut => svH3,
|
| 662 |
|
|
oDataOutValid => open,
|
| 663 |
|
|
|
| 664 |
|
|
oFull => open,
|
| 665 |
|
|
oEmpty => open,
|
| 666 |
|
|
oAlmostFull => open,
|
| 667 |
|
|
oAlmostEmpty => open,
|
| 668 |
|
|
oProgFull => open,
|
| 669 |
|
|
oProgEmpty => open,
|
| 670 |
|
|
|
| 671 |
|
|
oOverflow => open,
|
| 672 |
|
|
oUnderflow => open
|
| 673 |
|
|
);
|
| 674 |
|
|
end generate;
|
| 675 |
|
|
end generate;
|
| 676 |
|
|
|
| 677 |
|
|
H4_gen_var : if gH_IS_CONST(4) = '0' generate
|
| 678 |
|
|
H4_gen_var_shiftreg : if gUSE_BRAM_AS_LARGE_SHIFTREG = false generate
|
| 679 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 680 |
|
|
GENERIC map(
|
| 681 |
|
|
gBUS_WIDTH => 32,
|
| 682 |
|
|
gNB_PIPELINES => 64 * gBASE_DELAY)
|
| 683 |
|
|
PORT map(
|
| 684 |
|
|
iClk => iClk,
|
| 685 |
|
|
iInput => '0',
|
| 686 |
|
|
oDelayed_output => open,
|
| 687 |
|
|
ivInput => ivH4,
|
| 688 |
|
|
ovDelayed_output => svH4
|
| 689 |
|
|
);
|
| 690 |
|
|
end generate;
|
| 691 |
|
|
|
| 692 |
|
|
H4_gen_var_bram : if gUSE_BRAM_AS_LARGE_SHIFTREG = true generate
|
| 693 |
|
|
SyncReset_inst : SyncReset
|
| 694 |
|
|
port map(
|
| 695 |
|
|
iClk => iClk,
|
| 696 |
|
|
iAsyncReset => iRst_async,
|
| 697 |
|
|
oSyncReset => svResetHShiftFifo_sync(4)
|
| 698 |
|
|
);
|
| 699 |
|
|
|
| 700 |
|
|
sync_fifo_infer_inst : sync_fifo_infer
|
| 701 |
|
|
generic map(
|
| 702 |
|
|
gADDRESS_WIDTH => 8,
|
| 703 |
|
|
gDATA_WIDTH => 32
|
| 704 |
|
|
)
|
| 705 |
|
|
port map(
|
| 706 |
|
|
iClk => iClk,
|
| 707 |
|
|
iReset_sync => svResetHShiftFifo_sync(4),
|
| 708 |
|
|
|
| 709 |
|
|
ivProgFullTh => conv_std_logic_vector(2**8-3, 8),
|
| 710 |
|
|
ivProgEmptyTh => conv_std_logic_vector(2, 8),
|
| 711 |
|
|
|
| 712 |
|
|
iWrEn => iValid,
|
| 713 |
|
|
iRdEn => sHShiftFifoRdEn,
|
| 714 |
|
|
ivDataIn => ivH4,
|
| 715 |
|
|
ovDataOut => svH4,
|
| 716 |
|
|
oDataOutValid => open,
|
| 717 |
|
|
|
| 718 |
|
|
oFull => open,
|
| 719 |
|
|
oEmpty => open,
|
| 720 |
|
|
oAlmostFull => open,
|
| 721 |
|
|
oAlmostEmpty => open,
|
| 722 |
|
|
oProgFull => open,
|
| 723 |
|
|
oProgEmpty => open,
|
| 724 |
|
|
|
| 725 |
|
|
oOverflow => open,
|
| 726 |
|
|
oUnderflow => open
|
| 727 |
|
|
);
|
| 728 |
|
|
end generate;
|
| 729 |
|
|
end generate;
|
| 730 |
|
|
|
| 731 |
|
|
H5_gen_var : if gH_IS_CONST(5) = '0' generate
|
| 732 |
|
|
H5_gen_var_shiftreg : if gUSE_BRAM_AS_LARGE_SHIFTREG = false generate
|
| 733 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 734 |
|
|
GENERIC map(
|
| 735 |
|
|
gBUS_WIDTH => 32,
|
| 736 |
|
|
gNB_PIPELINES => 64 * gBASE_DELAY)
|
| 737 |
|
|
PORT map(
|
| 738 |
|
|
iClk => iClk,
|
| 739 |
|
|
iInput => '0',
|
| 740 |
|
|
oDelayed_output => open,
|
| 741 |
|
|
ivInput => ivH5,
|
| 742 |
|
|
ovDelayed_output => svH5
|
| 743 |
|
|
);
|
| 744 |
|
|
end generate;
|
| 745 |
|
|
|
| 746 |
|
|
H5_gen_var_bram : if gUSE_BRAM_AS_LARGE_SHIFTREG = true generate
|
| 747 |
|
|
SyncReset_inst : SyncReset
|
| 748 |
|
|
port map(
|
| 749 |
|
|
iClk => iClk,
|
| 750 |
|
|
iAsyncReset => iRst_async,
|
| 751 |
|
|
oSyncReset => svResetHShiftFifo_sync(5)
|
| 752 |
|
|
);
|
| 753 |
|
|
|
| 754 |
|
|
sync_fifo_infer_inst : sync_fifo_infer
|
| 755 |
|
|
generic map(
|
| 756 |
|
|
gADDRESS_WIDTH => 8,
|
| 757 |
|
|
gDATA_WIDTH => 32
|
| 758 |
|
|
)
|
| 759 |
|
|
port map(
|
| 760 |
|
|
iClk => iClk,
|
| 761 |
|
|
iReset_sync => svResetHShiftFifo_sync(5),
|
| 762 |
|
|
|
| 763 |
|
|
ivProgFullTh => conv_std_logic_vector(2**8-3, 8),
|
| 764 |
|
|
ivProgEmptyTh => conv_std_logic_vector(2, 8),
|
| 765 |
|
|
|
| 766 |
|
|
iWrEn => iValid,
|
| 767 |
|
|
iRdEn => sHShiftFifoRdEn,
|
| 768 |
|
|
ivDataIn => ivH5,
|
| 769 |
|
|
ovDataOut => svH5,
|
| 770 |
|
|
oDataOutValid => open,
|
| 771 |
|
|
|
| 772 |
|
|
oFull => open,
|
| 773 |
|
|
oEmpty => open,
|
| 774 |
|
|
oAlmostFull => open,
|
| 775 |
|
|
oAlmostEmpty => open,
|
| 776 |
|
|
oProgFull => open,
|
| 777 |
|
|
oProgEmpty => open,
|
| 778 |
|
|
|
| 779 |
|
|
oOverflow => open,
|
| 780 |
|
|
oUnderflow => open
|
| 781 |
|
|
);
|
| 782 |
|
|
end generate;
|
| 783 |
|
|
end generate;
|
| 784 |
|
|
|
| 785 |
|
|
H6_gen_var : if gH_IS_CONST(6) = '0' generate
|
| 786 |
|
|
H6_gen_var_shiftreg : if gUSE_BRAM_AS_LARGE_SHIFTREG = false generate
|
| 787 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 788 |
|
|
GENERIC map(
|
| 789 |
|
|
gBUS_WIDTH => 32,
|
| 790 |
|
|
gNB_PIPELINES => 64 * gBASE_DELAY)
|
| 791 |
|
|
PORT map(
|
| 792 |
|
|
iClk => iClk,
|
| 793 |
|
|
iInput => '0',
|
| 794 |
|
|
oDelayed_output => open,
|
| 795 |
|
|
ivInput => ivH6,
|
| 796 |
|
|
ovDelayed_output => svH6
|
| 797 |
|
|
);
|
| 798 |
|
|
end generate;
|
| 799 |
|
|
|
| 800 |
|
|
H6_gen_var_bram : if gUSE_BRAM_AS_LARGE_SHIFTREG = true generate
|
| 801 |
|
|
SyncReset_inst : SyncReset
|
| 802 |
|
|
port map(
|
| 803 |
|
|
iClk => iClk,
|
| 804 |
|
|
iAsyncReset => iRst_async,
|
| 805 |
|
|
oSyncReset => svResetHShiftFifo_sync(6)
|
| 806 |
|
|
);
|
| 807 |
|
|
|
| 808 |
|
|
sync_fifo_infer_inst : sync_fifo_infer
|
| 809 |
|
|
generic map(
|
| 810 |
|
|
gADDRESS_WIDTH => 8,
|
| 811 |
|
|
gDATA_WIDTH => 32
|
| 812 |
|
|
)
|
| 813 |
|
|
port map(
|
| 814 |
|
|
iClk => iClk,
|
| 815 |
|
|
iReset_sync => svResetHShiftFifo_sync(6),
|
| 816 |
|
|
|
| 817 |
|
|
ivProgFullTh => conv_std_logic_vector(2**8-3, 8),
|
| 818 |
|
|
ivProgEmptyTh => conv_std_logic_vector(2, 8),
|
| 819 |
|
|
|
| 820 |
|
|
iWrEn => iValid,
|
| 821 |
|
|
iRdEn => sHShiftFifoRdEn,
|
| 822 |
|
|
ivDataIn => ivH6,
|
| 823 |
|
|
ovDataOut => svH6,
|
| 824 |
|
|
oDataOutValid => open,
|
| 825 |
|
|
|
| 826 |
|
|
oFull => open,
|
| 827 |
|
|
oEmpty => open,
|
| 828 |
|
|
oAlmostFull => open,
|
| 829 |
|
|
oAlmostEmpty => open,
|
| 830 |
|
|
oProgFull => open,
|
| 831 |
|
|
oProgEmpty => open,
|
| 832 |
|
|
|
| 833 |
|
|
oOverflow => open,
|
| 834 |
|
|
oUnderflow => open
|
| 835 |
|
|
);
|
| 836 |
|
|
end generate;
|
| 837 |
|
|
end generate;
|
| 838 |
|
|
|
| 839 |
|
|
H7_gen_var : if gH_IS_CONST(7) = '0' generate
|
| 840 |
|
|
H7_gen_var_shiftreg : if gUSE_BRAM_AS_LARGE_SHIFTREG = false generate
|
| 841 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 842 |
|
|
GENERIC map(
|
| 843 |
|
|
gBUS_WIDTH => 32,
|
| 844 |
|
|
gNB_PIPELINES => 64 * gBASE_DELAY)
|
| 845 |
|
|
PORT map(
|
| 846 |
|
|
iClk => iClk,
|
| 847 |
|
|
iInput => '0',
|
| 848 |
|
|
oDelayed_output => open,
|
| 849 |
|
|
ivInput => ivH7,
|
| 850 |
|
|
ovDelayed_output => svH7
|
| 851 |
|
|
);
|
| 852 |
|
|
end generate;
|
| 853 |
|
|
|
| 854 |
|
|
H7_gen_var_bram : if gUSE_BRAM_AS_LARGE_SHIFTREG = true generate
|
| 855 |
|
|
SyncReset_inst : SyncReset
|
| 856 |
|
|
port map(
|
| 857 |
|
|
iClk => iClk,
|
| 858 |
|
|
iAsyncReset => iRst_async,
|
| 859 |
|
|
oSyncReset => svResetHShiftFifo_sync(7)
|
| 860 |
|
|
);
|
| 861 |
|
|
|
| 862 |
|
|
sync_fifo_infer_inst : sync_fifo_infer
|
| 863 |
|
|
generic map(
|
| 864 |
|
|
gADDRESS_WIDTH => 8,
|
| 865 |
|
|
gDATA_WIDTH => 32
|
| 866 |
|
|
)
|
| 867 |
|
|
port map(
|
| 868 |
|
|
iClk => iClk,
|
| 869 |
|
|
iReset_sync => svResetHShiftFifo_sync(7),
|
| 870 |
|
|
|
| 871 |
|
|
ivProgFullTh => conv_std_logic_vector(2**8-3, 8),
|
| 872 |
|
|
ivProgEmptyTh => conv_std_logic_vector(2, 8),
|
| 873 |
|
|
|
| 874 |
|
|
iWrEn => iValid,
|
| 875 |
|
|
iRdEn => sHShiftFifoRdEn,
|
| 876 |
|
|
ivDataIn => ivH7,
|
| 877 |
|
|
ovDataOut => svH7,
|
| 878 |
|
|
oDataOutValid => open,
|
| 879 |
|
|
|
| 880 |
|
|
oFull => open,
|
| 881 |
|
|
oEmpty => open,
|
| 882 |
|
|
oAlmostFull => open,
|
| 883 |
|
|
oAlmostEmpty => open,
|
| 884 |
|
|
oProgFull => open,
|
| 885 |
|
|
oProgEmpty => open,
|
| 886 |
|
|
|
| 887 |
|
|
oOverflow => open,
|
| 888 |
|
|
oUnderflow => open
|
| 889 |
|
|
);
|
| 890 |
|
|
end generate;
|
| 891 |
|
|
end generate;
|
| 892 |
|
|
|
| 893 |
|
|
process (iClk)
|
| 894 |
|
|
begin
|
| 895 |
|
|
if rising_edge(iClk) then
|
| 896 |
|
|
ovH0 <= svAPipe(64) + svH0;
|
| 897 |
|
|
ovH1 <= svBPipe(64) + svH1;
|
| 898 |
|
|
ovH2 <= svCPipe(64) + svH2;
|
| 899 |
|
|
ovH3 <= svDPipe(64) + svH3;
|
| 900 |
|
|
ovH4 <= svEPipe(64) + svH4;
|
| 901 |
|
|
ovH5 <= svFPipe(64) + svH5;
|
| 902 |
|
|
ovH6 <= svGPipe(64) + svH6;
|
| 903 |
|
|
ovH7 <= svHPipe(64) + svH7;
|
| 904 |
|
|
end if;
|
| 905 |
|
|
end process;
|
| 906 |
|
|
|
| 907 |
|
|
OUT_VALID_gen : if gOUT_VALID_GEN = true generate
|
| 908 |
|
|
pipelines_without_reset_inst: pipelines_without_reset
|
| 909 |
|
|
GENERIC map(
|
| 910 |
|
|
gBUS_WIDTH => 1,
|
| 911 |
|
|
gNB_PIPELINES => (64 * gBASE_DELAY + 1))
|
| 912 |
|
|
PORT map(
|
| 913 |
|
|
iClk => iClk,
|
| 914 |
|
|
iInput => iValid,
|
| 915 |
|
|
oDelayed_output => oValid,
|
| 916 |
|
|
ivInput => (others=>'0'),
|
| 917 |
|
|
ovDelayed_output => open
|
| 918 |
|
|
);
|
| 919 |
|
|
end generate;
|
| 920 |
|
|
|
| 921 |
|
|
end behavioral;
|
| 922 |
|
|
|
