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[/] [btc_dsha256/] [trunk/] [rtl/] [vhdl/] [sha256core/] [sha_256_pkg.vhd] - Blame information for rev 3

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1 3 nuxi1209
------------------------------------------------------------------- 
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--                                                               --
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--  Copyright (C) 2013 Author and VariStream Studio              --
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--  Author : Yu Peng                                             --
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--                                                               -- 
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--  This source file may be used and distributed without         -- 
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--  restriction provided that this copyright statement is not    -- 
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--  removed from the file and that any derivative work contains  -- 
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--  the original copyright notice and the associated disclaimer. -- 
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--                                                               -- 
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--  This source file is free software; you can redistribute it   -- 
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--  and/or modify it under the terms of the GNU Lesser General   -- 
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--  Public License as published by the Free Software Foundation; -- 
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--  either version 2.1 of the License, or (at your option) any   -- 
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--  later version.                                               -- 
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--                                                               -- 
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--  This source is distributed in the hope that it will be       -- 
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--  useful, but WITHOUT ANY WARRANTY; without even the implied   -- 
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--  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      -- 
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--  PURPOSE.  See the GNU Lesser General Public License for more -- 
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--  details.                                                     -- 
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--                                                               -- 
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--  You should have received a copy of the GNU Lesser General    -- 
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--  Public License along with this source; if not, download it   -- 
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--  from http://www.opencores.org/lgpl.shtml                     -- 
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--                                                               -- 
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-------------------------------------------------------------------
28 2 nuxi1209
 
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.std_logic_arith.all;
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package sha_256_pkg is
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        type tDwordArray is array (natural range<>) of std_logic_vector(31 downto 0);
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        function sigma_0 (signal x : in std_logic_vector) return std_logic_vector;
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        function sigma_1 (signal x : in std_logic_vector) return std_logic_vector;
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        function sum_0 (signal x : in std_logic_vector) return std_logic_vector;
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        function sum_1 (signal x : in std_logic_vector) return std_logic_vector;
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        function chi (signal x : in std_logic_vector;
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                                signal y : in std_logic_vector;
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                                signal z : in std_logic_vector) return std_logic_vector;
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        function maj (signal x : in std_logic_vector;
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                                signal y : in std_logic_vector;
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                                signal z : in std_logic_vector) return std_logic_vector;
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        function getW_IS_CONST (is_const : in std_logic_vector) return std_logic_vector;
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        function conv_str_to_msg (str : in string) return tDwordArray;
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end sha_256_pkg;
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package body sha_256_pkg is
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function sigma_0 (signal x : in std_logic_vector) return std_logic_vector is
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        variable tmp_0 : std_logic_vector(31 downto 0);
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        variable tmp_1 : std_logic_vector(31 downto 0);
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        variable tmp_2 : std_logic_vector(31 downto 0);
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        variable r : std_logic_vector(31 downto 0);
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begin
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        tmp_0 := x(6 downto 0) & x(31 downto 7);
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        tmp_1 := x(17 downto 0) & x(31 downto 18);
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        tmp_2 := "000" & x(31 downto 3);
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        r := tmp_0 xor tmp_1 xor tmp_2;
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        return r;
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end sigma_0;
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function sigma_1 (signal x : in std_logic_vector) return std_logic_vector is
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        variable tmp_0 : std_logic_vector(31 downto 0);
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        variable tmp_1 : std_logic_vector(31 downto 0);
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        variable tmp_2 : std_logic_vector(31 downto 0);
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        variable r : std_logic_vector(31 downto 0);
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begin
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        tmp_0 := x(16 downto 0) & x(31 downto 17);
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        tmp_1 := x(18 downto 0) & x(31 downto 19);
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        tmp_2 := "0000000000" & x(31 downto 10);
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        r := tmp_0 xor tmp_1 xor tmp_2;
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        return r;
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end sigma_1;
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function chi (signal x : in std_logic_vector;
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        signal y : in std_logic_vector;
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        signal z : in std_logic_vector) return std_logic_vector is
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    variable r : std_logic_vector(31 downto 0);
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begin
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        r := (x and y) xor (not(x) and z);
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        return r;
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end chi;
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function maj (signal x : in std_logic_vector;
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        signal y : in std_logic_vector;
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        signal z : in std_logic_vector) return std_logic_vector is
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        variable r : std_logic_vector(31 downto 0);
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begin
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        r := (x and y) xor (x and z) xor (y and z);
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        return r;
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end maj;
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function sum_0 (signal x : in std_logic_vector) return std_logic_vector is
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        variable tmp_0 : std_logic_vector(31 downto 0);
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        variable tmp_1 : std_logic_vector(31 downto 0);
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        variable tmp_2 : std_logic_vector(31 downto 0);
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        variable r : std_logic_vector(31 downto 0);
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begin
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        tmp_0 := x(1 downto 0) & x(31 downto 2);
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        tmp_1 := x(12 downto 0) & x(31 downto 13);
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        tmp_2 := x(21 downto 0) & x(31 downto 22);
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        r := tmp_0 xor tmp_1 xor tmp_2;
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        return r;
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end sum_0;
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function sum_1 (signal x : in std_logic_vector) return std_logic_vector is
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        variable tmp_0 : std_logic_vector(31 downto 0);
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        variable tmp_1 : std_logic_vector(31 downto 0);
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        variable tmp_2 : std_logic_vector(31 downto 0);
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        variable r : std_logic_vector(31 downto 0);
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begin
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        tmp_0 := x(5 downto 0) & x(31 downto 6);
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        tmp_1 := x(10 downto 0) & x(31 downto 11);
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        tmp_2 := x(24 downto 0) & x(31 downto 25);
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        r := tmp_0 xor tmp_1 xor tmp_2;
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        return r;
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end sum_1;
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function getW_IS_CONST (is_const : in std_logic_vector) return std_logic_vector is
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        variable r : std_logic_vector(0 to 63);
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begin
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        for i in 0 to 15 loop
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                r(i) := is_const(i);
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        end loop;
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        for i in 16 to 63 loop
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                r(i) := r(i-16) and r(i-15) and r(i-7) and r(i-2);
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        end loop;
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        return r;
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end getW_IS_CONST;
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function conv_str_to_msg (str : in string) return tDwordArray is
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        variable str_len : integer := str'length;
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        variable retval : tDwordArray(0 to 15) := (others=>(others=>'0'));
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begin
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        if str_len > 0 then
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                for i in 0 to (str_len - 1) loop
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                        retval(i / 4)(((4 - (i mod 4)) * 8 - 1) downto ((3 - (i mod 4)) * 8)) := conv_std_logic_vector(character'pos(str(i + 1)), 8);
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                end loop;
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        end if;
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        retval(str_len / 4)(((4 - (str_len mod 4)) * 8 - 1) downto ((3 - (str_len mod 4)) * 8)) := X"80";
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        retval(15) := conv_std_logic_vector((str_len * 8), 32);
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        return retVal;
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end conv_str_to_msg;
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end sha_256_pkg;

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