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[/] [btcminer/] [trunk/] [fpga/] [miner130.v] - Blame information for rev 2

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1 2 ZTEX
/*!
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   btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code for ZTEX USB-FPGA Module 1.15b (one double hash pipe)
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   Copyright (C) 2011 ZTEX GmbH
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   http://www.ztex.de
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License version 3 as
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   published by the Free Software Foundation.
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   This program is distributed in the hope that it will be useful, but
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   WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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   General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
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module miner130 (clk, reset,  midstate, data,  golden_nonce, nonce2, hash2);
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        parameter NONCE_OFFS = 32'd0;
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        parameter NONCE_INCR = 32'd1;
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        input clk, reset;
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        input [255:0] midstate;
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        input [95:0] data;
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        output reg [31:0] golden_nonce, nonce2, hash2;
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        reg [31:0] nonce;
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        wire [255:0] hash;
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        reg [7:0] cnt = 8'd0;
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        reg feedback = 1'b0;
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        reg is_golden_nonce;
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        reg feedback_b1, feedback_b2, feedback_b3, feedback_b4, feedback_b5, feedback_b6, reset_b1, reset_b2;
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        reg [255:0] state_buf;
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        reg [511:0] data_buf;
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        sha256_pipe129 p (
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                .clk(clk),
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                .state(state_buf),
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                .data(data_buf),
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                .hash(hash)
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        );
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        always @ (posedge clk)
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        begin
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                if ( cnt == 8'd129 )
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                begin
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                    feedback <= ~feedback;
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                    cnt <= 8'd0;
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                end else begin
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                    cnt <= cnt + 8'd1;
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                end
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                if ( feedback_b1 )
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                begin
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                    data_buf <= { 256'h0000010000000000000000000000000000000000000000000000000080000000,
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                                  hash[`IDX(7)] + midstate[`IDX(7)],
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                                  hash[`IDX(6)] + midstate[`IDX(6)],
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                                  hash[`IDX(5)] + midstate[`IDX(5)],
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                                  hash[`IDX(4)] + midstate[`IDX(4)],
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                                  hash[`IDX(3)] + midstate[`IDX(3)],
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                                  hash[`IDX(2)] + midstate[`IDX(2)],
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                                  hash[`IDX(1)] + midstate[`IDX(1)],
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                                  hash[`IDX(0)] + midstate[`IDX(0)]
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                                };
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                end else begin
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                    data_buf <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data};
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                end
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                if ( feedback_b2 )
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                begin
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                    state_buf <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
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                end else begin
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                    state_buf <= midstate;
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                end
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                if ( reset_b1 )
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                begin
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                    nonce <= NONCE_OFFS;
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                end else if ( ! feedback_b3 )
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                begin
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                    nonce <= nonce + NONCE_INCR;
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                end
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                if ( reset_b2 )
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                begin
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                    golden_nonce <= 32'd0;
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                end else if ( is_golden_nonce )
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                begin
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                    golden_nonce <= nonce2;
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                end
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                if ( ! feedback_b4 )
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                begin
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                    hash2 <= hash[255:224];
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                end
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                if ( ! feedback_b5 )
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                begin
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                    nonce2 <= nonce;
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                end
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                if ( ! feedback_b6 )
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                begin
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                    is_golden_nonce <= hash[255:224] == 32'ha41f32e7;
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                end
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                feedback_b1 <= feedback;
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                feedback_b2 <= feedback;
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                feedback_b3 <= feedback;
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                feedback_b4 <= feedback;
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                feedback_b5 <= feedback;
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                feedback_b6 <= feedback;
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                reset_b1 <= reset;
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                reset_b2 <= reset;
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        end
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endmodule

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