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// The synthesis directives "translate_off/translate_on" specified below are

// supported by Xilinx, Mentor Graphics and Synplicity synthesis

// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file blk_mem_gen_v2_7.v when simulating

// the core, blk_mem_gen_v2_7. When compiling the wrapper file, be sure to

// reference the XilinxCoreLib Verilog simulation library. For detailed

// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module blk_mem_gen_v2_7(

        clka,

        dina,

        addra,

        ena,

        wea,

        douta,

        clkb,

        dinb,

        addrb,

        enb,

        web,

        doutb);

input clka;

input [15 : 0] dina;

input [15 : 0] addra;

input ena;

input [0 : 0] wea;

output [15 : 0] douta;

input clkb;

input [15 : 0] dinb;

input [15 : 0] addrb;

input enb;

input [0 : 0] web;

output [15 : 0] doutb;

// synthesis translate_off

      BLK_MEM_GEN_V2_7 #(

                .C_ADDRA_WIDTH(16),

                .C_ADDRB_WIDTH(16),

                .C_ALGORITHM(1),

                .C_BYTE_SIZE(9),

                .C_COMMON_CLK(0),

                .C_DEFAULT_DATA("0"),

                .C_DISABLE_WARN_BHV_COLL(0),

                .C_DISABLE_WARN_BHV_RANGE(0),

                .C_FAMILY("spartan3"),

                .C_HAS_ENA(1),

                .C_HAS_ENB(1),

                .C_HAS_MEM_OUTPUT_REGS_A(0),

                .C_HAS_MEM_OUTPUT_REGS_B(0),

                .C_HAS_MUX_OUTPUT_REGS_A(0),

                .C_HAS_MUX_OUTPUT_REGS_B(0),

                .C_HAS_REGCEA(0),

                .C_HAS_REGCEB(0),

                .C_HAS_SSRA(0),

                .C_HAS_SSRB(0),

                .C_INIT_FILE_NAME("blk_mem_gen_v2_7.mif"),

                .C_LOAD_INIT_FILE(1),

                .C_MEM_TYPE(2),

                .C_MUX_PIPELINE_STAGES(0),

                .C_PRIM_TYPE(1),

                .C_READ_DEPTH_A(40000),

                .C_READ_DEPTH_B(40000),

                .C_READ_WIDTH_A(16),

                .C_READ_WIDTH_B(16),

                .C_SIM_COLLISION_CHECK("ALL"),

                .C_SINITA_VAL("0"),

                .C_SINITB_VAL("0"),

                .C_USE_BYTE_WEA(0),

                .C_USE_BYTE_WEB(0),

                .C_USE_DEFAULT_DATA(0),

                .C_USE_ECC(0),

                .C_USE_RAMB16BWER_RST_BHV(0),

                .C_WEA_WIDTH(1),

                .C_WEB_WIDTH(1),

                .C_WRITE_DEPTH_A(40000),

                .C_WRITE_DEPTH_B(40000),

                .C_WRITE_MODE_A("WRITE_FIRST"),

                .C_WRITE_MODE_B("WRITE_FIRST"),

                .C_WRITE_WIDTH_A(16),

                .C_WRITE_WIDTH_B(16),

                .C_XDEVICEFAMILY("spartan3"))

        inst (

                .CLKA(clka),

                .DINA(dina),

                .ADDRA(addra),

                .ENA(ena),

                .WEA(wea),

                .DOUTA(douta),

                .CLKB(clkb),

                .DINB(dinb),

                .ADDRB(addrb),

                .ENB(enb),

                .WEB(web),

                .DOUTB(doutb),

                .REGCEA(),

                .SSRA(),

                .REGCEB(),

                .SSRB(),

                .DBITERR(),

                .SBITERR());

// synthesis translate_on

endmodule